Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, a top portion of the substrate forming a gate structure, a first interlayer dielectric layer formed on the substrate exposed by the gate structure, the first interlayer dielectric layer covering sidewalls of the gate structure, a top portion of the gate structure and the first interlayer dielectric layer forming an etch stop layer, a top portion of the etch stop layer having a second interlayer dielectric layer; forming a first opening exposing the etch stop layer in the second interlayer dielectric layer, the first opening being located above the first interlayer dielectric layer between adjacent gate structures; forming a barrier layer on sidewalls of the first opening; forming a second opening through the etch stop layer and the first interlayer dielectric layer at a bottom of the first opening; removing the barrier layer; forming a conductive plug in the first opening and the second opening, the conductive plug including a first conductive plug in the first opening and a second conductive plug in the second opening. The uniformity of the longitudinal dimension of the first conductive plug is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on top of the substrate; source / drain doped regions located in the substrate on both sides of the gate structure; a first interlayer dielectric layer located on the exposed substrate of the gate structure, and the first interlayer dielectric layer covering the sidewalls of the gate structure; an etch stop layer located on top of the gate structure and the first interlayer dielectric layer; a second interlayer dielectric layer located on top of the etch stop layer; and a conductive plug penetrating the first interlayer dielectric layer, the etch stop layer, and the second interlayer dielectric layer between adjacent gate structures and electrically connected to the source / drain doped regions. The conductive plug includes a first conductive plug located in the first interlayer dielectric layer and the etch stop layer, and a second conductive plug located in the second interlayer dielectric layer. The sidewall of the second conductive plug is recessed relative to the sidewall of the first conductive plug. The bottom of the second conductive plug is connected to the top of the first conductive plug and extends to cover a portion of the top of the etch stop layer on the side of the first conductive plug.

[0006] This invention provides a semiconductor structure and a method for forming the same, comprising: providing a substrate, wherein a gate structure is formed on the top of the substrate, source and drain doped regions are formed in the substrate on both sides of the gate structure, a first interlayer dielectric layer is formed on the exposed substrate of the gate structure, the first interlayer dielectric layer covers the sidewalls of the gate structure, an etch stop layer is formed on top of the gate structure and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on top of the etch stop layer; and a first opening is formed in the second interlayer dielectric layer to expose the etch stop layer, the first opening being located between adjacent gate structures along a direction perpendicular to the extension direction of the gate structure. Above the first interlayer dielectric layer; a barrier layer is formed on the sidewall of the first opening; after forming the barrier layer, a second opening is formed that penetrates the bottom of the first opening and the first interlayer dielectric layer, the second opening exposing the source / drain doped region, the top of the second opening communicating with the bottom of the first opening, and the sidewall of the second opening protruding relative to the sidewall of the first opening; after forming the second opening, the barrier layer is removed; after removing the barrier layer, conductive plugs are formed in the first opening and the second opening, the conductive plugs including a first conductive plug located in the first opening and a second conductive plug located in the second opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. A first opening exposing an etch stop layer is formed in a second interlayer dielectric layer. The first opening is located above the first interlayer dielectric layer between adjacent gate structures in a direction perpendicular to the extension direction of the gate structure. After a barrier layer is formed on the sidewall of the first opening, a second opening is formed that penetrates the bottom of the first opening and the etch stop layer and the first interlayer dielectric layer. The top of the second opening is connected to the bottom of the first opening, and the sidewall of the second opening protrudes relative to the sidewall of the first opening. The etch stop layer in this embodiment of the invention can serve as an etch stop layer. By forming a first opening in the second interlayer dielectric layer that exposes the etch stop layer, the longitudinal dimension of the first conductive plug formed in the first opening is defined, ensuring that the longitudinal dimension of the first conductive plug meets process requirements and improves the uniformity of the longitudinal dimension of the first conductive plug. Before forming the second opening, a barrier layer is formed on the sidewall of the first opening. The barrier layer covers the sidewall of the second interlayer dielectric layer exposed by the first opening, i.e., the barrier layer occupies part of the space of the first opening, allowing the second opening to be formed in the etch stop layer and the first interlayer dielectric layer exposed by the barrier layer. Correspondingly, the sidewall of the second opening protrudes relative to the sidewall of the first opening. This allows the lateral dimension of the second conductive plug formed in the second opening to meet process requirements while increasing the lateral dimension of the first conductive plug formed in the first opening. This increases the contact area between the first conductive plug and other interconnect structures subsequently formed on top of the first conductive plug, thereby reducing the contact resistance between the first conductive plug and the corresponding interconnect structure, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0013] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1A substrate 10 is provided, on which a gate structure 18 is formed. Source and drain doped regions 17 are formed in the substrate on both sides of the gate structure 18. A first interlayer dielectric layer 11 is formed on the exposed substrate of the gate structure 18. The first interlayer dielectric layer 11 covers the sidewalls of the gate structure 18. An etch stop layer 13 is formed on top of the gate structure 18 and the first interlayer dielectric layer 11. A second interlayer dielectric layer 14 is formed on top of the etch stop layer 13. A hard mask layer 15 with a mask opening 16 is formed on top of the second interlayer dielectric layer 14 between adjacent gate structures 18.

[0015] refer to Figure 2 Using the hard mask layer 15 as a mask, the second interlayer dielectric layer 14, the etching stop layer 13 and the first interlayer dielectric layer 11 are sequentially etched along the mask opening 16 to form a groove 19 that exposes the top of the source / drain doped region 17.

[0016] refer to Figure 3 A filling layer 20 is formed on top of the hard mask layer 15 and in the groove 19.

[0017] refer to Figure 4 Remove the fill layer 20 on top of the hard mask layer 15 and a portion of the fill layer 20 in the groove 19. The remaining fill layer 20 covers the sidewall of the etching stop layer 13 and exposes the sidewall or part of the sidewall of the second interlayer dielectric layer 14 and the hard mask layer 15.

[0018] refer to Figure 5 The sidewalls of the second interlayer dielectric layer 14 and the hard mask layer 15 exposed by the filling layer 20 are laterally etched in a direction parallel to the surface of the substrate 10 and perpendicular to the sidewall of the gate structure 18, forming an opening 30 in the second interlayer dielectric layer 14. The sidewall of the opening 30 protrudes outward relative to the sidewall of the groove 19.

[0019] in, Figure 5 The dashed lines in the figure indicate the positions of the sidewalls of the second interlayer dielectric layer 14 and the hard mask layer 15 exposed by the filler layer 20 before lateral etching.

[0020] refer to Figure 6 Remove the filling layer 20 and hard mask layer 15 from the groove 19.

[0021] Research has revealed that, due to the influence of the pattern density of the grooves 19 in different regions, the thickness of the filler layer 20 removed during the process of removing a portion of the filler layer 20 in the grooves 19 is easily uneven. Consequently, during the lateral etching of the sidewalls of the second interlayer dielectric layer 14 and the hard mask layer 15 exposed by the filler layer 20, the longitudinal dimension d of the opening 30 formed in the second interlayer dielectric layer is easily uneven, thus affecting the performance of the semiconductor structure.

[0022] Subsequently, conductive plugs are formed in the opening 30 and the groove 19. Correspondingly, the longitudinal dimension uniformity of the first conductive plug formed in the opening 30 is poor, which has an adverse effect on the performance of the semiconductor structure.

[0023] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a gate structure on the top of the substrate, forming source and drain doped regions in the substrate on both sides of the gate structure, forming a first interlayer dielectric layer on the exposed substrate of the gate structure, the first interlayer dielectric layer covering the sidewalls of the gate structure, forming an etch stop layer on top of the gate structure and the first interlayer dielectric layer, and forming a second interlayer dielectric layer on top of the etch stop layer; forming a first opening in the second interlayer dielectric layer exposing the etch stop layer, the first opening being located adjacent to the gate structure along a direction perpendicular to the extension direction of the gate structure. Above the first interlayer dielectric layer between the structures; a barrier layer is formed on the sidewall of the first opening; after forming the barrier layer, a second opening is formed that penetrates the bottom of the first opening and the first interlayer dielectric layer, the second opening exposing the source / drain doped region, the top of the second opening communicating with the bottom of the first opening, and the sidewall of the second opening protruding relative to the sidewall of the first opening; after forming the second opening, the barrier layer is removed; after removing the barrier layer, conductive plugs are formed in the first opening and the second opening, the conductive plugs including a first conductive plug located in the first opening and a second conductive plug located in the second opening.

[0024] The etch stop layer in this embodiment of the invention can serve as an etch stop layer. By forming a first opening in the second interlayer dielectric layer that exposes the etch stop layer, the longitudinal dimension of the first conductive plug formed in the first opening is defined, ensuring that the longitudinal dimension of the first conductive plug meets process requirements and improving the uniformity of the longitudinal dimension of the first conductive plug. Before forming the second opening, a barrier layer is formed on the sidewall of the first opening. The barrier layer covers the sidewall of the second interlayer dielectric layer exposed by the first opening, i.e., the barrier layer occupies part of the space of the first opening, allowing the second opening to be formed in the etch stop layer and the first interlayer dielectric layer exposed by the barrier layer. Correspondingly, the sidewall of the second opening protrudes relative to the sidewall of the first opening. This allows the lateral dimension of the first conductive plug formed in the first opening to meet process requirements while increasing the lateral dimension of the second conductive plug formed in the second opening. This increases the contact area between the second conductive plug and other interconnect structures subsequently formed on top of the second conductive plug, thereby reducing the contact resistance between the second conductive plug and the corresponding interconnect structure and improving the performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0027] The semiconductor structure includes: a substrate; a gate structure 209 located on top of the substrate; source / drain doped regions 211 located in the substrate on both sides of the gate structure 209; a first interlayer dielectric layer 202 located on the exposed substrate of the gate structure 209, and the first interlayer dielectric layer 202 covering the sidewalls of the gate structure 209; an etch stop layer 204 located on top of the gate structure 209 and the first interlayer dielectric layer 202; a second interlayer dielectric layer 205 located on top of the etch stop layer 204; and a conductive plug 219 penetrating the first interlayer dielectric layer between adjacent gate structures 209. 202, an etch stop layer 204 and a second interlayer dielectric layer 205, and electrically connected to the source / drain doped region 211, the conductive plug 219 includes a second conductive plug 218 located in the first interlayer dielectric layer 202 and the etch stop layer 204, and a first conductive plug 217 located in the second interlayer dielectric layer 205, the sidewall of the second conductive plug 218 is recessed relative to the sidewall of the first conductive plug 217, the bottom of the first conductive plug 217 is connected to the top of the second conductive plug 218, and extends to cover part of the top of the etch stop layer 204 covering the side of the second conductive plug 218.

[0028] The etch stop layer 204 in this embodiment of the invention can serve as an etch stop layer. A first conductive plug 217 is formed in the second interlayer dielectric layer, and the first conductive plug 217 extends to cover a portion of the top of the etch stop layer 204 on the side of the second conductive plug 218. In other words, the bottom of the first conductive plug 217 is flush with the top of the etch stop layer 204, thus defining the longitudinal dimension of the first conductive plug 217. This ensures that the longitudinal dimension of the first conductive plug 217 meets process requirements and improves the uniformity of the longitudinal dimension of the first conductive plug 217. Furthermore, the sidewall of the second conductive plug 218 is recessed relative to the sidewall of the first conductive plug 217, meaning the conductive plug 219 has a T-shaped shape. This allows the lateral dimension of the second conductive plug 218 to meet process requirements while increasing the lateral dimension of the first conductive plug 217. This increases the contact area between the first conductive plug 217 and other interconnect structures formed on the top of the first conductive plug 217, thereby reducing the contact resistance between the first conductive plug and the corresponding interconnect structure and improving the performance of the semiconductor structure.

[0029] The substrate includes a substrate 200 and fins 201 located on the substrate 200. In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0030] In this embodiment, the fin 201 is disposed on the substrate 200, and the material of the fin 201 is the same as that of the substrate, which is silicon.

[0031] In this embodiment, the semiconductor structure further includes an isolation layer (not shown) located on the substrate 200 exposed by the fin 201, and the isolation layer covers part of the sidewall of the fin 201.

[0032] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0033] In this embodiment, the gate structure 209 is used to control the opening and closing of the transistor channel.

[0034] In this embodiment, the gate structure 209 is a metal gate structure.

[0035] The gate structure 209 includes a gate dielectric layer 208 and a gate electrode layer 207 covering the bottom and sidewalls of the gate dielectric layer 208.

[0036] In this embodiment, the material of the gate dielectric layer 208 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0037] The gate electrode layer 207 is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer 207 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer 207 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 207 may only include a work function layer.

[0038] In this embodiment, the source and drain doped regions 211 are located in the fins 201 on both sides of the gate structure 209.

[0039] When the semiconductor device is a PMOS transistor, the material of the source / drain doped region 211 is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the semiconductor device is an NMOS transistor, the material of the source / drain doped region 211 is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.

[0040] In this embodiment, the semiconductor structure further includes a sidewall 203 located on the sidewall of the gate structure 209.

[0041] The sidewall 203 is used to protect the sidewall of the gate structure 209, and the sidewall 203 is also used to define the formation location of the source and drain doped layer 211.

[0042] The sidewall 203 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 203 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 203 is a single-layer structure, and the material of the sidewall 203 is silicon nitride.

[0043] The first interlayer dielectric layer 202 is used to isolate adjacent transistors. The first interlayer dielectric layer 202 is also used to provide space for the second conductive plug 218.

[0044] The first interlayer dielectric layer 202 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the first interlayer dielectric layer 202 is made of silicon oxide.

[0045] The etching stop layer 204 can stop the etching during the etching of the second interlayer dielectric layer 205, which helps to accurately control the bottom position of the first conductive plug 217, making the bottom of the first conductive plug 217 flush with the top of the etching stop layer 204, thereby improving the uniformity of the longitudinal dimensions of the first conductive plug 217.

[0046] In this embodiment, the material of the etch stop layer 204 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch stop layer 204 is silicon nitride.

[0047] The second interlayer dielectric layer 205 is used to electrically isolate the first conductive plug 217. At the same time, the second interlayer dielectric layer 205 also provides space for the first conductive plug 217.

[0048] The second interlayer dielectric layer 205 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the second interlayer dielectric layer 205 is made of silicon oxide.

[0049] The conductive plug 219 is electrically connected to the source / drain doped region 211, thereby enabling the source / drain doped region 211 to be electrically connected to external circuits or other interconnection structures.

[0050] The first conductive plug 217 is electrically connected to the source / drain doped region 211 via the second conductive plug 218.

[0051] In this embodiment, the conductive plug 219 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the conductive plug 219, thereby reducing power consumption. In other embodiments, the conductive plug can also be made of conductive materials such as cobalt or ruthenium.

[0052] It should be noted that the distance D2 in which the sidewall of the second conductive plug 218 is recessed relative to the sidewall of the first conductive plug 217 should not be too large or too small. Taking the direction perpendicular to the extension direction of the gate structure as the lateral direction, if the distance D2 of the recess of the sidewall of the second conductive plug 218 relative to the sidewall of the first conductive plug 217 is too large, it is easy to cause the lateral dimension of the first conductive plug 217 to be too large, even if the lateral dimension of the second conductive plug 218 meets the process requirements. This increases the risk of leakage between the first conductive plug 217 and the gate structure 209, thereby affecting the performance of the semiconductor structure. If the distance D2 of the recess of the sidewall of the second conductive plug 218 relative to the sidewall of the first conductive plug 217 is too small, even if the lateral dimension of the second conductive plug 218 meets the process requirements, it is easy to cause the lateral dimension of the first conductive plug to be too small. This results in the contact area between the first conductive plug and other interconnect structures subsequently formed on the top of the first conductive plug being too small, making it difficult to reduce the contact resistance between the first conductive plug and the corresponding interconnect structure, thereby reducing the performance of the semiconductor structure. Therefore, in this embodiment, the recessed distance D2 of the sidewall of the second conductive plug 218 relative to the sidewall of the first conductive plug 217 is 2 nanometers to 6 nanometers. For example, the protruding distance D2 of the sidewall of the second conductive plug 218 relative to the sidewall of the first conductive plug 217 is 4 nanometers.

[0053] It should also be noted that the longitudinal thickness D1 of the first conductive plug 217 should not be too large or too small. If the longitudinal thickness D1 of the first conductive plug 217 is too large, it will easily increase the probability of leakage between the first conductive plug 217 and the gate structure 209; if the longitudinal thickness D1 of the first conductive plug 217 is too small, it will increase the probability of the first conductive plug 217 being worn away during the planarization process in the formation process of the first conductive plug 217, thereby failing to achieve the effect of improving electrical properties. Therefore, in this embodiment, the longitudinal thickness of the first conductive plug 217 is 30 nanometers to 60 nanometers. For example, the longitudinal thickness of the first conductive plug 217 is 40 nanometers or 50 nanometers.

[0054] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0055] refer to Figure 8A substrate is provided, on the top of which a gate structure 109 is formed. Source and drain doped regions 111 are formed in the substrate on both sides of the gate structure 109. A first interlayer dielectric layer 102 is formed on the exposed substrate of the gate structure 109. The first interlayer dielectric layer 102 covers the sidewalls of the gate structure 109. An etch stop layer 104 is formed on the top of the gate structure 109 and the first interlayer dielectric layer 102. A second interlayer dielectric layer 105 is formed on the top of the etch stop layer 104.

[0056] The substrate is used to provide a platform for the process.

[0057] The substrate includes a substrate 100 and fins 101 located on the substrate 100. In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0058] In this embodiment, the fin 101 is disposed on the substrate 100, and the material of the fin 101 is the same as that of the substrate 100, which is silicon.

[0059] In other embodiments, when the formation method is used to form a planar transistor, the substrate may also be a planar substrate.

[0060] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 101, forming an isolation layer (not shown) on the substrate 100 exposed by the fin 101, the isolation layer covering part of the sidewall of the fin 101.

[0061] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0062] In this embodiment, the gate structure 109 is a metal gate structure, used to control the opening and closing of the transistor channel.

[0063] The gate structure 109 includes a gate dielectric layer 108 and a gate electrode layer 107 covering the bottom and sidewalls of the gate dielectric layer 108.

[0064] In this embodiment, the material of the gate dielectric layer 108 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0065] The gate electrode layer 107 is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer 107 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer 107 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 107 may only include a work function layer.

[0066] In this embodiment, the gate structure 109 is formed using a process of forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, before the gate structure 109 is formed, the position of the gate structure 109 is occupied by a dummy gate.

[0067] In this embodiment, after forming the pseudo-gate structure, source and drain doped layers 111 are formed in the fins 101 on both sides of the pseudo-gate structure.

[0068] When the formed semiconductor device is a PMOS transistor, the material of the source / drain doped region 111 is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the formed semiconductor device is an NMOS transistor, the material of the source / drain doped region 111 is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.

[0069] It should be noted that, in the step of providing the substrate, the sidewalls of the gate structure 109 are formed with sidewalls 103. Specifically, the sidewalls 103 are formed before the source / drain doped layer 111 is formed.

[0070] The sidewall 103 is used to protect the sidewall of the gate structure 109, and the sidewall 103 is also used to define the formation location of the source and drain doped layer 111.

[0071] The sidewall 103 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 103 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 103 is a single-layer structure, and the material of the sidewall 103 is silicon nitride.

[0072] In this embodiment, a first interlayer dielectric layer 102 is formed on the exposed substrate of the gate structure 109, and the first interlayer dielectric layer 102 covers the sidewall of the gate structure 109. Specifically, the top of the first interlayer dielectric layer 102 is flush with the top of the gate structure 109.

[0073] The first interlayer dielectric layer 102 is used to isolate adjacent transistors. The first interlayer dielectric layer 102 also serves to provide a process basis for the subsequent formation of a second opening exposing the source / drain doped layer 108.

[0074] The first interlayer dielectric layer 102 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the first interlayer dielectric layer 102 is made of silicon oxide.

[0075] In this embodiment, an etch stop layer 104 is formed on top of the gate structure 109 and the first interlayer dielectric layer 102.

[0076] The etching stop layer 104 can serve as an etching stop, providing an etching stop position for the subsequent formation of the first opening in the second interlayer dielectric layer.

[0077] In this embodiment, the material of the etch stop layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch stop layer 104 is silicon nitride.

[0078] In this embodiment, a second interlayer dielectric layer 105 is provided on top of the etching stop layer 104.

[0079] The second interlayer dielectric layer 105 is used to electrically isolate the conductive plugs formed subsequently. At the same time, the second interlayer dielectric layer 105 is also used to provide a process basis for the subsequent formation of the first opening.

[0080] The material of the second interlayer dielectric layer 105 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 105 is silicon oxide.

[0081] In this embodiment, during the step of providing the substrate, a hard mask layer 106 with a mask opening 110 is formed on the top of the second interlayer dielectric layer 105, and the mask opening 110 is located on the top of the second interlayer dielectric layer 105 between adjacent gate structures 109.

[0082] The hard mask layer 106 provides an etching mask for the subsequent formation of a first opening and a second opening between adjacent gate structures 109.

[0083] In this embodiment, the material of the hard mask layer 106 includes one or more of TiN, WDC, and TiO.

[0084] TiN, WDC, and TiO materials, as doped metal mixtures, have the characteristics of high material hardness and can be used as etching masks to form the first and second openings. As an example, the material of the hard mask layer 106 is TiN.

[0085] refer to Figure 9 A first opening 112 is formed in the second interlayer dielectric layer 105 to expose the etch stop layer 104. The first opening 112 is located above the first interlayer dielectric layer 103 between adjacent gate structures 109 in a direction perpendicular to the extension direction of the gate structure 109.

[0086] In this embodiment, during the formation of the first opening 112, the top of the etch stop layer 104 is used as the etch stop position. Therefore, by forming the first opening 112 in the second interlayer dielectric layer 105 to expose the etch stop layer 104, the longitudinal dimension of the first conductive plug subsequently formed in the first opening 112 is defined, so that the longitudinal dimension of the first conductive plug can meet the process requirements and improve the uniformity of the longitudinal dimension of the first conductive plug, thereby improving the performance of the semiconductor structure.

[0087] In this embodiment, in the step of forming the first opening 112, the hard mask layer 106 is used as a mask, and the second interlayer dielectric layer 105 between adjacent gate structures 109 is etched along the mask opening 110, so that the first opening 112 exposing the etch stop layer 104 is formed in the second interlayer dielectric layer 105.

[0088] In this embodiment, the process of etching the second interlayer dielectric layer 105 between adjacent gate structures 109 along the mask opening 110 includes a dry etching process.

[0089] refer to Figures 10 to 11 A barrier layer 115 is formed on the sidewall of the first opening 112.

[0090] In this embodiment, before the second opening is formed, a barrier layer 115 is first formed on the sidewall of the first opening 112. The barrier layer 115 covers the sidewall of the second interlayer dielectric layer 105 exposed by the first opening 112. That is, the barrier layer 115 occupies part of the space of the first opening 112, so that the second opening can be formed in the etch stop layer and the first interlayer dielectric layer exposed by the barrier layer. Accordingly, the sidewall of the second opening formed later protrudes relative to the sidewall of the first opening 112.

[0091] In this embodiment, the step of forming a barrier layer 115 on the sidewall of the first opening 112 includes: forming a barrier material layer 113 covering the bottom and sidewall of the first opening 112, and the top and side of the second interlayer dielectric layer 105; removing the barrier material layer 113 at the bottom of the first opening 112 and the top of the hard mask layer 106, and using the remaining barrier material layer 113 on the sidewall of the first opening 112 as the barrier layer 115.

[0092] In this embodiment, the process of forming the barrier material layer 113 covering the bottom and sidewalls of the first opening 112 and the top and sides of the second interlayer dielectric layer 105 includes an atomic layer deposition process.

[0093] Specifically, the atomic layer deposition process includes multiple atomic layer deposition cycles, which helps to improve the thickness uniformity of the barrier material layer 113, enabling the barrier material layer 113 to cover the bottom and sidewalls of the first opening 112, as well as the top and sides of the second interlayer dielectric layer 105. In addition, the atomic layer deposition process has good gap filling performance and step coverage, which correspondingly improves the conformal coverage capability of the barrier material layer 113.

[0094] In this embodiment, the process of removing the barrier material layer 113 from the bottom of the first opening 112 and the top of the second interlayer dielectric layer 105 includes a dry etching process.

[0095] The dry etching process is an anisotropic dry etching process. In this anisotropic dry etching process, the longitudinal etching rate is much greater than the transverse etching rate, which can obtain a fairly accurate pattern transformation and cause relatively little damage to the barrier layer 115 located on the sidewall of the first opening 112.

[0096] In this embodiment, the material of the barrier layer 115 includes one or more of TiN, WDC, and TiO.

[0097] TiN, WDC, and TiO materials, as alloy materials, have the characteristics of high material hardness and can be used as etching masks to form the second opening. As an example, the material of the barrier layer 115 is TiN.

[0098] In order to reduce the number of process steps and facilitate the removal of the hard mask layer 106 during the subsequent removal of the barrier layer 115, in this embodiment, the barrier layer 115 and the hard mask layer 106 are made of the same material.

[0099] It should be noted that the thickness of the barrier layer 115 should not be too large or too small. If the thickness of the barrier layer 115 is too large, the second opening formed using the barrier layer 115 as a mask may be too small, resulting in an undersized second conductive plug that fails to meet the electrical requirements. If the thickness of the barrier layer 115 is too small, the second opening formed using the barrier layer 115 as a mask may be too large, resulting in an oversized second conductive plug that increases the probability of leakage between the second conductive plug and the gate structure 109, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the barrier layer 115 is 2 nanometers to 6 nanometers. For example, the thickness of the barrier layer 115 is 4 nanometers.

[0100] refer to Figure 12 After the barrier layer 115 is formed, a second opening 116 is formed that penetrates the bottom of the first opening 112 through the etch stop layer 104 and the first interlayer dielectric layer 102. The second opening 116 exposes the source / drain doped region 111. The top of the second opening 116 is connected to the bottom of the first opening 112, and the sidewall of the second opening 116 protrudes relative to the sidewall of the first opening 112.

[0101] The second opening 116 provides space for the subsequent formation of the second conductive plug.

[0102] It should be noted that the sidewall of the second opening 116 protrudes relative to the sidewall of the first opening 112. This allows the lateral dimension of the second conductive plug formed in the second opening to meet the process requirements, while increasing the lateral dimension of the first conductive plug formed in the first opening. This increases the contact area between the first conductive plug and other interconnect structures subsequently formed on top of the first conductive plug, thereby reducing the contact resistance between the first conductive plug and the corresponding interconnect structure and improving the performance of the semiconductor structure.

[0103] In this embodiment, the step of forming a second opening 116 that penetrates the bottom of the first opening 112 through the etch stop layer 104 and the first interlayer dielectric layer 102 includes: using the barrier layer 115 and the hard mask layer 106 as masks, along the first opening 112, removing the etch stop layer 104 and the first interlayer dielectric layer 102 exposed in the first opening 112.

[0104] Specifically, the process of removing the etch stop layer 104 and the first interlayer dielectric layer 102 exposed by the first opening 112 includes a dry etching process.

[0105] refer to Figure 13After forming the second opening 116, the barrier layer 115 is removed.

[0106] Removing the barrier layer 115 provides space for the subsequent formation of the first conductive plug.

[0107] In this embodiment, the process for removing the barrier layer 115 includes a wet etching process.

[0108] The wet etching process is an isotropic dry etching process. This wet etching process possesses the characteristics of isotropic etching and offers advantages such as low process cost, high yield, and good surface uniformity. While ensuring the removal of the barrier layer 115, it also guarantees the sidewall morphology quality of the second interlayer dielectric layer 105.

[0109] In other embodiments, the process for removing the barrier layer may also include a dry etching process.

[0110] Continue to refer to Figure 13 In this embodiment, after the second opening 116 is formed, the hard mask layer 106 is removed.

[0111] Removing the hard mask layer 106 facilitates subsequent grinding of the conductive material layer until the top of the second interlayer dielectric layer 105 is exposed.

[0112] In this embodiment, the barrier layer 115 and the hard mask layer 106 are removed in the same step, which reduces the number of process steps and lowers the process cost.

[0113] refer to Figure 14 After removing the blocking layer 115, conductive plugs 119 are formed in the first opening 112 and the second opening 116. The conductive plugs 119 include a first conductive plug 117 located in the first opening 112 and a second conductive plug 118 located in the second opening 116.

[0114] The conductive plug 119 is electrically connected to the source / drain doped region 111, thereby enabling the source / drain doped region 111 to be electrically connected to external circuits or other interconnection structures.

[0115] The first conductive plug 117 is electrically connected to the source / drain doped region 111 via the second conductive plug 118.

[0116] In this embodiment, the conductive plug 119 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the conductive plug 119, thereby reducing power consumption. In other embodiments, the conductive plug can also be made of conductive materials such as cobalt or ruthenium.

[0117] In this embodiment, the step of forming the conductive plug 119 includes: forming a conductive material layer (not shown) in the first opening 112 and the second opening 116; grinding the conductive material layer until the top of the second interlayer dielectric layer 105 is exposed, and the remaining conductive material layer serves as the conductive plug 119.

[0118] In this embodiment, the process of grinding the conductive material layer until the top of the second interlayer dielectric layer 105 is exposed includes a chemical mechanical polishing process.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The base; The gate structure is located on the top of the base, and the gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The source-drain doped region is located in the base on both sides of the gate structure; The first interlayer dielectric layer is located on the base exposed by the gate structure, and the first interlayer dielectric layer covers the sidewall of the gate structure; The etching stop layer is located on the top of the gate structure and the first interlayer dielectric layer; The second interlayer dielectric layer is located on the top of the etching stop layer; The conductive plug penetrates the first interlayer dielectric layer, the etching stop layer and the second interlayer dielectric layer between adjacent gate structures, and is electrically connected with the source-drain doped region, the conductive plug includes a second conductive plug located in the first interlayer dielectric layer and the etching stop layer, and a first conductive plug located in the second interlayer dielectric layer, the sidewall of the second conductive plug is recessed relative to the sidewall of the first conductive plug, the bottom of the first conductive plug is connected with the top of the second conductive plug, and the part of the top of the etching stop layer covering the side of the second conductive plug is extended. The distance that the sidewall of the second conductive plug is protruded relative to the sidewall of the first conductive plug is 2-6 nanometers.

2. The semiconductor structure of claim 1, wherein, The longitudinal thickness of the first conductive plug is 30-60 nanometers.

3. The semiconductor structure of claim 1, wherein, The material of the conductive plug includes tungsten, cobalt or ruthenium.

4. The semiconductor structure of claim 1, wherein, The material of the etching stop layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride and boron carbon nitride.

5. The semiconductor structure of claim 1, wherein, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; 6. The semiconductor structure of claim 1, wherein, The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. The base is provided, the top of the base is formed with a gate structure, the source-drain doped region is formed in the base on both sides of the gate structure, the first interlayer dielectric layer is formed on the base exposed by the gate structure, the first interlayer dielectric layer covers the sidewall of the gate structure, the etching stop layer is formed on the top of the gate structure and the first interlayer dielectric layer, and the second interlayer dielectric layer is formed on the top of the etching stop layer; 7. A method of forming a semiconductor structure, characterized by, The first opening exposing the etching stop layer is formed in the second interlayer dielectric layer, the first opening is located above the first interlayer dielectric layer between adjacent gate structures in the direction perpendicular to the extending direction of the gate structure; The barrier layer is formed on the sidewall of the first opening; After the barrier layer is formed, the second opening penetrating the etching stop layer and the first interlayer dielectric layer at the bottom of the first opening is formed, the second opening exposes the source-drain doped region, the top of the second opening is connected with the bottom of the first opening, and the sidewall of the second opening is protruded relative to the sidewall of the first opening; After the second opening is formed, the barrier layer is removed. ​ ​ After removing the blocking layer, conductive plugs are formed in the first opening and the second opening. The conductive plugs include a first conductive plug located in the first opening and a second conductive plug located in the second opening.

8. The method of forming a semiconductor structure of claim 7, wherein, In the step of providing the substrate, a hard mask layer with a mask opening is formed on the top of the second interlayer dielectric layer, the mask opening being located on the top of the second interlayer dielectric layer between adjacent gate structures; In the step of forming the first opening, the hard mask layer is used as a mask, and the second interlayer dielectric layer between adjacent gate structures is etched along the mask opening to form a first opening in the second interlayer dielectric layer that exposes the etching stop layer; The step of forming a second opening that extends through the bottom of the first opening and through the etch stop layer and the first interlayer dielectric layer includes: using the barrier layer and the hard mask layer as masks, removing the etch stop layer and the first interlayer dielectric layer exposed by the first opening along the first opening; After the second opening is formed, the hard mask layer is removed.

9. The method of forming a semiconductor structure of claim 7, wherein, The step of forming a barrier layer on the sidewall of the first opening includes: forming a barrier material layer covering the bottom and sidewall of the first opening and the top of the second interlayer dielectric layer; removing the barrier material layer at the bottom of the first opening and the top of the second interlayer dielectric layer, and leaving the remaining barrier material layer on the sidewall of the first opening as the barrier layer.

10. The method of forming a semiconductor structure of claim 9, wherein, The process for forming a barrier material layer covering the bottom and sidewalls of the first opening and the top of the second interlayer dielectric layer includes an atomic layer deposition process.

11. The method of forming a semiconductor structure of claim 9, wherein, The process for removing the barrier material layer at the bottom of the first opening and the top of the hard mask layer includes a dry etching process.

12. The method of forming a semiconductor structure of claim 7, wherein, The material of the barrier layer includes one or more of TiN, WDC, and TiO.

13. The method of forming a semiconductor structure of claim 7, wherein, The thickness of the barrier layer is 2 nanometers to 6 nanometers.

14. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming the barrier layer, the barrier layer and the hard mask layer are made of the same material; After the second opening is formed, the barrier layer and hard mask layer are removed in the same step.

15. The method of forming a semiconductor structure of claim 8, wherein, The material of the hard mask layer includes one or more of TiN, WDC, and TiO.

16. The method of forming a semiconductor structure of claim 7, wherein, The process for removing the barrier layer includes a wet etching process.

17. The method of forming a semiconductor structure of claim 7, wherein, The step of forming conductive plugs in the first opening and the second opening includes: forming a conductive material layer in the first opening and the second opening; grinding the conductive material layer until the top of the second interlayer dielectric layer is exposed, with the remaining conductive material layer serving as a conductive plug.

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