bipolar transistor

Abstract

The present disclosure relates to bipolar transistors. The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacture. The structure includes a first transistor having an inner base, an outer base, and an emitter, and a second transistor having an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor have a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more specifically to heterojunction bipolar transistors and methods of manufacturing them. Background Technology

[0002] A heterojunction bipolar transistor (HBT) is a type of bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions or the collector and base regions, thus forming a heterojunction. HBTs are used in applications such as power amplifiers and cellular devices, and require low collector-base capacitance (Ccb), low base resistance (Rb), high cutoff frequency (fT / fmax), and high breakdown voltage (BVceo). Current integration schemes used to manufacture HBTs result in high Ccb (parasitic capacitance) and high Rb, which is a problem in bipolar technology because it limits the scaling of devices used to improve fT / fmax. Summary of the Invention

[0003] In one aspect of this disclosure, a structure includes: a first transistor including an inner base, an outer base, and an emitter; and a second transistor including an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor include a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

[0004] In one aspect of this disclosure, a structure includes: a first heterojunction bipolar transistor (HJB) comprising an emitter having a first dopant type, an outer base having a second dopant type, and a sub-collector region having the first dopant type; and a second HJB comprising an emitter having the second dopant type, an outer base having the first dopant type, and a sub-collector region having the second dopant type. The outer bases of the first and second HJB transistors comprise a common and continuous semiconductor layer.

[0005] In one aspect of this disclosure, a method includes: forming a first transistor including an inner base, an outer base, and an emitter; and forming a second transistor including an inner base, an outer base, and an emitter, wherein the outer base of the first transistor and the outer base of the second transistor are formed to have a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor. Attached Figure Description

[0006] In the following detailed description, the present disclosure is described with reference to the various accompanying drawings, using non-limiting examples of exemplary embodiments of the present disclosure.

[0007] Figure 1 The structure and corresponding manufacturing process according to aspects of this disclosure are shown.

[0008] Figure 2 The structure and corresponding manufacturing process according to additional aspects of this disclosure are shown.

[0009] Figure 3 The structure and corresponding manufacturing process according to other aspects of this disclosure are shown.

[0010] Figure 4 A flowchart illustrating a process for manufacturing the structure described herein, according to aspects of this disclosure, is shown. Detailed Implementation

[0011] This disclosure relates to semiconductor structures, and more specifically to heterojunction bipolar transistors and methods of fabrication. More specifically, the bipolar transistor can be a coplanar complementary bipolar transistor. In embodiments, the complementary bipolar transistor includes a common, continuous, and coplanar base region, such as an outer base film or layer. Advantageously, the bipolar transistor provides a compact complementary inverter layout, which offers significant area savings compared to conventional devices. For example, the collector contact space is significantly reduced compared to conventional devices. Furthermore, the bipolar transistor eliminates NPN-PNP remnants surrounding the protected device and thus improves device performance, such as fmax.

[0012] In a more specific embodiment, the bipolar device may be a complementary (NPN / PNP) heterojunction bipolar transistor comprising a common (e.g., continuous and coplanar) outer base layer with different doped regions (e.g., N-doped and P-doped regions). The complementary heterojunction bipolar transistor may have two different inner base dopings (e.g., N-type doping / P-type doping), two different emitter dopings, and two different secondary collector wells. The doped outer base regions may be silicided and shorted together via a common base contact to enable circuitry functions such as inverters. Additionally, in embodiments, the PNP transistor may have triple-well isolation beneath the secondary collector region.

[0013] The structures disclosed herein can be fabricated using a variety of different tools and in a variety of ways. However, in general, methods and tools are used to form structures with micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the structures of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned by photolithography on top of the wafer. Specifically, the fabrication of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film onto the mask. Furthermore, as is known in the art, a pre-cleaning process can be used to clean any contaminants from the etched surface. Additionally, as is known in the art, a rapid thermal annealing process can be used, where necessary, to drive in dopants or material layers.

[0014] Figure 1 The structure and corresponding manufacturing process according to aspects of this disclosure are shown. Figure 1 Structure 10 includes complementary heterojunction bipolar transistors 100 and 200 having a shared outer base region 12. In embodiments, the shared outer base region 12 may be planar and include different doping (e.g., N-type doping and P-type doping) for each of the complementary heterojunction bipolar transistors 100 and 200. For example, in embodiments, heterojunction bipolar transistor 100 may be a PNP having an outer base region 12a including P-type doping (e.g., boron); while heterojunction bipolar transistor 200 may be an NPN having an outer base region 12b including N-type doping (e.g., arsenic). Similarly, the inner base regions 14a and 14b of heterojunction bipolar transistors 100 and 200 may have different doping. For example, heterojunction bipolar transistor 100 may have an inner base region 14a including P-type doping (e.g., boron); while heterojunction bipolar transistor 200 may be an NPN having an inner base region 14b including N-type doping (e.g., arsenic).

[0015] More specifically, structure 10 (e.g., heterojunction bipolar transistors 100, 200) may include a semiconductor substrate 16. The semiconductor substrate 16 may be made of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors. The semiconductor substrate 16 may be a single-crystal semiconductor material including any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). In embodiments, the semiconductor substrate 16 may be a p-type substrate. The semiconductor substrate 16 may be a bulk substrate or semiconductor-on-insulator technology as known in the art, and therefore no further explanation is required to fully understand this disclosure.

[0016] The semiconductor substrate 16 may include an n-type triple-well isolation structure 18. In an embodiment, the n-type triple-well isolation structure 18 may be configured for a heterojunction bipolar transistor 200. In an embodiment, the n-type triple-well isolation structure 18 may be formed using a conventional ion implantation process. For example, the n-type triple-well isolation structure 18 may be formed by introducing N-type dopant, for example, by ion implantation of a dopant concentration into the semiconductor substrate 16.

[0017] In ion implantation processes, patterned implantation masks can be used to define selected areas exposed for implantation. The implantation mask may include a layer of photosensitive material, such as an organic photoresist, applied by spin coating, pre-baked, exposed to light projected through the photomask, post-baked, and developed with a chemical developer. The implantation mask has sufficient thickness and blocking capability to prevent the masked area from receiving a dose of implanted ions. The n-type triple-well isolation structure 18 is doped with n-type dopants, such as arsenic (As), phosphorus (P), and antimony (Sb), as well as other suitable examples. An annealing process can be performed to drive the dopants into the semiconductor substrate 16.

[0018] Still referencing Figure 1 The heterojunction bipolar transistors 100 and 200 further include secondary collector regions 20a and 20b, respectively, located in the semiconductor substrate 16. In embodiments, the secondary collector regions 20a and 20b are used for the respective heterojunction bipolar transistors 100 and 200. For example, the secondary collector region 20a of the heterojunction bipolar transistor 100 may be N-type doped, and the secondary collector region 20b of the heterojunction bipolar transistor 200 may be P-type doped. As already noted, the doping of the secondary collector regions 20a and 20b can be provided by ion implantation processes using different masks and different dopant types, therefore no further explanation is required to fully understand this disclosure.

[0019] A trench isolation structure 22 may be provided in the semiconductor substrate 16. In an embodiment, depending on the thickness of the secondary collector regions 20a, 20b, the trench isolation structure 22 may be a shallow trench isolation structure or a deep trench isolation structure. In this regard, the trench isolation structure 22 may be used to isolate the collector regions 20a, 20b from other devices (passive or active) of the structure 10.

[0020] The trench isolation structure 22 can be formed using conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed on the semiconductor substrate 16 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) can be used to transfer the pattern from the patterned photoresist layer to the semiconductor substrate 16 through the openings in the resist to form one or more trenches in the semiconductor substrate 16. After the resist is removed by a conventional oxygen ashing process or other known stripping agents, an insulating material (e.g., an oxide-based material) can be deposited by any conventional deposition process (e.g., chemical vapor deposition (CVD)). Any residual material on the surface of the semiconductor substrate 16 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0021] Figure 1 An insulating material 24 is also shown located on the semiconductor substrate 16, and more specifically on both the secondary collector regions 20a and 20b. In embodiments, the insulating material 24 can be any dielectric material, such as a nitride, an oxide, or a combination thereof. For example, the insulating material 24 can be a stack of oxides and nitrides. The insulating material 24 can be patterned to form trenches 26 exposing the secondary collector regions 20a and 20b for forming inner base regions. Patterning can be used to expose the underlying secondary collector regions 20a and 20b for subsequent formation of collector contacts 28.

[0022] In one embodiment, trench 26 is filled with semiconductor material 30. In another embodiment, semiconductor material 30 may be intrinsic Si. Semiconductor material 30 may be epitaxially grown on the surfaces of secondary collector regions 20a, 20b. Additional semiconductor materials 14a, 14b may be grown on and in contact with the respective secondary collector regions 20a, 20b. In another embodiment, additional semiconductor materials 14a, 14b may serve as the inner base of the respective heterojunction bipolar transistors 100, 200. Additional semiconductor materials 14a, 14b may be SiGe materials doped with different dopants for the respective heterojunction bipolar transistors 100, 200. For example, semiconductor material 14a may be P-doped SiGe, and semiconductor material 14b may be N-doped SiGe. In another embodiment, semiconductor materials 14a, 14b may be epitaxially grown using in-situ doping processes known in the art.

[0023] By way of example, various epitaxial growth process apparatuses can be employed in this application, including, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial growth can be performed at temperatures ranging from 300°C to 800°C. Epitaxial growth can be performed using any known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. Dopants (n-type or p-type, as defined below) are typically added to the precursor gas or gas mixture.

[0024] Still referencing Figure 1 The heterojunction bipolar transistors 100 and 200 also include a shared outer base region 12 (e.g., base regions 12a and 12b) connected to the respective inner base regions 14a and 14b of each heterojunction bipolar transistor 100 and 200. The shared outer base region 12 may be planar and include different doping (e.g., N-type and P-type doping) for each of the heterojunction bipolar transistors 100 and 200. For example, the shared and continuous outer base region 12a includes a P-type doping, such as boron, and the shared outer base region 12b includes an N-type doping, such as arsenic. The shared outer base regions 12a and 12b may be separated by an intrinsic semiconductor material 12c. In embodiments, the intrinsic semiconductor material 12c may be the same as or different from the shared outer base regions 12a and 12b, such as Si or polycrystalline silicon.

[0025] The heterojunction bipolar transistors 100 and 200 also include emitter regions 32a and 32b. In an embodiment, emitter regions 32a and 32b are electrically connected (e.g., in contact) to corresponding inner base regions 14a and 14b. Emitter regions 32a and 32b can be polycrystalline silicon materials with different doping types. For example, emitter region 32a can be an N-type emitter region, and emitter region 32b can be a P-type emitter region. In an embodiment, emitter regions 32a and 32b can be isolated from outer base regions 12a and 12b by sidewall spacers 34 and underlying insulating material. Sidewall spacers 34 can be insulating materials, such as nitrides, oxides, or combinations thereof. Sidewall spacers 34 can be formed by conventional deposition processes (e.g., CVD) and subsequent conventional etching processes (e.g., RIE).

[0026] Contacts 28, 36, and 38 can be formed on the corresponding secondary collector regions 20a and 20b, outer base regions 12a and 12b, and emitter regions 32a and 32b. Prior to forming contacts 28, 36, and 38, silicide contacts 40 can be formed on the exposed semiconductor surfaces of the corresponding secondary collector regions 20a and 20b, outer base regions 12a and 12b, and emitter regions 32a and 32b.

[0027] Those skilled in the art will understand that the silicide process begins by depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over exposed semiconductor material. After material deposition, the structure is heated, allowing the transition metal to react with the exposed silicon (or other semiconductor material described herein) in the active regions of the semiconductor device (e.g., the corresponding secondary collector regions 20a, 20b, outer base regions 12a, 12b, and emitter regions 32a, 32b), forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0028] Contacts 28, 36, 36a, and 38 may be formed in the interlayer dielectric material 42. The interlayer dielectric material 42 may be formed by conventional deposition processes (e.g., CVD). The interlayer dielectric material 42 may be a layer of oxide and nitride materials as known in the art. Contacts 28, 36, 36a, and 38 may be formed by patterning the interlayer dielectric material 42 and subsequently depositing a conductive material in trenches formed by the patterning process, as known in the art, and therefore no further explanation is required to fully understand this disclosure. The conductive material may be tungsten, TiN, TaN, etc. Contact 36a may also span the internal semiconductor material 12c and connect to both emitter regions 32a and 32b.

[0029] Figure 2 The structure and corresponding manufacturing process according to additional aspects of this disclosure are shown. Figure 2 In structure 10a, semiconductor material 12d can be used to separate the outer base regions 12a, 12b. In an embodiment, two contacts 36a can be used to connect to the respective emitter regions 32a, 32b; although a single contact spanning the semiconductor material 12b can also be used. Silicide contacts for the different outer base regions 12a, 12b can also be separated from each other, for example, isolated.

[0030] By performing an etching process to a certain depth and subsequently a deposition process (e.g., CVD), the semiconductor material 12d can extend through the insulator material 24 and contact the secondary collector regions 20a, 20b. In alternative embodiments, the semiconductor material 12d can extend to other depths on the surface or structure of the insulator material 24. The semiconductor material 12d can connect the outer base regions 12a, 12b to the inner base regions 14a, 14b. The semiconductor material 12d can be a selectively epitaxial semiconductor material, more specifically, an intrinsic Si material, such as fully undoped or in-situ doped Si or SiGe material. 12d can also be an insulator material separating the two outer base regions. Figure 2 The remaining features of structure 10a are similar to Figure 1 The features of structure 10 are similar, therefore no further explanation is required to fully understand this disclosure.

[0031] Figure 3 The structure and corresponding manufacturing process according to additional aspects of this disclosure are shown. Figure 3 In structure 10b, the outer base regions 12a and 12b overlap at reference numeral 12e as shown in the figure. In this configuration, the overlapping region 12e will result in a smaller footprint for the complementary heterojunction bipolar transistors 100 and 200. In this embodiment, the outer base region 12b may rise above and overlap with the outer base region 12a; however, it is also expected that the outer base region 12a may rise above and overlap with the outer base region 12b. Furthermore, portions of the outer base regions 12a and 12b remain planar.

[0032] For example, further Figure 3 As shown, the insulating material 24 can separate the outer base regions 12a and 12b. It should be understood that the insulating material 24 can be a stack of dielectric materials such as oxide layers and nitride layers. In this embodiment, the contact 36a can be shared by the emitter regions 32a and 32b; although it is also contemplated that... Figure 2 The two separate contacts described. Additionally, an undoped semiconductor region 20 can be disposed between the secondary collector regions 20a and 20b. Furthermore, a heavily doped region 44 having corresponding n-type and p-type dopants matching the dopant types of the collector regions 20a and 20b can be located below the collector contact 28. The heavily doped region 44 can also be located... Figure 1 and Figure 2 It exists in the structure. Figure 3 The remaining features of structure 10b are similar to Figure 1 The features of structure 10 are similar, therefore no further explanation is required to fully understand this disclosure.

[0033] Figure 4 The diagram shows the representation used for forming Figure 1This is a flowchart of part of the manufacturing process of a heterojunction bipolar transistor. Those skilled in the art will recognize that other manufacturing steps can be used to complete a heterojunction bipolar transistor, and the flowchart focuses on the formation of the base and emitter regions. [Previous information regarding...] Figure 1 The remaining steps are described. Furthermore, Figure 4 Flowcharts can be used for manufacturing Figure 2 The structure shown includes additional etching and deposition steps for forming region 12d.

[0034] In step 400, NPN and PNP base epitaxial semiconductor materials can be grown within the trenches of the underlying secondary collector regions 20a and 20b, which are exposed beneath the insulating material 24. In an embodiment, the epitaxial semiconductor material can be intrinsic Si material and doped SiGe material located on top of the intrinsic Si material. In this way, the inner base regions can be laterally surrounded by the insulating material 24. In an embodiment, the epitaxial materials can be grown using conventional epitaxial growth processes, wherein the upper epitaxial semiconductor material (e.g., SiGe) undergoes a corresponding in-situ doping process to form the inner bases 14a and 14b. A nitride film can be used to protect the underlying insulating material 24 during this epitaxial process, and the nitride film can be removed, for example, by hot phosphoric acid.

[0035] In step 405, an insulating (e.g., oxide) film may be deposited on the epitaxial semiconductor material, followed by a patterning process to expose the underlying epitaxial semiconductor material. A polycrystalline silicon film may be deposited on the insulating material 24. In embodiments, the insulating (e.g., oxide) film and the polycrystalline silicon film may be deposited using conventional deposition methods (e.g., CVD).

[0036] In step 410, the polycrystalline silicon material is subjected to different dopant types using different ion implantation processes as described herein to form the outer base regions 12a and 12b. For example, the ion implantation process for NPN will use a P-type dopant, such as boron, and the ion implantation process for PNP will use an N-type dopant, such as arsenic. It should be understood that the polycrystalline silicon films used for the outer bases 12a and 12b have planar and continuous surfaces. In embodiments, the masks used in the different ion implantation processes will prevent portions of the polycrystalline silicon material from being implanted, thereby forming... Figure 1 The internal semiconductor material 12c is shown in the figure.

[0037] In step 415, an insulating material (e.g., a mask) can be formed on the polysilicon film, and an etching process can be performed on the polysilicon film and the insulating material to form an emitter opening in the polysilicon film on the NPN (or PNP) side of the device. In this embodiment, the etching process is a conventional photolithography and etching process as described herein. A spacer sidewall material, such as an oxide or nitride or a combination thereof, can be deposited and patterned to form sidewall spacers 34. For example, the spacer sidewall material can be blanket-deposited on the structure including the emitter opening using a CVD process. The spacer sidewall material can undergo an anisotropic etching process to form the sidewall spacers 34. An emitter material can be grown in situ using doping within the opening and on both the insulating material and the sidewall spacers to form an emitter 32a.

[0038] In step 420, another etching process can be performed on the polysilicon film and the insulating material to form an emitter opening in the polysilicon film on the PNP (or NPN) side of the device. In this embodiment, the etching process is a conventional photolithography and etching process as described herein. Spacer sidewall materials, such as oxides or nitrides or combinations thereof, can be formed on the sidewalls of the opening to form sidewall spacers 34 as described above. Emitter material can be grown in situ within the opening and on the insulating material using in-situ doping to form emitter 32b. It should be understood that steps 415 and 420 are interchangeable.

[0039] The polysilicon films used for emitters 32a and 32b are planar and can be patterned according to a specific design configuration through an etching process. Silicides and contacts can be as follows... Figure 1 To manufacture as described.

[0040] These structures can be used in System-on-Chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0041] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with one or both surface-mount or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0042] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: The first transistor includes an inner base, an outer base, and an emitter; as well as The second transistor includes an inner base, an outer base, and an emitter. Wherein, the outer base of the first transistor and the outer base of the second transistor include a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

2. The structure of claim 1, wherein, The outer base of the first transistor and the outer base of the second transistor are coplanar.

3. The structure according to claim 1, wherein, The first dopant type is an N-type dopant, and the second dopant type is a P-type dopant.

4. The structure according to claim 1, wherein, The common external base is a continuous semiconductor base material located between the first transistor and the second transistor.

5. The structure according to claim 4, further comprising: Semiconductor material that isolates the first dopant type of the first transistor from the second dopant type of the second transistor.

6. The structure according to claim 1, wherein, The first transistor and the second transistor include complementary NPN heterojunction bipolar transistors and PNP heterojunction bipolar transistors.

7. The structure according to claim 6, wherein, The PNP heterojunction bipolar transistor includes a triple-well configuration.

8. The structure according to claim 6, wherein, The first transistor includes a secondary collector region having the second dopant type, and the second transistor includes a secondary collector region having the first dopant type.

9. The structure according to claim 1, further comprising: A common contact connected to the outer base of the first transistor and the outer base of the second transistor.

10. The structure according to claim 9, wherein, The common contact extends over the semiconductor region that separates the outer base of the first transistor from the outer base of the second transistor.

11. The structure according to claim 1, further comprising: A first silicide contact located on the outer base of the first transistor and a second silicide contact located on the outer base of the second transistor, wherein the first silicide contact and the second silicide contact are separated from each other.

12. The structure according to claim 1, further comprising: A single silicide contact extending over both the outer base of the first transistor and the outer base of the second transistor.

13. The structure according to claim 1, wherein, The outer base of the first transistor extends above and overlaps with the outer base of the second transistor.

14. A structure comprising: A first heterojunction bipolar transistor includes an emitter having a first dopant type, an outer base having a second dopant type, and a secondary collector region having the first dopant type. as well as The second heterojunction bipolar transistor includes an emitter having the second dopant type, an outer base having the first dopant type, and a secondary collector region having the second dopant type. Wherein, the outer base of the first heterojunction bipolar transistor and the outer base of the second heterojunction bipolar transistor include a common and continuous semiconductor layer.

15. The structure according to claim 14, wherein, The outer base of the first heterojunction bipolar transistor is coplanar with the outer base of the second heterojunction bipolar transistor.

16. The structure according to claim 14, wherein, The first dopant type is an N-type dopant, and the second dopant type is a P-type dopant.

17. The structure according to claim 14, further comprising: Semiconductor material that isolates the outer base of the first heterojunction bipolar transistor from the outer base of the second heterojunction bipolar transistor.

18. The structure according to claim 14, wherein, The first heterojunction bipolar transistor and the second heterojunction bipolar transistor include complementary NPN heterojunction bipolar transistors and PNP heterojunction bipolar transistors, wherein the PNP heterojunction bipolar transistor further includes a triple-well.

19. The structure according to claim 14, wherein, The outer base of the first heterojunction bipolar transistor extends above and overlaps with the outer base of the second heterojunction bipolar transistor.

20. A method comprising: Forming a first transistor comprising an inner base, an outer base, and an emitter; as well as This forms a second transistor comprising an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor are formed to have a common outer base layer, the common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

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