Semiconductor device

Abstract

The present disclosure relates to a semiconductor device, and a semiconductor device according to at least one example embodiment includes a substrate, a bit line on the substrate, a plurality of word lines on the bit line, a first active pattern and a second active pattern spaced apart in a first direction between the plurality of word lines, at least one cell capacitor on at least one of the first active pattern and the second active pattern, and a plurality of shield patterns above the plurality of word lines and below the cell capacitor. The plurality of shield patterns overlap a second dopant region of at least one of the first active pattern and the second active pattern in the first direction, and the plurality of shield patterns include at least one of a metal-containing material having an n-type work function and polysilicon doped with an impurity.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Due to the increasing demand for higher integration technologies, techniques to increase the integration density of semiconductor devices are being explored. In the case of two-dimensional memory (or semiconductor) devices, the integration density is primarily determined by the area occupied by a single memory cell, and in this respect, it can depend on the level of micropatterning technology.

[0003] However, micropatterning techniques typically require expensive equipment. Therefore, despite increasing integration density in two-dimensional semiconductor devices, such technologies are generally still limited by rising costs. Consequently, three-dimensional memory devices with memory cells arranged in three dimensions are being explored.

[0004] As components contained in semiconductor memory devices become more integrated and / or miniaturized, it can be advantageous to reduce and / or minimize the influence between components included in the semiconductor device to improve the operating performance of the semiconductor device. Summary of the Invention

[0005] This disclosure attempts to provide a semiconductor device with improved reliability and / or productivity.

[0006] A semiconductor device according to at least one example embodiment includes: a substrate; bit lines on the substrate extending in a first horizontal direction; a plurality of word lines on the bit lines, each word line extending in a second horizontal direction intersecting the first horizontal direction; a first active pattern and a second active pattern between the plurality of word lines, such that the first active pattern and the second active pattern are spaced apart in the first horizontal direction; one or more cell capacitors, the one or more cell capacitors including at least one cell capacitor on at least one of the first active pattern and the second active pattern; and a plurality of shielding patterns at a level between the level of the plurality of word lines and the level of the one or more cell capacitors, wherein each of the first active pattern and the second active pattern includes a first doped region connected to the bit line, a second doped region connected to the one or more cell capacitors, and a channel region between the first doped region and the second doped region, the plurality of shielding patterns including at least one shielding pattern overlapping the second doped region of the first active pattern in the first horizontal direction and a shielding pattern overlapping the second doped region of the second active pattern in the first horizontal direction, and the plurality of shielding patterns including at least one of a metallic material having an n-type work function and impurity-doped polysilicon.

[0007] A semiconductor device according to at least one example embodiment includes: a substrate; bit lines on the substrate extending in a first horizontal direction; a plurality of word lines on the bit lines extending in a second horizontal direction intersecting the first horizontal direction; a first active pattern and a second active pattern spaced apart between the plurality of word lines in the first horizontal direction; a back gate electrode extending in the second horizontal direction between the first active pattern and the second active pattern; one or more memory contacts including at least one of memory contacts on the first active pattern and memory contacts on the second active pattern; One or more cell capacitors on one or more storage contacts; and a plurality of shielding patterns on at least one of a plurality of word lines and a back gate electrode, wherein each of the first active pattern and the second active pattern includes: a first dopant region connected to the bit line, a second dopant region connected to the storage contact, and a channel region between the first dopant region and the second dopant region, the plurality of shielding patterns including at least one of a shielding pattern overlapping the second dopant region of the first active pattern in a first horizontal direction and a shielding pattern overlapping the second dopant region of the second active pattern in a first horizontal direction, and the work function of the plurality of shielding patterns is less than or equal to the work function of the second dopant region.

[0008] A semiconductor device according to at least one example embodiment includes: a substrate; bit lines on the substrate extending in a first horizontal direction; a plurality of word lines on the bit lines extending in a second horizontal direction intersecting the first horizontal direction; a plurality of active patterns located between the plurality of word lines, such that the plurality of active patterns are spaced apart in the first horizontal direction; a back gate electrode between the plurality of active patterns extending in the second horizontal direction; at least one memory contact on the plurality of active patterns; at least one cell capacitor on the at least one memory contact; and a plurality of shielding patterns, the plurality of shielding patterns including a first shielding pattern on the back gate electrode and a second shielding pattern on the plurality of word lines, wherein the plurality of active patterns Each of the plurality of shielding patterns includes a first dopant region connected to a bit line, a second dopant region connected to a memory contact, and a channel region between the first and second dopant regions. Each of the plurality of shielding patterns overlaps with the second dopant region of at least one of the plurality of active patterns in a first horizontal direction. The first and second shielding patterns include at least one of a metallic material having an n-type work function and polysilicon doped with n-type impurities. The work function of each of the first and second shielding patterns is lower than or equal to the work function of the second dopant region of the corresponding active pattern, and the work function of each of the first and second shielding patterns is greater than or equal to the work function of at least one memory contact.

[0009] A method for manufacturing a semiconductor device according to at least one example embodiment includes the following steps: preparing a sub-substrate comprising a buried insulating layer and an active layer stacked sequentially; forming a back gate electrode extending in a first direction within the active layer; forming a first shielding pattern on the back gate electrode; patterning the active layer to form a plurality of active patterns on both sides of the back gate electrode; forming initial word lines on the buried insulating layer on both sides of the back gate electrode; forming a second shielding pattern on the initial word lines; forming memory contacts connected to the plurality of active patterns; forming cell capacitors on the memory contacts; after removing the sub-substrate and the buried insulating layer, patterning the initial word lines to form a plurality of word lines on both sides of the back gate electrode; forming bit lines extending in a second direction intersecting the first direction on the plurality of active patterns; forming a peripheral circuit structure on the substrate; and bonding the bit lines and the peripheral circuit structure to face each other; wherein the first shielding pattern and the second shielding pattern comprise impurity-doped polycrystalline silicon or a metal-containing material having an n-type work function.

[0010] Each of the multiple active patterns includes a first dopant region connected to a bit line, a second dopant region connected to a storage contact, and a channel region between the first and second dopant regions, and the work function of each shielding pattern in the first and second shielding patterns may be lower than or equal to the work function of the second dopant region.

[0011] Impurities can be n-type impurities.

[0012] The concentration of n-type impurities in each of the first and second shielding patterns can be greater than or equal to the concentration of n-type impurities in the second dopant region.

[0013] The work function of the first shielding pattern and the second shielding pattern can be greater than or equal to the work function of the storage contact.

[0014] Metallic materials with an n-type work function may include at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN).

[0015] The method for manufacturing a semiconductor device may further include a step of forming a first shielding insulating pattern on a back gate electrode before forming a first shielding pattern, a step of forming a first shielding cover pattern on the first shielding pattern, a step of forming a second shielding insulating pattern on an initial word line before forming a second shielding pattern, and a step of forming a second shielding cover pattern on the second shielding pattern.

[0016] According to some example embodiments, since the shielding pattern is formed such that it is positioned to overlap with the doped region of the active pattern connected to the capacitor, the gate-induced drain leakage current (GIDL) of the storage transistor can be reduced or suppressed. Attached Figure Description

[0017] Figure 1 It is a plan view of a semiconductor device according to at least one example embodiment.

[0018] Figure 2 It shows along Figure 1 A cross-sectional view of the sections intercepted by lines A-A' and B-B'.

[0019] Figure 3 It shows along Figure 1 A cross-sectional view of the section cut by line C-C'.

[0020] Figure 4 yes Figure 3 A magnified view of a portion of region P1.

[0021] Figures 5 to 11 This is a partially enlarged view showing a cross-section of a semiconductor device according to some example embodiments.

[0022] Figure 12 This is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0023] Figure 13 yes Figure 12 A magnified view of region R1.

[0024] Figure 14 and Figure 15 This is a partially enlarged view showing a cross-section of a semiconductor device according to some example embodiments.

[0025] Figures 16 to 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to at least one example embodiment. Detailed Implementation

[0026] In the following detailed description, certain embodiments are shown and described only by way of illustration.

[0027] The present invention and its concept can be implemented in different ways and are not limited to the following embodiments.

[0028] The accompanying drawings and descriptions are intended to be illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements.

[0029] As used herein, expressions such as "at least one of..." modify the entire list of elements when preceding it, without modifying any individual element in the list. For example, the expression "at least one of a, b, or c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0030] Furthermore, the dimensions and thicknesses of each structure shown in the accompanying drawings are arbitrarily illustrated for understanding and ease of description, but the invention is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Additionally, the thicknesses of some layers and regions are exaggerated in the drawings for understanding and ease of description. Furthermore, when the terms “about” or “substantially” are used in conjunction with numerical and / or geometric terms in this specification, the numerical values ​​intended to be associated include manufacturing tolerances (e.g., ±10%) around said values. Moreover, regardless of whether numerical and / or geometric terms are modified to “about” or “substantially,” it should be understood that these values ​​should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around said numerical and / or geometric values.

[0031] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly” on another element, there are no intermediate elements present. Additionally, when an element is referred to as being “on” a reference portion, the element is located above or below the reference portion, and does not necessarily mean that the element is located “above” or “on” in a direction opposite to gravity. Furthermore, it will be understood that spatially relative terms, such as “above,” “top,” etc., are intended to cover different orientations of the device in use or operation other than those depicted in the figures, and the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein are interpreted accordingly.

[0032] Furthermore, throughout the specification, unless explicitly stated otherwise, the word “comprising” and variations such as “including” or “included” shall be understood to imply inclusion of the stated element but not exclusion of any other element.

[0033] Furthermore, throughout the specification, when referred to as "on a plane," it means when viewing the target portion from above, and when referred to as "on a cross section," it means when viewing the cross section obtained by vertically cutting the target portion from the side.

[0034] In the following text, reference will be made to Figures 1 to 4 A semiconductor device according to at least one example embodiment is described.

[0035] Figure 1 It is a plan view of a semiconductor device according to at least one example embodiment. Figure 2 It shows along Figure 1 A cross-sectional view of the sections intercepted by lines A-A' and B-B'. Figure 3 It shows along Figure 1 A cross-sectional view of the section cut by line C-C'. Figure 4 yes Figure 3A magnified view of a portion of region P1.

[0036] The semiconductor device according to at least one example embodiment may include a plurality of memory cells, the plurality of memory cells including vertical channel transistors (VCTs). However, this is an example, and the semiconductor device according to the embodiment is not limited thereto, and various changes may be made.

[0037] Reference Figures 1 to 4 The semiconductor device according to some example embodiments may include a substrate 100 and a peripheral circuit structure PS and a cell structure CS located on the substrate 100.

[0038] The substrate 100 may include a cell array region CAR and a peripheral circuit region PAR defined around the cell array region CAR. For example, the peripheral circuit region PAR may be positioned adjacent to and surrounding the cell array region CAR. However, the arrangement relationship between the cell array region CAR and the peripheral circuit region PAR is not limited to this and can be varied.

[0039] In the cell array area CAR, multiple memory cells including storage transistors MT and cell capacitors DSP, word lines WL and bit lines BL connected to them can be located, and in the peripheral circuit area PAR, multiple contacts (not shown in the figure) and contact wiring (not shown in the figure) connected to the components located in the cell array area CAR can be located.

[0040] A storage cell may include a storage transistor MT and a cell capacitor DSP. Two distinguishable states can be determined based on whether any charge is stored in the cell capacitor DSP, and thus the cell capacitor DSP can be used as a storage element.

[0041] The gate electrode of the storage transistor MT can be connected to the word line WL, and the first source / drain electrode of the storage transistor MT can be connected to a terminal of the cell capacitor DSP, and the second source / drain electrode of the storage transistor MT can be connected to the bit line BL.

[0042] The substrate 100 may comprise, but is not limited to, silicon, germanium silicon, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and / or combinations thereof, and the materials contained in the substrate 100 may be varied. For example, the substrate 100 may be a silicon substrate.

[0043] In at least one example embodiment, the peripheral circuit structure PS and the unit structure CS positioned on the substrate 100 can be positioned to overlap in the vertical direction. For example, the peripheral circuit structure PS and the unit structure CS can be stacked sequentially on the substrate 100. In other words, the unit structure CS can be positioned on the peripheral circuit structure PS. However, this disclosure is not limited to this, and the stacking relationship between the unit structure CS and the peripheral circuit structure PS can be changed differently. For example, the unit structure CS can be adjacent to and positioned side by side with the peripheral circuit structure PS in the horizontal direction. As another example, the unit structure CS can be positioned below the peripheral circuit structure PS so as to overlap with the peripheral circuit structure in the vertical direction.

[0044] The configuration and structure of the semiconductor device according to the example embodiments will be described in detail below.

[0045] An example embodiment will be described assuming that the cell structure CS is located on the peripheral circuit structure PS.

[0046] The peripheral circuit structure PS can be positioned on the substrate 100. The peripheral circuit structure PS can be positioned between the substrate 100 and the unit structure CS.

[0047] The peripheral circuit structure PS can be located within the cell array region CAR and the peripheral circuit region PAR of the entire substrate 100. In other words, a portion of the peripheral circuit structure PS can be located on the cell array region CAR of the substrate 100, and another portion can be located on the peripheral circuit region PAR.

[0048] Although not shown in the accompanying drawings, the peripheral circuit structure PS may include a core region and a peripheral region. The core region and the peripheral region may be collectively referred to as the logic region or the peripheral circuit region.

[0049] The core area may include a core library, and the core library may include core circuitry such as word line drivers, sense amplifiers, row decoders, column decoders, and read / write circuitry (R / W circuitry).

[0050] The peripheral area may include peripheral circuits, such as timer registers, address registers, data input registers, data output registers, and data input / output terminals.

[0051] The peripheral circuit structure PS may include peripheral circuitry PC for driving components located in the unit structure CS. For example, the peripheral circuitry PC may include the core circuitry and / or peripheral circuitry mentioned above.

[0052] The peripheral circuit structure PS may include peripheral circuit PC, peripheral circuit contacts PCT1, PCT2 and PCT3, peripheral circuit wiring PCL1 and PCL2, peripheral circuit insulation layer 212, first bonding insulation layer 214 and multiple first bonding pads 221.

[0053] Peripheral circuitry PC can be positioned on substrate 100. Peripheral circuitry PC can be, for example, a sensing transistor, a transmission transistor, a driving transistor, etc. However, the type of transistor in peripheral circuitry PC can vary depending on the design of the semiconductor device. Peripheral circuitry wirings PCL1 and PCL2 and / or multiple first bonding pads 221 can each comprise a conductive material, such as a metal, a conductive oxide, and / or a conductive nitride. For example, the conductive material can be a zero-bandgap material, a semiconductor doped to have the same or substantially similar conductivity as a zero-bandgap material, a combination thereof, and / or the like.

[0054] The peripheral circuit insulating layer 212 may cover the peripheral circuit PC. In other words, the peripheral circuit insulating layer 212 may cover the side surface and top surface of the peripheral circuit PC. The peripheral circuit insulating layer 212 may contain an insulating material. For example, the peripheral circuit insulating layer 212 may include silicon oxide, silicon nitride, silicon nitride, and / or a low dielectric constant material. However, this disclosure is not limited thereto.

[0055] The peripheral circuit contacts PCT1, PCT2 and PCT3, as well as the peripheral circuit wiring PCL1 and PCL2, can be located in the peripheral circuit insulation layer 212.

[0056] The first peripheral circuit wiring PCL1 can be connected to the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring PCL1 can be connected to at least one source / drain region of the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring PCL1 and the second peripheral circuit wiring PCL2 can be connected via the second peripheral circuit contact PCT2.

[0057] Although shown in the accompanying drawings, in at least one example embodiment the peripheral circuit insulation layer 212 consists of a single layer, this disclosure is not limited thereto, and the peripheral circuit insulation layer 212 may consist of multiple layers comprising the same and / or different materials.

[0058] When the peripheral circuit insulation layer 212 is composed of multiple layers, at least some of the first peripheral circuit contact PCT1, the second peripheral circuit contact PCT2, the third peripheral circuit contact PCT3, the first peripheral circuit wiring PCL1, the second peripheral circuit wiring PCL2, and the third peripheral circuit wiring PCL3 may be located in the same layer or in different layers.

[0059] The first bonding insulating layer 214 can be positioned on the peripheral circuit insulating layer 212.

[0060] The first bonding insulating layer 214 may also comprise an insulating material. For example, the first bonding insulating layer 214 may comprise silicon carbon nitride, but is not limited thereto. As another example, the first bonding insulating layer 214 may comprise at least one of silicon oxide, silicon oxide nitride, carbon silicon oxide nitride, and silicon nitride.

[0061] The third peripheral circuit contact PCT3 can be located within the peripheral circuit insulating layer 212 and the first bonding insulating layer 214. In other words, a portion of the third peripheral circuit contact PCT3 can be located within the peripheral circuit insulating layer 212, and another portion can be located within the first bonding insulating layer 214.

[0062] Multiple first bonding pads 221 may be positioned within a first bonding insulating layer 214. The first bonding insulating layer 214 may surround the multiple first bonding pads 221. The first bonding insulating layer 214 may surround the side and bottom surfaces of the first bonding pads 221. The upper surface of the first bonding insulating layer 214 may be positioned at substantially the same level as the upper surfaces of the multiple first bonding pads 221, and the first bonding insulating layer 214 may expose the upper surfaces of the multiple first bonding pads 221. The first bonding pads 221 may be connected to a second peripheral circuit wiring PCL2 via a third peripheral circuit contact PCT3.

[0063] In at least one example embodiment, the peripheral circuit structure PS and the unit structure CS can be joined using a hybrid bonding process, such as a Cu-to-Cu (C2C) wafer bonding method, to form a semiconductor device. For example, the peripheral circuit structure PS and the unit structure CS can be joined using a hybrid copper bonding (HCB) method to form a semiconductor device. However, the bonding method for the peripheral circuit structure PS and the unit structure CS is not limited to this and can be modified in various ways.

[0064] Although not shown in the accompanying drawings, in some example embodiments, the cell structure CS and the peripheral circuit structure PS can be directly connected via a single via. For example, the cell structure CS and the peripheral circuit structure PS can be connected to a single via extending from the peripheral circuit structure PS to the cell structure CS.

[0065] Specifically, the peripheral circuit structure PS may include two surfaces facing each other. One of the two surfaces of the peripheral circuit structure PS may be the surface facing the unit structure CS, and the other surface of the peripheral circuit structure PS may be the surface facing the substrate 100.

[0066] Here, one surface of the peripheral circuit structure PS can refer to the front side of the peripheral circuit structure PS, and the other surface of the peripheral circuit structure PS can refer to the rear side of the peripheral circuit structure PS.

[0067] Furthermore, the unit structure CS may include one surface and another surface facing each other. One surface of the unit structure CS may be the surface facing the peripheral circuit structure PS, and the other surface may be the surface opposite to said one surface. Here, one surface of the unit structure CS may refer to the rear side of the unit structure CS, and the other surface of the unit structure CS may refer to the front side of the unit structure CS.

[0068] In at least one example embodiment, a surface of the peripheral circuit structure PS adjacent to the unit structure CS can be a bonding surface with the unit structure CS. Furthermore, a surface of the unit structure CS adjacent to the peripheral circuit structure PS can be a bonding surface with the peripheral circuit structure PS. In other words, a surface of the peripheral circuit structure PS and a surface of the unit structure CS can be bonding surfaces of the peripheral circuit structure PS and the unit structure CS. A surface of the peripheral circuit structure PS and a surface of the unit structure CS can constitute the interface between the peripheral circuit structure PS and the unit structure CS.

[0069] Specifically, the unit structure CS may include a second bonding insulating layer 216, which contacts the first bonding insulating layer 214 of the peripheral circuit structure PS. The second bonding insulating layer 216 may contain the same material as the first bonding insulating layer 214 located in the aforementioned peripheral circuit structure PS, and may be located on the first bonding insulating layer 214.

[0070] Within the second bonding insulating layer 216 located in the unit structure CS, second bonding pads 222 may be positioned. The second bonding pads 222 may include a conductive material. The second bonding insulating layer 216 may surround a plurality of second bonding pads 222. The second bonding insulating layer 216 may surround the side and top surfaces of the second bonding pads 222. The lower surface of the second bonding insulating layer 216 may be positioned substantially at the same level as the lower surfaces of the plurality of second bonding pads 222, and the second bonding insulating layer 216 may expose the lower surfaces of the plurality of second bonding pads 222.

[0071] The plurality of second bonding pads 222 located in the second bonding insulating layer 216 can form a metallic bond while in direct contact with the plurality of first bonding pads 221 located in the first bonding insulating layer 214. The upper surfaces of the plurality of first bonding pads 221 and the lower surfaces of the plurality of second bonding pads 222 can be in contact. The plurality of first bonding pads 221 and the plurality of second bonding pads 222 can be positioned at the interface between the peripheral circuit structure PS and the unit structure CS, and can be in contact with each other.

[0072] Furthermore, the first bonding insulating layer 214 located in the peripheral circuit structure PS and the plurality of second bonding insulating layers 216 located in the unit structure CS can contact each other to form a junction insulating layer.

[0073] Therefore, one surface of the unit structure CS and one surface of the peripheral circuit structure PS can be bonded. In other words, a plurality of first bonding pads 221 and a first bonding insulating layer 214 located in the peripheral circuit structure PS can constitute one surface or bonding surface of the peripheral circuit structure PS, and a plurality of second bonding pads 222 and a second bonding insulating layer 216 located in the unit structure CS can constitute one surface or bonding surface of the unit structure CS.

[0074] The first bonding pad 221 of the peripheral circuit structure PS and the second bonding pad 222 of the cell structure CS can be bonded to provide an electrical connection path between the peripheral circuit structure PS and the cell structure CS. For example, cell connection wiring 232 connected to components included in the cell structure CS can be connected to the peripheral circuit PC and / or the peripheral circuit wirings PCL1 and PCL2 included in the peripheral circuit structure PS via the first bonding pad 221 and the second bonding pad 222.

[0075] The cell structure CS may include cell connection wiring contacts 231 and cell connection wiring 232 positioned in the second bonding insulating layer 216. Cell connection wiring contacts 231 and cell connection wiring 232 may include conductive material. Cell connection wiring 232 may be connected to components positioned in the cell structure CS, and cell connection wiring contacts 231 may connect the second bonding pad 222 to the cell connection wiring 232. For example, cell connection wiring 232 may be connected to multiple memory cells located in the cell structure CS, including memory transistors MT and cell capacitors DSP, word lines WL and bit lines BTL connected to the memory cells, etc.

[0076] Each of the peripheral circuit contacts PCT1, PCT2, and PCT3 and the peripheral circuit wirings PCL1 and PCL2 located in the peripheral circuit structure PS, and each of the cell connection wiring contacts 231 and cell connection wirings 232 located in the cell structure CS, may contain a conductive material. For example, each of them may contain aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), tantalum (Ta), etc. However, this disclosure is not limited thereto.

[0077] In at least one example embodiment, the cell structure CS may include multiple bit lines BL, multiple word lines WL1 and WL2 located on the bit lines BL and extending across the multiple bit lines BL, multiple active patterns AP1 and AP2 located between the word lines WL1 and WL2, a back gate electrode BG located between the active patterns AP1 and AP2 and extending across the multiple bit lines BL, a memory contact BC located on the multiple active patterns AP1 and AP2, a landing pad LP located on the memory contact BC, a cell capacitor DSP located on the landing pad LP, and multiple shielding patterns SP located at the horizontal level between the word lines WL1 and WL2 and the cell capacitor DSP and overlapping at least a portion of the active patterns AP1 and AP2 in the horizontal direction.

[0078] A semiconductor device according to at least one example embodiment may include multiple bit lines BL.

[0079] Multiple bit lines BL can extend parallel to each other in a second direction Y that intersects a first direction X parallel to the substrate 100. The multiple bit lines BL can be positioned on the substrate 100 so that they are spaced apart from each other in the first direction X.

[0080] In at least one example embodiment, multiple bit lines BL can extend from the cell array region CAR to the peripheral circuit region PAR in the second direction Y.

[0081] Therefore, the end of bit line BL can be located in the peripheral circuit region PAR, which is located on both sides of the cell array region CAR in the second direction Y. The end of bit line BL located in the peripheral circuit region PAR can be connected to the bit line contact (not shown in the figure) that connects bit line BL to the peripheral circuit structure PS.

[0082] Bit line BL may include a polysilicon layer 161, a first metal layer 163, a second metal layer 165, and a bit line capping layer 167.

[0083] The polysilicon layer 161 may contain polysilicon doped with impurities, and the first metal layer 163 and the second metal layer 165 may contain conductive materials. For example, the first metal layer 163 may contain conductive metal nitrides (e.g., titanium nitrides, tantalum nitrides, etc.), and the second metal layer 165 may contain metals (e.g., tungsten, titanium, tantalum, etc.).

[0084] Furthermore, either the first metal layer 163 or the second metal layer 165 may contain a metal silicide, such as titanium silicide, cobalt silicide, or nickel silicide. However, the materials contained in the first metal layer 163 and the second metal layer 165 are not limited to these and can be varied.

[0085] The bit line cap 167 may contain an insulating material, such as silicon nitride or silicon dioxide.

[0086] In some example embodiments, the bit line BL may comprise two-dimensional or three-dimensional materials, and may comprise, for example, graphene as a carbon-based two-dimensional material, carbon nanotubes as a three-dimensional material, or a combination thereof.

[0087] Multiple bit lines BL can be positioned adjacent to the peripheral circuit structure PS. With multiple bit lines BL positioned adjacent to the peripheral circuit structure PS, the electrical connection paths between the bit lines BL and the peripheral circuit PC can be reduced.

[0088] The semiconductor device according to at least one example embodiment may further include a bit line shielding pattern BS and a spacer insulating layer 175 located between the peripheral circuit structure PS and the cell structure CS.

[0089] The bit line shielding pattern BS can be positioned between the peripheral circuit structure PS and the bit line BL.

[0090] Furthermore, the bit line shielding pattern BS can be located between adjacent bit lines BL in the bit line BL, and can extend in the second direction Y.

[0091] In other words, the bit line shielding pattern BS can be arranged alternately with the bit line BL in the first direction X.

[0092] The spacer insulating layer 175 may be conformally positioned below the bit lines BL. The spacer insulating layer 175 may cover both side surfaces and the lower surface of each of the multiple bit lines BL. The spacer insulating layer 175 may define and / or fill the gap region between the multiple bit lines BL. The gap region of the spacer insulating layer 175 may extend in the second direction Y so as to be parallel to the bit lines BL.

[0093] Bit line shielding patterns (BS) can contain conductive materials. For example, a bit line shielding pattern (BS) can include metallic materials such as tungsten (W), titanium (Ti), nickel (Ni), and cobalt (Co). As another example, a bit line shielding pattern (BS) can contain conductive two-dimensional (2D) materials such as graphene. However, bit line shielding patterns (BS) are not limited to these.

[0094] The spacer insulating layer 175 may comprise an insulating material. For example, the spacer insulating layer 175 may comprise silicon oxide, silicon nitride, silicon nitride, and / or a low-dielectric material.

[0095] The bit line shielding pattern BS can be positioned below the spacer insulation layer 175. The bit line shielding pattern BS can be positioned in the gap region of the spacer insulation layer 175.

[0096] like Figure 2 and Figure 3As shown, the bit line shielding pattern BS may include line portions located between adjacent bit lines BL, and connecting portions of common connecting line portions.

[0097] Specifically, the line portions of the bit line shielding pattern BS can be positioned between bit lines BL and within a plurality of gap regions defined by the spacer insulating layer 175. Therefore, the line portions of the bit line shielding pattern BS and the side surfaces of the bit lines BL can be spaced apart, and the spacer insulating layer 175 is inserted therebetween.

[0098] The connecting portion of the bit line shielding pattern BS can be connected to and integral with the line portion. The connecting portion of the bit line shielding pattern BS can be located on the line portion to connect the line portion, and located between adjacent bit lines BL. However, this disclosure is not limited thereto, and in some exemplary embodiments, the line portion and the connecting portion of the bit line shielding pattern BS can be formed as separate components.

[0099] Although not shown, the connecting portion of the bit line shielding pattern BS can extend from the cell array region CAR to the peripheral circuit region PAR. Therefore, the end portion of the connecting portion of the bit line shielding pattern BS can be positioned in the peripheral circuit region PAR. The connecting portion of the bit line shielding pattern BS located in the peripheral circuit region PAR can be connected to the bit line shielding contact (not shown in the figure).

[0100] The semiconductor device according to at least one example embodiment may further include a bit line shielding cap 179 located under the bit line shielding pattern BS, a first unit insulating layer 177 located between a spacer insulating layer 175 and a second bonding insulating layer 216, a second unit insulating layer 173 located on the spacer insulating layer 175, and a component isolation layer STI located on the second unit insulating layer 173.

[0101] The bit line shielding cover 179 can be positioned between the bit line shielding pattern BS and the second bonding insulation layer 216 to cover the bit line shielding pattern BS.

[0102] The first unit insulating layer 177 can be positioned on the second bonding insulating layer 216. The upper surface of the first unit insulating layer 177 can contact the spacer insulating layer 175, and the side surface of the first unit insulating layer 177 can contact the end portion of the bit line shielding pattern BS and the end portion of the bit line shielding cover layer 179.

[0103] The second unit insulation layer 173 can be positioned on the spacer insulation layer 175.

[0104] like Figure 3As shown, the second unit insulating layer 173 may contact and cover the end portion of the bit line BL. However, this is an example, and the present disclosure is not limited thereto. For example, the second unit insulating layer 173 may be positioned separately from the end portion of the bit line BL.

[0105] The component isolation layer STI can be positioned on the second cell insulating layer 173. A portion of the component isolation layer STI can overlap with the bit line BL in the third direction Z, which is the vertical direction.

[0106] The bit line shielding cap 179, the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI may contain insulating materials, such as silicon oxide, silicon nitride, silicon nitride, and / or low-dielectric materials. For example, the bit line shielding cap 179 may contain silicon nitride, and the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI may contain silicon oxide. However, this is just an example, and the materials contained in each of the bit line shielding cap 179, the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI may vary.

[0107] Multiple active patterns AP1 and AP2 may include multiple first active patterns AP1 and multiple second active patterns AP2, which are positioned spaced apart in a first direction X between word lines WL1 and WL2. The multiple first active patterns AP1 and multiple second active patterns AP2 may be alternately positioned on bit line BL in a second direction Y.

[0108] The first active pattern AP1 and the second active pattern AP2 can be arranged in two dimensions on a plane along the first direction X and the second direction Y. In other words, the first active pattern AP1 and the second active pattern AP2 can be positioned so that they are spaced apart from each other and face each other in the second direction Y.

[0109] In at least one example embodiment, each of the first active pattern AP1 and the second active pattern AP2 may comprise a semiconductor material, such as a single-crystal semiconductor material. For example, the first active pattern AP1 and the second active pattern AP2 may comprise single-crystal silicon. However, this disclosure is not limited thereto, and the materials comprised in the first active pattern AP1 and the second active pattern AP2 may be varied. For example, the first and second active patterns AP1 and AP2 may comprise at least one of polycrystalline semiconductors, oxide semiconductors, and two-dimensional materials. For example, the polycrystalline semiconductor may be polycrystalline silicon. As another example, the oxide semiconductor may be indium gallium zinc oxide (IGZO). As another example, the two-dimensional material may be a semiconductor two-dimensional material, such as at least one of MoS2, WS2, MoSe2, WSe2, and / or the like.

[0110] Each of the first active pattern AP1 and the second active pattern AP2 may have a length in the first direction X, a width in the second direction Y, and a height in the third direction Z. Each of the first active pattern AP1 and the second active pattern AP2 may include a first surface and a second surface facing each other in the third direction Z.

[0111] Here, the first surface may refer to the surface adjacent to the bit line BL, and the second surface may refer to the surface adjacent to the memory contact described below. In other words, the first surface of active patterns AP1 and AP2 may correspond to the lower surface, and the second surface may correspond to the upper surface.

[0112] In at least one example embodiment, the first surface and the second surface of each of the first active pattern AP1 and the second active pattern AP2 may have the same width or substantially similar widths. Furthermore, the width of the first active pattern AP1 may be the same as (or substantially similar to) the width of the second active pattern AP2. However, this disclosure is not limited thereto, and in some example embodiments, the first surface and the second surface of each of the first active pattern AP1 and the second active pattern AP2 may have different widths. For example, the width of the second surface of each of the first active pattern AP1 and the second active pattern AP2 may be greater than the width of the first surface.

[0113] The following will refer to Figure 4 Describe in detail the first active pattern AP1 and the second active pattern AP2.

[0114] The semiconductor device according to at least one example embodiment may include a plurality of back gate electrodes BG extending between a first active pattern AP1 and a second active pattern AP2 in a direction different from the direction of the bit line BL.

[0115] Multiple back gate electrodes BG can be located between a first active pattern AP1 and a second active pattern AP2, which are adjacent to each other in the second direction Y and extend across the bit line BL in the first direction X. In other words, the multiple back gate electrodes BG can extend across the bit line BL in a direction different from the extension direction of the bit line BL.

[0116] Multiple back gate electrodes BG can be located on bit lines BL and bit line shielding patterns BS. A first active pattern AP1 can be positioned on one side of the back gate electrode BG in the second direction Y, and a second active pattern AP2 can be positioned on the other side of the back gate electrode BG in the second direction Y.

[0117] The thickness of the back gate electrode BG in the third direction Z can be less than the thickness of the first active pattern AP1 and the second active pattern AP2 in the third direction Z. However, this is just an example, and the relationship between the thickness of the back gate electrode BG in the third direction Z and the thicknesses of the first active pattern AP1 and the second active pattern AP2 in the third direction Z can be varied.

[0118] Furthermore, the back gate electrode BG can be located between a pair of adjacent first word lines WL1 and second word lines WL2 in the second direction Y. For example, the first active pattern AP1 can be located between the first word line WL1 (described below) and the back gate electrode BG, and the second active pattern AP2 can be located between the second word line WL2 (described below) and the back gate electrode BG. However, this is just an example, and the arrangement of the first active pattern AP1 and the second active pattern AP2, the first word lines WL1 and the second word lines WL2 (described below), and the back gate electrode BG is not limited to this and can be varied.

[0119] The back gate electrode (BG) may contain a conductive material. For example, the back gate electrode (BG) may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, conductive two-dimensional material, and metal. However, this is just an example, and the conductive material can be varied.

[0120] During the operation of a semiconductor device, the back gate electrode (BG) can receive a negative voltage and increase the threshold voltage of the vertical-channel transistor. In other words, as the vertical-channel transistor is scaled down, the threshold voltage can be reduced, thereby protecting leakage current characteristics from degradation.

[0121] The semiconductor device according to at least one example embodiment may further include a first back gate insulating pattern 111 and a second back gate insulating pattern 117.

[0122] The first back gate insulating pattern 111 and the second back gate insulating pattern 117 may be located between the first active pattern AP1 and the second active pattern AP2 that are adjacent to each other in the second direction Y. The first back gate insulating pattern 111 and the second back gate insulating pattern 117 may extend in the first direction X so as to be parallel to the back gate electrode BG.

[0123] The first back gate insulating pattern 111 may contact the first active pattern AP1 and the second active pattern AP2. The first back gate insulating pattern 111 may extend in the third direction Z along the side surfaces of each of the first active pattern AP1 and the second active pattern AP2 that face each other in the second direction Y.

[0124] The back gate electrode BG may include a first surface and a second surface facing each other in the third direction Z. Here, the first surface of the back gate electrode BG may refer to the surface facing the bit line BL and the bit line shielding pattern BS, and the second surface of the back gate electrode BG may refer to the surface facing the first shielding pattern SP1, which will be described below. In other words, the first surface of each back gate electrode BG may correspond to the lower surface of the back gate electrode BG, and the second surface may correspond to the upper surface of the back gate electrode BG.

[0125] The first back gate insulating pattern 111 can extend along the two side surfaces of the back gate electrode BG, and the second back gate insulating pattern 117 can be positioned between the first surface of the back gate electrode BG and the bit line BL.

[0126] The first back gate insulating pattern 111 and the second back gate insulating pattern 117 may contain an insulating material. Each of the first back gate insulating pattern 111 and the second back gate insulating pattern 117 may contain an insulating material, such as at least one of silicon oxide, silicon oxide nitride, or silicon nitride. However, the materials contained in the first back gate insulating pattern 111 and the second back gate insulating pattern 117 are not limited thereto and can be varied.

[0127] Multiple word lines WL1 and WL2 may be located on bit line BL and bit line masking pattern BS. The multiple word lines WL1 and WL2 may include multiple first word lines WL1 and multiple second word lines WL2 extending in a first direction X that intersects with a second direction Y, which is the extension direction of bit line BL. The multiple first word lines WL1 and second word lines WL2 may be positioned separately from each other in the second direction Y.

[0128] The first active pattern AP1 and the second active pattern AP2 can be located between the first word line WL1 and the second word line WL2, which are adjacent in the second direction Y.

[0129] Multiple first word lines WL1 and multiple second word lines WL2 may overlap with bit lines BL and bit line shielding patterns BS in a third direction Z. The multiple first word lines WL1 and second word lines WL2 may extend in a third direction Z intersecting a first direction X and a second direction Y. The third direction Z may also be referred to as the vertical direction; in these cases, the first direction X and the second direction Y may also be referred to as the first horizontal direction X and the second horizontal direction Y, respectively.

[0130] In other words, the first word line WL1 and the second word line WL2 can be located between the bit line BL and the second shielding pattern SP2, which will be described below, and extend in the third direction Z.

[0131] In at least one example embodiment, word lines WL1 and WL2 may extend from the cell array region CAR to the peripheral circuit region PAR in a first direction X. Therefore, end portions of word lines WL1 and WL2 may be located in the peripheral circuit region PAR, and word line contacts (not shown in the figures) may be connected around the end portions of word lines WL1 and WL2 located in the peripheral circuit region PAR.

[0132] In at least one example embodiment, the first word line WL1 and the second word line WL2 have a rectangular shape in the cross-sectional view; however, the cross-sectional shape of the first word line WL1 and the second word line WL2 is not limited to this and can be varied. For example, each of the first word line WL1 and the second word line WL2 can have an 'L' shape in the cross-sectional view.

[0133] Each of the first word line WL1 and the second word line WL2 may include a first surface and a second surface facing each other in a third direction Z. Here, the first surface of each of the first word line WL1 and the second word line WL2 may refer to the surface facing the bit line BL and the bit line shielding pattern BS, and the second surface may refer to the surface facing the second shielding pattern SP2, which will be described below. In other words, the first surface of each word line in the first word line WL1 and the second word line WL2 may correspond to the lower surface, and the second surface may correspond to the upper surface.

[0134] The first word line WL1 and the second word line WL2 may contain conductive materials. For example, the first and second word lines WL1 and WL2 may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional materials, and metals. However, the conductive materials are not limited to these.

[0135] The semiconductor device according to at least one example embodiment may further include a gate insulating pattern GOX on the side surfaces of word lines WL1 and WL2, a gate isolation pattern 141 between word lines WL1 and WL2, and a gate cover pattern 147 on the first surfaces of word lines WL1 and WL2.

[0136] The gate insulating pattern GOX can contact the first active pattern AP1 and the second active pattern AP2. The gate insulating pattern GOX can extend in the third direction Z along the side surfaces of the first active pattern AP1 and the second active pattern AP2 that face each other in the second direction Y.

[0137] The gate isolation pattern 141 can be positioned between the first word line WL1 and the second word line WL2, which are spaced apart in the second direction Y. The gate isolation pattern 141 can be located between the gate cover pattern 147 and the contact interlayer insulating layer 271, which will be described below.

[0138] The gate isolation pattern 141 may contact the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be isolated and insulated by the gate isolation pattern 141. The gate isolation pattern 141 may extend in the third direction Z between the first word line WL1 and the second word line WL2.

[0139] Specifically, the gate isolation pattern 141 may include a first surface and a second surface facing each other in the third direction Z. The first surface of the gate isolation pattern 141 may refer to the surface facing the gate cap pattern 147, and the second surface may refer to the surface facing the contact interlayer insulating layer 271. In other words, the first surface of the gate isolation pattern 141 may correspond to the lower surface, and the second surface may correspond to the upper surface.

[0140] The thickness of the gate isolation pattern 141 in the third direction Z can be greater than the thickness of the first word line WL1 and the second word line WL2 in the third direction Z. The first surface of the gate isolation pattern 141 can be positioned at a lower level than the first surfaces of the first word line WL1 and the second word line WL2, and the second surface of the gate isolation pattern 141 can be positioned at a higher level than the second surfaces of the first word line WL1 and the second word line WL2.

[0141] Gate cover pattern 147 can be positioned on the first surfaces of word lines WL1 and WL2. Gate cover pattern 147 can cover the first surfaces of word lines WL1 and WL2.

[0142] The first surface of the gate isolation pattern 141 and its adjacent side surface can be covered by the gate cover pattern 147, and the second surface can be covered by the contact interlayer insulating layer 271.

[0143] The gate insulating pattern (GOX) may comprise an insulating material, such as silicon oxide, silicon nitride, a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or at least a combination thereof. For example, the high dielectric constant material may comprise any one of, but is not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof.

[0144] The gate isolation pattern 141 and the gate cover pattern 147 may comprise an insulating material, such as at least one of silicon oxide, silicon nitride, or a combination thereof. For example, the gate isolation pattern 141 may comprise silicon oxide, and the gate cover pattern 147 may comprise silicon nitride. However, this disclosure is not limited thereto.

[0145] Multiple shielding patterns SP can overlap with at least some of the first active pattern AP1 and the second active pattern AP2 in a second direction Y, which is the horizontal direction. Multiple shielding patterns SP can also overlap with at least a portion of one of the first active pattern AP1 and the second active pattern AP2 in a direction parallel to the extension direction of the bit line BL. In other words, multiple shielding patterns SP can overlap with at least a portion of one of the first active pattern AP1 and the second active pattern AP2 in a direction perpendicular to the extension directions of word lines WL1 and WL2.

[0146] Multiple shielding patterns SP can be positioned horizontally between word lines WL1 and WL2 and the unit capacitor DSP and / or between the back gate electrode BG and the unit capacitor DSP.

[0147] Multiple shielding patterns SP can be positioned at the level between the upper surfaces of word lines WL1 and WL2 and the lower surface of the storage contact BC, which will be described below, and / or between the upper surface of the back gate electrode BG and the lower surface of the storage contact BC.

[0148] Multiple shielding patterns SP can be positioned on at least one of multiple word lines WL1 and WL2 and multiple back gate electrodes BG. In other words, multiple shielding patterns SP can be positioned to overlap with at least one of multiple word lines WL1 and WL2 and multiple back gate electrodes BG in the third direction Z.

[0149] In at least one example embodiment, the plurality of shielding patterns SP may include a plurality of first shielding patterns SP1 located on the back gate electrode BG and a plurality of second shielding patterns SP2 located on word lines WL1 and WL2.

[0150] Multiple first shielding patterns SP1 can be positioned to overlap at least a portion of each of multiple back gate electrodes BG in the third direction Z, and multiple second shielding patterns SP2 can be positioned to overlap at least a portion of each of multiple word lines WL1 and WL2 in the third direction Z.

[0151] The first shielding pattern SP1 can extend along the third direction Z on the back gate electrode BG, and the second shielding pattern SP2 can extend along the third direction Z on the word lines WL1 and WL2.

[0152] Multiple shielding patterns SP can be positioned between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other in the second direction Y. The thickness of the multiple shielding patterns SP in the third direction Z can be less than the thickness of the first active pattern AP1 and the second active pattern AP2 in the third direction Z.

[0153] Therefore, each shielding pattern SP can be positioned to partially overlap with the first active pattern AP1 and the second active pattern AP2 in the second direction Y. However, the arrangement of the multiple shielding patterns SP is not limited to this and can be varied.

[0154] The following is for reference Figure 4 The arrangement relationship between the first and second active patterns AP1 and AP2 and the multiple shielding patterns SP is described in detail.

[0155] Although not in Figure 1 As shown in detail, however, in at least one example embodiment, the first shielding pattern SP1 may have the same (or substantially similar) shape as the back gate electrode BG in a plan view, and the second shielding pattern SP2 may have the same (or substantially similar) shape as each of the first word lines WL1 and WL2 in a plan view. However, this disclosure is not limited thereto. For example, the first shielding pattern SP1 and the back gate electrode BG may have different shapes in a plan view, and the second shielding pattern SP2 and each of the word lines WL1 and WL2 may have the same (or substantially similar) shape in a plan view. As another example, the first shielding pattern SP1 and the back gate electrode BG may have the same (or substantially) shape in a plan view, and the second shielding pattern SP2 and each of the word lines WL1 and WL2 may have different shapes in a plan view. As another example, the first shielding pattern SP1 and the back gate electrode BG may have different shapes in a plan view, and the second shielding pattern SP2 and each of the word lines WL1 and WL2 may have different shapes in a plan view.

[0156] The semiconductor device according to at least one example embodiment may further include a first shielding insulating pattern 113 located between the back gate electrode BG and the first shielding pattern SP1, a first shielding cover pattern 115 located on the first shielding pattern SP1, a second shielding insulating pattern 143 located between word lines WL1 and WL2 and the second shielding pattern SP2, and a second shielding cover pattern 145 located on the second shielding pattern SP2.

[0157] The first shielding insulating pattern 113 may be positioned between the back gate electrode BG and the first shielding pattern SP1, and shall isolate and insulate them. The first shielding cover pattern 115 may be positioned on the first shielding pattern SP1 and shall cover the first shielding pattern SP1. The first shielding cover pattern 115 may be positioned between the first shielding pattern SP1 and the contact interlayer insulating layer 271, which will be described below.

[0158] The first shielding insulating pattern 113 may extend along the side surface of the first shielding pattern SP1 and the side surface of the first shielding cover pattern 115. The two side surfaces of the first shielding insulating pattern 113 may be surrounded by the first back gate insulating pattern 111.

[0159] The first shielding insulation pattern 113 can be positioned between the first shielding pattern SP1 and the first back gate insulation pattern 111, and between the first shielding cover pattern 115 and the first back gate insulation pattern 111.

[0160] The second shielding insulation pattern 143 may be positioned between word lines WL1 and WL2 and the second shielding pattern SP2, and shall isolate and insulate them. The second shielding cover pattern 145 may be positioned on and cover the second shielding pattern SP2. The second shielding cover pattern 145 may be positioned between the second shielding pattern SP2 and the storage contact BC, which will be described below.

[0161] The second shielding insulating pattern 143 may extend along the side surface of the second shielding pattern SP2 and the side surface of the second shielding cover pattern 145. The two side surfaces of the second shielding cover pattern 145 may be surrounded by the gate insulating pattern GOX.

[0162] The second shielding insulation pattern 143 can be positioned between the second shielding pattern SP2 and the gate insulation pattern GOX, and between the second shielding cover pattern 145 and the gate insulation pattern GOX.

[0163] Each of the first shielding insulation pattern 113, the first shielding cover pattern 115, the second shielding insulation pattern 143, and the second shielding cover pattern 145 may contain an insulating material. For example, the insulating material may contain silicon oxide, silicon nitride, silicon nitride, etc., but is not limited to these, and various modifications may be made.

[0164] In at least one example embodiment, the plurality of shielding patterns SP can be configured such that no voltage is directly applied to the plurality of shielding patterns SP. In other words, the plurality of shielding patterns SP can be electrically floated.

[0165] In some example embodiments, voltage can be applied to multiple shielding patterns SP. For example, the same voltage can be applied to the back gate electrode BG and the first shielding pattern SP1, and the same voltage can be applied to the word lines WL1 and WL2 and the second shielding pattern SP2. As another example, different voltages can be applied to the back gate electrode BG and the first shielding pattern SP1, and the same voltage can be applied to the word lines WL1 and WL2 and the second shielding pattern SP2. As another example, the same voltage can be applied to the back gate electrode BG and the first shielding pattern SP1, and different voltages can be applied to the word lines WL1 and WL2 and the second shielding pattern SP2. As another example, different voltages can be applied to the back gate electrode BG and the first shielding pattern SP1, and different voltages can be applied to the word lines WL1 and WL2 and the second shielding pattern SP2.

[0166] Thus, when a voltage is applied to multiple shielding patterns SP, the multiple shielding patterns SP can be used together with multiple word lines WL1 and WL2 and / or back gate electrode BG as the gate electrode of the storage transistor MT, thereby controlling the threshold voltage of the storage transistor MT.

[0167] The semiconductor device according to at least one example embodiment may further include a contact interlayer insulating layer 271, a pad isolation insulating layer 273, and a contact etch stop layer 275 sequentially stacked on active patterns AP1 and AP2.

[0168] Interlayer insulating layer 271 can be positioned on active patterns AP1 and AP2. Interlayer insulating layer 271 can cover the first back gate insulating pattern 111, the first shielding cover pattern 115 and the second shielding cover pattern 145, the gate isolation pattern 141 and the element isolation layer STI.

[0169] The interlayer insulating layer 271, the pad isolation insulating layer 273, and the contact etch stop layer 275 each comprise an insulating material, such as at least one of silicon oxide, silicon nitride, or a combination thereof. For example, the interlayer insulating layer 271 may comprise silicon oxide, and the pad isolation insulating layer 273 and the contact etch stop layer 275 may comprise silicon nitride. However, this disclosure is not limited thereto.

[0170] In the cell array area CAR of the cell structure CS, the storage contact BC, landing pad LP and cell capacitor DSP can be stacked sequentially.

[0171] The semiconductor device according to at least one example embodiment may include a plurality of memory contacts BC. The plurality of memory contacts BC may extend through a contact interlayer insulating layer 271. The plurality of memory contacts BC may be connected to a first active pattern AP1 and a second active pattern AP2, respectively. The memory contacts BC adjacent to each other may be isolated and insulated from each other by the contact interlayer insulating layer 271.

[0172] Multiple storage contacts BC can be arranged in a matrix pattern along a first direction X and a second direction Y on a plane (e.g., a horizontal plane). Figure 1 The diagram shows each storage contact BC having a circular shape in a plane; however, this disclosure is not limited thereto, and each storage contact BC may have various shapes in the plan view, such as elliptical, rectangular, square, rhomboid, hexagonal, and / or similar shapes.

[0173] The storage contact BC may contain a conductive material. For example, the conductive material may contain at least one of the following: doped polycrystalline silicon, conductive metal nitride, conductive metal silicon nitride, metal nitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal. As a more specific example, the storage contact BC may contain polycrystalline silicon doped with n-type impurities. However, the material contained in the storage contact BC is not limited to this and can be varied.

[0174] The semiconductor device according to at least one example embodiment may include a plurality of landing pads LP. The plurality of landing pads LP may be respectively positioned on a plurality of memory contacts BC.

[0175] Multiple landing pads (LPs) can be arranged in a matrix along the first direction X and the second direction Y in a plan view. Figure 1 The diagram shows each landing pad LP having a circular shape in a plane; however, this disclosure is not limited thereto, and in the plan view, each landing pad LP may have various shapes, such as elliptical, rectangular, square, rhomboid, hexagonal and / or similar shapes.

[0176] Pad isolation insulation layer 273 can be positioned between the landing pads LP. The upper surface of the landing pads LP can be positioned at the same (or substantially similar) level as the upper surface of the pad isolation insulation layer 273.

[0177] The landing pad (LP) may contain a conductive material. The conductive material may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, combinations thereof, and / or the like.

[0178] The semiconductor device according to at least one example embodiment may include a plurality of unit capacitor DSPs. The plurality of unit capacitor DSPs may be arranged in a matrix pattern along a first direction X and a second direction Y, such as... Figure 1 As shown.

[0179] Multiple unit capacitors (DSPs) can be positioned on multiple landing pads (LPs). The multiple unit capacitors (DSPs) can completely or partially overlap with the multiple landing pads (LPs) in a third direction (Z). The multiple unit capacitors (DSPs) can be connected to a first active pattern (AP1) and a second active pattern (AP2).

[0180] Each unit capacitor DSP may include a first electrode 251, a second electrode 255, and a dielectric film 253 located between the first electrode 251 and the second electrode 255.

[0181] The first electrode 251 may pass through the contact etch stop layer 275 and connect to the bonding pad LP. The first electrode 251 may extend along a third direction Z on the landing pad LP.

[0182] The first electrode 251 may comprise a conductive material, such as a metal, a conductive metal nitride, or a combination thereof. For example, the first electrode 251 may comprise at least one of TiN, Ru, TaN, WN, Pt, Ir, combinations thereof, and / or the like. However, the material comprised in the first electrode 251 is not limited thereto and can be varied.

[0183] The dielectric film 253 can be extended to conform to the contours of the upper and side surfaces of the first electrode 251. In other words, the dielectric film 253 can cover the side and upper surfaces of the first electrode 251. A portion of the dielectric film 253 can be positioned on the upper surface of the contact etch stop layer 275. In other words, a portion of the dielectric film 253 can be positioned between the contact etch stop layer 275 and the second electrode 255.

[0184] The dielectric film 253 may contain a dielectric material, such as at least one of tantalum oxide (Ta2O5), aluminum oxide (Al2O3), titanium oxide (TiO2), or combinations thereof. However, this disclosure is not limited thereto, and the materials contained in the dielectric film 253 may be varied.

[0185] The second electrode 255 can be positioned on the dielectric film 253. The second electrode 255 can completely cover the first electrode 251, and the dielectric film 253 can electrically insulate the second electrode 255 from the first electrode 251. In other words, the second electrode 255 can cover the upper surface and side surface of the first electrode 251.

[0186] The second electrode 255 may comprise a conductive material, such as a metallic material. In at least some embodiments, the second electrode 255 may comprise at least one of W, Ti, Ru, SiGe, etc. For example, the second electrode 255 may comprise tungsten (W). However, the material comprised in the second electrode 255 is not limited to this and can be varied. For example, the second electrode 255 may comprise a conductive metal nitride, a metal silicide, or a combination thereof.

[0187] The semiconductor device according to at least one example embodiment may further include a third unit insulating layer 277 and a fourth unit insulating layer 279 sequentially stacked on a contact etch stop layer 275.

[0188] Furthermore, the semiconductor device according to at least one exemplary embodiment may also include a first unit wiring contact 261 and a first unit wiring 262 located in the third unit insulating layer 277, and a second unit wiring contact 263 and a second unit wiring 264 located in the fourth unit insulating layer 279.

[0189] The third unit insulating layer 277 can completely cover the unit capacitor DSP. In other words, the third unit insulating layer 277 can also cover the upper and side surfaces of the unit capacitor DSP.

[0190] The unit capacitor DSP can be connected to the first unit wiring 262 through the first unit wiring contact 261, and the first unit wiring 262 can be connected to the second unit wiring 264 through the second unit wiring contact 263.

[0191] In at least one example embodiment, the first unit wiring 262 may be wiring to which an external voltage is applied, or a redistribution layer (RDL) connected to wiring to which an external voltage is applied. At least a portion of the second unit wiring 264 may correspond to a power line to which an external voltage is applied. However, this is an example, and the functions of the first unit wiring 262 and the second unit wiring 264 may vary.

[0192] The first unit wiring contact 261, the first unit wiring 262, the second unit wiring contact 263, and the second unit wiring 264 may contain conductive materials, such as metallic materials. For example, the first unit wiring contact 261, the first unit wiring 262, the second unit wiring contact 263, and the second unit wiring 264 may each contain at least one of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta), combinations thereof, and / or the like.

[0193] The following is for reference Figure 3 and Figure 4 Detailed description of multiple shielding patterns SP.

[0194] refer to Figure 4 and Figure 3 Each of the first active pattern AP1 and the second active pattern AP2 may include a first doped region SDR1 connected to the bit line BL, a second doped region SDR2 connected to the unit capacitor DSP, and a channel region CHR located between the first doped region SDR1 and the second doped region SDR2.

[0195] The second doped region SDR2 can be connected to the cell capacitor DSP via the storage contact BC and the landing pad LP. In other words, the second doped region SDR2 can be directly connected to the storage contact BC.

[0196] The first dopant region SDR1 and the second dopant region SDR2 are regions doped with impurities within the first active pattern AP1 and the second active pattern AP2, and the impurity concentration in the first dopant region SDR1 and the second dopant region SDR2 can be greater than the impurity concentration in the channel region CHR.

[0197] The first active pattern AP1 and the second active pattern AP2 can be controlled by word lines WL1 and WL2 and / or the back gate electrode BG, as described below, during operation of the semiconductor device. As mentioned above, in at least one example embodiment, when the first active pattern AP1 and the second active pattern AP2 contain single-crystal semiconductor material, the leakage current characteristics of the semiconductor memory device can be improved.

[0198] The first doped region SDR1 and the second doped region SDR2 of the active patterns AP1 and AP2 can correspond to the first source / drain electrode and the second source / drain electrode of the storage transistor MT, and the channel region CHR can correspond to the channel of the storage transistor MT.

[0199] In at least one example embodiment, the thickness of word lines WL1 and WL2 in the third direction Z can be the same as (or substantially similar to) the thickness of the back gate electrode BG in the third direction Z. In other words, the upper and lower surfaces of word lines WL1 and WL2 can be positioned at the same (or substantially similar to) the levels of the upper and lower surfaces of the back gate electrode BG, respectively. However, this disclosure is not limited thereto, and either or both of the upper and lower surfaces of word lines WL1 and WL2 can be positioned at a level different from the levels of the upper and lower surfaces of the back gate electrode BG.

[0200] Furthermore, in some example embodiments, the thickness of the first word line WL1 and the second word line WL2 in the third direction Z can be less than the thickness of the first active pattern AP1 and the second active pattern AP2 in the third direction Z. However, the relationship between the thickness of the word lines WL1 and WL2 in the third direction Z and the thickness of the back gate electrode BG in the third direction Z, the arrangement relationship between the word lines WL1 and WL2 and the back gate electrode BG, and the relationship between the thickness of the word lines WL1 and WL2 in the third direction Z and the thickness of the active patterns AP1 and AP2 in the third direction Z are not limited to this and can be varied.

[0201] In at least one example embodiment, the shielding pattern SP may overlap with at least one second dopant region SDR2 of the active patterns AP1 and AP2 in a second direction Y, which is a horizontal direction. Furthermore, the shielding pattern SP may be located at a higher level than the channel region CHR so as not to overlap with the channel region CHR in the second direction Y.

[0202] The thickness of the shielding pattern SP in the third direction Z can be less than the thickness of the second doped region SDR2 in the third direction Z. Accordingly, the shielding pattern SP can overlap a portion of the second doped region SDR2 in the second direction Y. In other words, the shielding pattern SP can overlap the second doped region SDR2 in a direction that intersects the extension direction of the second doped region SDR2 of each of the active patterns AP1 and AP2.

[0203] The first shielding pattern SP1 may include a first surface SP1_S1 and a second surface SP1_S2 facing each other in the third direction Z. The first surface SP1_S1 of the first shielding pattern SP1 may contact the first shielding insulation pattern 113, and the second surface SP1_S2 may contact the first shielding cover pattern 115.

[0204] The first shielding insulation pattern 113 may surround the first surface SP1_S1 of the first shielding pattern SP1, and the first side surface SP1_S3 and the second side surface SP1_S4 of the first shielding pattern SP1 facing each other in the second direction Y.

[0205] The first shielding insulation pattern 113 may extend conformally along the first surface SP1_S1, the first side surface SP1_S3, and the second side surface SP1_S4 of the first shielding pattern SP1. In other words, the first shielding insulation pattern 113 may extend along the first surface SP1_S1, the first side surface SP1_S3, and the second side surface SP1_S4 of the first shielding pattern SP1 with substantially the same thickness. However, this disclosure is not limited thereto, and the thickness of the first shielding insulation pattern 113 located on the first surface SP1_S1 of the first shielding pattern SP1 may be different from the thickness of the first shielding insulation pattern 113 located on the first side surface SP1_S3 and the second side surface SP1_S4 of the first shielding pattern SP1.

[0206] The upper surface of the first shielding insulating pattern 113 can be positioned at substantially the same level as the upper surface of the first back gate insulating pattern 111 and the upper surface of the first shielding cover pattern 115. The upper surface of the first shielding insulating pattern 113 can contact the interlayer insulating layer 271.

[0207] The second shielding pattern SP2 may include a first surface SP2_S1 and a second surface SP2_S2 facing each other in the third direction Z. The first surface SP2_S1 of the second shielding pattern SP2 may contact the second shielding insulation pattern 143, and the second side surface SP2_S2 may contact the second shielding cover pattern 145.

[0208] Here, the first surface SP1_S1 of the first shielding pattern SP1 can correspond to the lower surface, and the second surface SP1_S2 can correspond to the upper surface. Similarly, the first surface SP2_S1 of the second shielding pattern SP2 can correspond to the lower surface, and the second surface SP2_S2 can correspond to the upper surface.

[0209] The second shielding insulation pattern 143 may surround the first surface SP2_S1 of the second shielding pattern SP2, and the first side surface SP2_S3 and the second side surface SP2_S4 of the second shielding pattern SP2 that face each other in the second direction Y.

[0210] The second shielding insulation pattern 143 may extend conformally along the first surface SP2_S1, the first side surface SP2_S3, and the second side surface SP2_S4 of the second shielding pattern SP2. In other words, the second shielding insulation pattern 143 may extend along the first surface SP2_S1, the first side surface SP2_S3, and the second side surface SP2_S4 of the second shielding pattern SP2 with substantially the same thickness. However, this disclosure is not limited thereto, and the thickness of the second shielding insulation pattern 143 positioned on the first surface SP2_S1 of the second shielding pattern SP2 may be different from the thickness of the second shielding insulation pattern 143 positioned on the first side surface SP2_S3 and the second side surface SP2_S4 of the second shielding pattern SP2.

[0211] The upper surface of the second shielding insulating pattern 143 may contact the storage contact BC. A portion of the second shielding cover pattern 145 may be recessed into the storage contact BC. In other words, the upper surface of the second shielding cover pattern 145 may be recessed into the storage contact BC and include a curved surface. The upper surface of the second shielding cover pattern 145 may be positioned at a lower level than the upper surface of the gate isolation pattern 141.

[0212] The first shielding insulation pattern 113 and the second shielding insulation pattern 143 may surround the first shielding pattern SP1 and the second shielding pattern SP2 with the same (or substantially similar) thickness, respectively.

[0213] Specifically, the thickness of the first shielding insulation pattern 113 located on the first surface SP1_S1 of the first shielding pattern SP1 in the third direction Z and the thickness of the second shielding insulation pattern 143 located on the first surface SP2_S1 of the second shielding pattern SP2 in the third direction Z can be substantially the same.

[0214] Furthermore, the thickness of the first shielding insulating pattern 113 on the two side surfaces SP1_S3 and SP1_S4 of the first shielding pattern SP1 in the second direction Y can be the same as (or substantially similar to) the thickness of the second shielding insulating pattern 143 on the two side surfaces SP2_S3 and SP2_S4 of the second shielding pattern SP2 in the second direction Y. However, this disclosure is not limited thereto, and the first shielding insulating pattern 113 and the second shielding insulating pattern 143 can surround the first shielding pattern SP1 and the second shielding pattern SP2 with different thicknesses, respectively.

[0215] Among the multiple second shielding patterns SP2, the first side surface SP2_S3 of the second shielding pattern SP2 located on word lines WL1 and WL2 can face the gate isolation pattern 141, in which the second shielding insulating pattern 143 is inserted, and the second side surface SP2_S4 can face the gate insulating pattern GOX, in which the second shielding insulating pattern 143 is inserted.

[0216] In at least one example embodiment, the back gate electrode BG may have a first width W1, and the word lines WL1 and WL2 may have a second width W2. The first shielding pattern SP1 may have a third width W3, and the second shielding pattern SP2 may have a fourth width W4.

[0217] Furthermore, the first shielding cover pattern 115 located on the first shielding pattern SP1 may have a third width W3, and the second shielding cover pattern 145 located on the second shielding pattern SP2 may have a fourth width W4. In other words, the first shielding cover pattern 115 may have the same (or substantially similar) width as the first shielding pattern SP1, and the second shielding cover pattern 145 may have the same (or substantially similar) width as the second shielding pattern SP2.

[0218] Here, the first width W1, the second width W2, the third width W3, and the fourth width W4 can each refer to the width in the second direction Y.

[0219] In at least one example embodiment, the first width W1 may be greater than the second width W2, the third width W3, and the fourth width W4. In other words, the width of the back gate electrode BG may be greater than the width of the first shielding pattern SP1, the width of each word line in word lines WL1 and WL2, and the width of the second shielding pattern SP2.

[0220] The second width W2 can be smaller than the first width W1 and the third width W3, and larger than the fourth width W4. In other words, the width of each word line in word lines WL1 and WL2 can be smaller than the width of the back gate electrode BG and the width of the first shielding pattern SP1, and larger than the width of the second shielding pattern SP2.

[0221] The third width W3 can be smaller than the first width W1 and larger than the second width W2 and the fourth width W4. In other words, the width of the first shielding pattern SP1 can be smaller than the width of the back gate electrode BG and larger than the width of each word line in word lines WL1 and WL2 and the width of the second shielding pattern SP2.

[0222] The fourth width W4 can be smaller than the first width W1, the second width W2, and the third width W3. In other words, the width of the second shielding pattern SP2 can be smaller than the widths of the back gate electrode BG, the first shielding pattern SP1, and the word lines WL1 and WL2, respectively. However, this disclosure is not limited thereto, and the relationship between the first width W1, the second width W2, the third width W3, and the fourth width W4 can be varied.

[0223] In some example embodiments, the first width W1 and the second width W2 may be the same or substantially similar. In other words, the width of the back gate electrode BG may be the same as (or substantially similar to) the width of each of the word lines WL1 and WL2.

[0224] In these cases, the third width W3 of the first shielding pattern SP1 and the fourth width W4 of the second shielding pattern SP2 located on the back gate electrode BG and word lines WL1 and WL2, respectively, can be substantially the same.

[0225] In some example embodiments, when the first shielding insulating pattern 113 positioned on the two side surfaces SP1_S3 and SP1_S4 of the first shielding pattern SP1 is omitted, the first width W1 and the third width W3 can be substantially the same. In other words, when the first shielding insulating pattern 113 positioned on the two side surfaces SP1_S3 and SP1_S4 of the first shielding pattern SP1 is omitted, the width of the back gate electrode BG and the width of the first shielding pattern SP1 can be substantially the same.

[0226] Furthermore, when the second shielding insulation pattern 143 located on the two side surfaces SP1_S3 and SP1_S4 of the second shielding pattern SP2 is omitted, the second width W2 and the fourth width W4 can be substantially the same. In other words, when the second shielding insulation pattern 143 located on the two side surfaces SP1_S3 and SP1_S4 of the second shielding pattern SP2 is omitted, the width of each of the word lines WL1 and WL2 and the width of the second shielding pattern SP2 can be substantially the same.

[0227] In at least one example embodiment, the first shielding pattern SP1 may have a first thickness T1, and the second shielding pattern SP2 may have a second thickness T2.

[0228] Here, the first thickness T1 can refer to the thickness of the first surface SP1_S1 and the second surface SP1_S2 of the first shielding pattern SP1 in the third direction Z, and the second thickness T2 can refer to the thickness of the first surface SP2_S1 and the second surface SP2_S2 of the second shielding pattern SP2 in the third direction Z.

[0229] In at least one example embodiment, the first thickness T1 may be the same as (or substantially similar to) the second thickness T2. In other words, the thickness of the first shielding pattern SP1 may be the same as (or substantially similar to) the thickness of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the relationship between the first thickness T1 and the second thickness T2 may vary.

[0230] In at least one example embodiment, the first surface SP1_S1 of the first shielding pattern SP1 may be positioned at substantially the same level as the first surface SP2_S1 of the second shielding pattern SP2. Furthermore, the second surface SP1_S2 of the first shielding pattern SP1 may be positioned on substantially the same horizontal plane as the second surface SP2_S2 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 can be varied.

[0231] In some example embodiments, the thickness of the first shielding insulating pattern 113 on the first surface SP1_S1 of the first shielding pattern SP1 in the third direction Z may be different from the thickness of the second shielding insulating pattern 143 on the first surface SP2_S1 of the second shielding pattern SP2 in the third direction Z, or the first thickness T1 of the first shielding pattern SP1 may be different from the second thickness T2 of the second shielding pattern SP2.

[0232] Accordingly, the horizontal relationship between the first surface SP1_S1 of the first shielding pattern SP1 and the first surface SP2_S1 of the second shielding pattern SP2, and / or the horizontal relationship between the second surface SP1_S2 of the first shielding pattern SP1 and the second surface SP2_S2 of the second shielding pattern SP2 can be changed in various ways.

[0233] In at least one example embodiment, the work function of the shielding pattern SP can be lower than or substantially equal to the work function of the second doped region SDR2 of each of the active patterns AP1 and AP2. In other words, the work function of the shielding pattern SP can be substantially the same as, or less than, the work function of the second doped region SDR2 of each of the active patterns AP1 and AP2.

[0234] Furthermore, the work function of the shielding pattern SP can be greater than or substantially equal to the work function of the storage contact BC. In other words, the work function of the shielding pattern SP can be substantially the same as or greater than the work function of the storage contact BC.

[0235] Therefore, the work function of the shielding pattern SP can be greater than or substantially equal to the work function of the storage contact BC, and less than or substantially equal to the work function of the second doped region SDR2 of each of the plurality of active patterns AP1 and AP2. However, this disclosure is not limited thereto, and the relationship between the work function of the shielding pattern SP, the work function of the second doped region SDR2 of each of the plurality of active patterns AP1 and AP2, and the work function of the storage contact BC can be varied.

[0236] Although not shown, in some example embodiments, when the storage contact BC is omitted and the second doped region SDR2 of each of the plurality of active patterns AP1 and AP2 is directly connected to the unit capacitor DSP, the work function of the shielding pattern SP may be lower than or substantially equal to the work function of the second doped region SDR2. In other words, when the storage contact BC is omitted, the work function of the shielding pattern SP may be the same as (or substantially similar to) or less than the work function of the second doped region SDR2.

[0237] Here, the work function of the shielding pattern SP can refer to the effective work function, which can be determined by the type of material or the concentration of impurities contained in the shielding pattern SP. In other words, the effective work function of a particular material can refer to the intrinsic property of the material, which is defined as the energy required for an electron to be emitted from an atom of the material into a vacuum when the electron is initially at the Fermi level within the material, and thus the work function of the material depends on the composition of the material.

[0238] Thus, when the work function of the shielding pattern SP is substantially the same as or less than the work function of the second doped region SDR2 of each active pattern AP1 and AP2, an electric field can be prevented from occurring between the shielding pattern SP and the adjacent second doped region SDR2. Alternatively, an electric field can be formed between them to improve the electrical characteristics of the storage transistor.

[0239] Specifically, when the work function of the shielding pattern SP is the same as (or substantially similar to) the work function of the second doped region SDR2, the electric field between the shielding pattern SP and the second doped region SDR2 can be prevented, thereby preventing the occurrence of gate-induced drain leakage (GIDL) current in the storage transistor. Furthermore, when the work function of the shielding pattern SP is less than the work function of the second doped region SDR2, the electric field formed between the shielding pattern SP and the second doped region SDR2 can suppress the occurrence of GIDL current in the storage transistor.

[0240] In addition, when the work function of the shielding pattern SP is the same as (or substantially similar to) the work function of the storage contact BC, the electric field between the shielding pattern SP and the storage contact BC can be prevented.

[0241] Furthermore, since the work function of the shielding pattern SP is greater than that of the storage contact BC, an electric field can be formed between the shielding pattern SP and the storage contact BC. In these cases, as described above, since the work function of the shielding pattern SP is less than or substantially equal to the work function of the second dopant region SDR2, the gate-induced drain leakage (GIDL) current of the storage transistor can be prevented or suppressed by the storage contact BC.

[0242] In at least one example embodiment, each of the shielding pattern SP and the storage contact BC may comprise polysilicon doped with impurities.

[0243] Specifically, when the storage contact BC comprises polysilicon doped with impurities, the concentration of impurities doped into the shielding pattern SP can be the same as (or substantially similar to) or less than the concentration of impurities doped into the storage contact BC. In other words, the concentration of impurities included in the shielding pattern SP can be less than or substantially equal to the concentration of impurities included in the storage contact BC.

[0244] Furthermore, the concentration of impurities doped into the shielding pattern SP can be the same as (or substantially similar to) the concentration of impurities in the second doped region SDR2 of each of the multiple active patterns AP1 and AP2, or greater than the concentration of impurities in the second doped region SDR2 of each of the multiple active patterns AP1 and AP2. In other words, the concentration of impurities included in the shielding pattern SP can be greater than or substantially equal to the concentration of impurities included in the second doped region SDR2.

[0245] This may be a result of the fact that, in subsequent thermal processing steps, as impurities diffuse from the storage contact BC to the second dopant region SDR2 of each of the plurality of active patterns AP1 and AP2, the impurity concentration has a decreasing concentration gradient from the storage contact BC to the second dopant region SDR2. However, this disclosure is not limited thereto, and the relationship between the concentrations of impurities included in the shielding pattern SP, the concentrations of impurities included in the second dopant region SDR2 of each of the plurality of active patterns AP1 and AP2, and the concentrations of impurities included in the storage contact BC can be varied differently.

[0246] The effective work function of a particular material can be determined by the concentration of impurities doped into that material. In other words, as the concentration of impurities doped into a particular material changes, the work function may change accordingly due to changes in the electron density or electron structure within the material.

[0247] Specifically, as described above, since the concentration of impurities included in the shielding pattern SP is the same as (or substantially similar to) or less than the concentration of impurities included in the storage contact BC, the effective work function of the shielding pattern SP can be the same as (or substantially similar to) or greater than the effective work function of the storage contact BC.

[0248] Furthermore, as described above, since the impurity concentration included in the shielding pattern SP is the same as (or substantially similar to) or greater than the impurity concentration in the second dopant region SDR2 of each active pattern included in the active patterns AP1 and AP2, the effective work function of the shielding pattern SP can be the same as (or substantially similar to) or less than the effective work function of the second dopant region SDR2.

[0249] In some example embodiments, when the storage contact BC and the second dopant region SDR2 of each of the plurality of active patterns AP1 and AP2 have the same (or substantially similar) impurity concentration, the impurity concentration included in the shielding pattern SP may be the same (or substantially similar) or greater than the impurity concentration included in each of the storage contact BC and the second dopant region SDR2.

[0250] In these cases, the work function of the shielding pattern SP can be less than each of the work function of the storage contact BC and the work function of the second doped region SDR2, or it can be the same as (or substantially similar to) each of the work functions of the storage contact BC and the second doped region SDR2. Furthermore, the work function of the storage contact BC can be the same as (or substantially similar to) the work function of the second doped region SDR2.

[0251] Here, the term "doping" can refer to an intentional doping process that has been performed. Furthermore, the concentration of impurities included in each of the shielding pattern SP, the storage contact BC, and the second dopant regions SDR2 of the active patterns AP1 and AP2 can refer to the average concentration of impurities over the total area of ​​each of the shielding pattern SP, the storage contact BC, and the second dopant regions SDR2.

[0252] In at least one example embodiment, the impurities included in each of the shielding pattern SP, the storage contact BC, and the second dopant regions SDR2 of the active patterns AP1 and AP2 can be n-type impurities. In other words, the concentration of n-type impurities included in the shielding pattern SP can be greater than or substantially equal to the concentration of n-type impurities included in the second dopant regions SDR2, and the concentration of n-type impurities included in the shielding pattern SP can be less than or equal to the concentration of n-type impurities included in the storage contact BC.

[0253] n-type impurities may include at least one of, for example, phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), and / or the like. However, this disclosure is not limited thereto, and the type and / or concentration relationship of impurities in each of the second dopant regions SDR2 of the shielding pattern SP, the storage contact BC, and the active patterns AP1 and AP2 may vary.

[0254] In some example embodiments, the shielding pattern SP may include a metallic material having the same (or substantially similar) or similar work function to the second dopant region SDR2 of each of the active patterns AP1 and AP2.

[0255] Specifically, when the first active pattern AP1, the second active pattern AP2, and the storage contact BC are doped with n-type impurities, the shielding pattern SP may include a metallic material having an n-type work function.

[0256] Here, a metallic material having an n-type work function can refer to a material having a work function that is the same as (or substantially similar to) or similar to that of polycrystalline silicon doped with n-type impurities. For example, the work function of a metallic material having an n-type work function may be less than or substantially equal to the work function of the second dopant region SDR2 of the active patterns AP1 and AP2 including n-type impurities, and greater than or substantially equal to the work function of the storage contact BC. However, this disclosure is not limited thereto, and the work function of a metallic material having an n-type work function can be varied differently.

[0257] Metallic materials with an n-type work function may include, for example, at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), and / or combinations thereof.

[0258] In some example embodiments, when the shielding pattern SP has a multilayer structure, the shielding pattern SP may contain at least one of TiN / TiON, Mg / TiN, TiN / Mg / TiN, La / TiN, TiN / La / TiN, Sr / TiN, TiN / Sr / TiN, and / or combinations thereof. However, this disclosure is not limited thereto, and the metallic material with an n-type work function included in the shielding pattern SP may be varied.

[0259] In some example embodiments, some of the plurality of shielding patterns SP may comprise impurity-doped polysilicon, while others may comprise a metallic material having an n-type work function. For example, a first shielding pattern SP1 may comprise impurity-doped polysilicon, and a second shielding pattern SP2 may comprise a metallic material having an n-type work function. As another example, a first shielding pattern SP1 may comprise a metallic material having an n-type work function, and a second shielding pattern SP2 may comprise impurity-doped polysilicon.

[0260] Since the shielding pattern SP is located between the second doped regions SDR2 of adjacent active patterns AP1 and AP2, the interference between the second doped regions SDR2 of adjacent active patterns AP1 and AP2 can be reduced.

[0261] Furthermore, the shielding pattern SP can reduce interference between the storage contact BC connected to the second doped region SDR2 of one of the active patterns AP1 and AP2 and the second doped region SDR2 of the other active pattern AP1 and AP2. In other words, the shielding pattern SP can reduce interference between adjacent storage contacts BC in the diagonal direction intersecting the second direction Y and the third direction Z in the cross section and the second doped region SDR2 of the active patterns AP1 and AP2.

[0262] In at least one example embodiment, when the shielding pattern SP contains doped polysilicon, the strength of the electric field formed between the shielding pattern SP and the storage contact BC is relatively weakened compared to when the shielding pattern SP contains metallic material, such that interference between adjacent storage contacts BC and the second dopant SDR2 of each of the active patterns AP1 and AP2 can be improved.

[0263] Furthermore, in at least one example embodiment, when the shielding pattern SP comprises polycrystalline silicon doped with impurities, the work function of the shielding pattern SP can be controlled by changing the concentration of impurities included in the shielding pattern SP, compared to when the shielding pattern SP comprises metallic material.

[0264] When the shielding pattern SP is formed from polycrystalline silicon doped with impurities, the concentration of impurities included in the shielding pattern SP can be adjusted based on the concentration of impurities in the active patterns AP1 and AP2, compared to when the shielding pattern SP is formed from a metallic material with a fixed work function.

[0265] Therefore, the electrical characteristics of semiconductor devices can be improved by protecting them from (e.g., preventing or suppressing) gate-induced drain leakage current in storage transistors.

[0266] In the following text, reference will be made to Figures 5 to 15 The following describes semiconductor devices according to various embodiments. In the following example embodiments, components that are the same as (or substantially similar to) those in the above embodiments will be indicated by the same reference numerals, and their redundant descriptions will be omitted or will be brief, with the differences from the above embodiments being described primarily.

[0267] Figures 5 to 11 This is a partially enlarged cross-sectional view showing a semiconductor device according to some example embodiments. Specifically, Figures 5 to 11 This illustrates the relationship between [examples] and [examples] according to some example embodiments. Figure 3 A magnified view of the corresponding regions P2 to P8 of region P1.

[0268] according to Figure 5 and Figure 6 The semiconductor device of at least one example embodiment shown differs from the semiconductor device according to the above embodiment in the arrangement of the shielding pattern SP.

[0269] according to Figure 5 In at least one example embodiment shown, unlike the semiconductor device including region P1 according to the at least one example embodiment described above, the shielding pattern SP may be located on word lines WL1 and WL2, and may not be located on the back gate electrode BG. In other words, compared with... Figure 4 Unlike at least one example embodiment shown, the first shielding pattern located on the back gate electrode BG may be omitted (see [reference]). Figure 4 (See the attached figure labeled "SP1").

[0270] Furthermore, since the shielding pattern SP is omitted on the back gate electrode BG, it is similar to... Figure 4 Unlike at least one example embodiment shown, the first shielding insulating pattern located on the back gate electrode BG may be omitted (see [reference]). Figure 4 (See attached figure numeral "113").

[0271] In at least one example embodiment, the shielding pattern SP may be located on one side of the second dopant region SDR2 of each of the active patterns AP1 and AP2, and the back gate cover pattern 116 may be located on the other side of the second dopant region SDR2.

[0272] Specifically, the back gate cover pattern 116 located on the back gate electrode BG may include a first surface and a second surface facing each other in the third direction Z. Here, the first surface may refer to the lower surface of the back gate cover pattern 116, and the second surface may refer to the upper surface of the back gate cover pattern 116.

[0273] The first surface of the back gate cover pattern 116 can contact the back gate electrode BG, and the second surface can contact the interlayer insulating layer 271. The thickness of the back gate cover pattern 116 in the third direction Z can be greater than the thickness of the shielding pattern SP in the third direction Z. However, this disclosure is not limited thereto, and the relationship between the thickness of the back gate cover pattern 116 in the third direction Z and the thickness of the shielding pattern SP in the third direction Z can be varied.

[0274] The shielding pattern SP located on word lines WL1 and WL2 may include a first surface and a second surface facing each other in the third direction Z. Here, the first surface may refer to the lower surface of the shielding pattern SP, and the second surface may refer to the upper surface of the shielding pattern SP.

[0275] The first surface of the back gate cover pattern 116 may be positioned at a different level than the first surface of the shielding pattern SP, and the second surface of the back gate cover pattern 116 may be positioned at a different level than the second surface of the shielding pattern SP. For example, the first surface of the back gate cover pattern 116 may be positioned at a lower level than the first surface of the shielding pattern SP, and the second surface of the back gate cover pattern 116 may be positioned at a higher level than the second surface of the shielding pattern SP.

[0276] Furthermore, the first surface of the back gate cover pattern 116 may be located at the same (or substantially similar) level as the lower surface of the shielding insulating pattern 142, which surrounds the first surface of the shielding pattern SP, the two side surfaces of the shielding pattern SP, and the two side surfaces of the shielding cover pattern 144. However, this disclosure is not limited thereto, and the arrangement relationship between the back gate cover pattern 116 and the shielding pattern SP and / or the arrangement relationship between the back gate cover pattern 116 and the shielding insulating pattern 142 may be varied.

[0277] according to Figure 6 In at least one example embodiment shown, unlike the semiconductor device including region P1, the shielding pattern SP may be located on the back gate electrode BG and may not be located on word lines WL1 and WL2. In other words, compared with... Figure 4 Unlike at least one example embodiment shown, the second shielding pattern located on word lines WL1 and WL2 may be omitted (see [reference]). Figure 4 (See the attached figure labeled "SP2").

[0278] Furthermore, since the shielding pattern SP is omitted on the word lines WL1 and WL2, it is consistent with... Figure 4 Unlike at least one example embodiment shown, the second shielding insulation pattern located on word lines WL1 and WL2 may be omitted (see [reference]). Figure 4 (See attached figure "143").

[0279] In at least one example embodiment, the shielding pattern SP may be located on one side of the second dopant region SDR2 of each of the active patterns AP1 and AP2, and the word line capping layer 146 may be located on the other side of the second dopant region SDR2.

[0280] Specifically, the word line cover 146 may include a first surface and a second surface facing each other in a third direction Z. The first surface of the word line cover 146 may contact word lines WL1 and WL2, and the second surface may contact storage contact BC. Here, the first surface may refer to the lower surface of the word line cover 146, and the second surface may refer to the upper surface of the word line cover 146.

[0281] The shielding pattern SP positioned on the back gate electrode BG may include a first surface and a second surface facing each other in the third direction Z. Here, the first surface may refer to the lower surface of the shielding pattern SP, and the second surface may refer to the upper surface of the shielding pattern SP.

[0282] The first surface of the word line cover 146 may be positioned at a different level than the first surface of the shielding pattern SP, and the second surface of the word line cover 146 may be positioned at a different level than the second surface of the shielding pattern SP. For example, the first surface of the word line cover 146 may be positioned at a lower level than the first surface of the shielding pattern SP, and the second surface of the word line cover 146 may be positioned at a higher level than the second surface of the shielding pattern SP.

[0283] In at least one example embodiment, the second surface of the word line cover 146 may include a curved surface, since the second surface is stored in contact with the BC recess.

[0284] In at least one example embodiment, the first surface of the word line cover 146 may be located at the same (or substantially similar) level as the lower surface of the shielding insulating pattern 112, which surrounds the first surface of the shielding pattern SP, the two side surfaces of the shielding pattern SP, and the two side surfaces of the shielding cover pattern 114. However, this disclosure is not limited thereto, and the arrangement relationship between the word line cover 146 and the shielding pattern SP and / or the arrangement relationship between the word line cover 146 and the shielding insulating pattern 112 may be varied.

[0285] Figure 5 and Figure 6 At least one example embodiment shown can be the result of forming the shielding pattern SP on the word lines WL1 and WL2 and the shielding pattern SP on the back gate electrode BG by separate processes. In other words, by omitting the process steps of forming the shielding pattern SP on the word lines WL1 and WL2 or the process steps of forming the shielding pattern SP on the back gate electrode BG, as in Figure 5 and Figure 6 As shown in at least one example embodiment, the shielding pattern SP can be formed only on the word lines WL1 and WL2 or the back gate electrode BG.

[0286] according to Figure 5 and Figure 6 The semiconductor device of at least one example embodiment shown can have the same (or substantially similar) effects as the semiconductor device according to the embodiments described above. In other words, when the shielding pattern SP is formed on one side of each of the active patterns AP1 and AP2, coupling caused by interference between the doped regions of the adjacent active patterns AP1 and AP2 and the word lines WL1 and WL2 inserted therebetween can be improved, or coupling caused by interference between the doped regions of the adjacent active patterns AP1 and AP2 and the back gate electrode BG inserted therebetween.

[0287] According to Figure 7 and Figure 8The semiconductor device of the example embodiment shown has a different thickness and / or width of the shielding pattern SP compared to the semiconductor device according to the example embodiment described above.

[0288] according to Figure 7 The semiconductor device of at least one example embodiment shown differs from the semiconductor device including region P1 according to the above embodiment in that the thickness of the first shielding pattern SP1 in the third direction Z is different from the thickness of the second shielding pattern SP2 in the third direction Z.

[0289] In at least one example embodiment, the thickness of the first shielding insulating pattern 113 surrounding the first shielding pattern SP1 and the thickness of the second shielding insulating pattern 143 surrounding the second shielding pattern SP2 may be the same or substantially similar.

[0290] In at least one example embodiment, the first shielding pattern SP1 may have a first thickness T1, and the second shielding pattern SP2 may have a second thickness T2. The first thickness T1 may be greater than the second thickness T2. In other words, the thickness of the first shielding pattern SP1 may be greater than the thickness of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the relationship between the first thickness T1 and the second thickness T2 may vary. For example, the first thickness T1 may be less than the second thickness T2.

[0291] In at least one example embodiment, the first surface SP1_S1 of the first shielding pattern SP1 may be positioned at the same or substantially similar level to the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 may be positioned at a higher level than the second surface SP2_S2 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 may be changed differently as the thickness relationship between the first shielding pattern SP1 and the second shielding pattern SP2 and / or the thickness relationship between the first shielding insulating pattern 113 and the second shielding insulating pattern 143 are changed differently. For example, when the second thickness T2 of the second shielding pattern SP2 is greater than the first thickness T1 of the first shielding pattern SP1, the first surface SP1_S1 of the first shielding pattern SP1 may be located at the same (or substantially similar) level to the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 may be located at a lower level than the second surface SP2_S2 of the second shielding pattern SP2.

[0292] according to Figure 8 The semiconductor device shown in at least one example embodiment is in accordance with... Figure 4The difference between the semiconductor device including region P1 in the above embodiment shown is that the thicknesses of the first shielding insulating pattern 113 and the second shielding insulating pattern 143 are different.

[0293] In at least one example embodiment, the thickness of the first shielding insulating pattern 113 surrounding the first surface SP1_S1 and the two side surfaces SP1_S3 and SP1_S4 of the first shielding pattern SP1 may differ from the thickness of the second shielding insulating pattern 143 surrounding the first surface SP2_S1 and the two side surfaces SP2_S3 and SP2_S4 of the second shielding pattern SP2. For example, the thickness of the first shielding insulating pattern 113 in the second direction Y and the thickness in the third direction Z may be greater than the thickness of the second shielding insulating pattern 143 in the second direction Y and the third direction Z, respectively.

[0294] Therefore, according to Figure 4 Compared to the first shielding pattern SP1 of at least one example embodiment shown, the first shielding pattern SP1 according to this at least one example embodiment may have a smaller width in the second direction Y.

[0295] In at least one example embodiment, the third width W3 may be smaller than the first width W1 and the second width W2, and smaller than or equal to (or substantially similar to) the fourth width W4. In other words, the width of the first shielding pattern SP1 may be smaller than the widths of the back gate electrode BG and the word lines WL1 and WL2, respectively, and smaller than or equal to (or substantially similar to) the width of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the relationship between the first width W1, the second width W2, the third width W3, and the fourth width may vary. For example, with... Figure 8 Unlike the previous example, the third width W3 can be smaller than the first width W1 and the second width W2, and greater than or equal to (or substantially similar to) the fourth width W4. In other words, the width of the first shielding pattern SP1 can be smaller than the widths of the back gate electrode BG and the word lines WL1 and WL2, respectively, and greater than or equal to (or substantially similar to) the width of the second shielding pattern SP2.

[0296] In at least one example embodiment, the first thickness T1 of the first shielding pattern SP1 may be less than the second thickness T2 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the relationship between the first thickness T1 and the second thickness T2 may vary.

[0297] As described above, when the thickness of the first shielding insulation pattern 113 in the third direction Z is greater than the thickness of the second shielding insulation pattern 143 in the third direction Z, the first surface SP1_S1 of the first shielding pattern SP1 can be located at a higher level than the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 can be located at a substantially the same level as the second surface SP2_S2 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 can be varied.

[0298] With Figure 8 Unlike the example embodiments, in some example embodiments, when the first thickness T1 is less than the second thickness T2, due to the thickness difference between the first shielding insulation pattern 113 and the second shielding insulation pattern 143, the first surface SP1_S1 of the shielding pattern SP1 can be positioned at a higher level than the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 can be positioned at a higher level than the second surface SP2_S2 of the second shielding pattern SP2.

[0299] and Figure 8 In some example embodiments, due to the thickness difference between the first shielding insulation pattern 113 and the second shielding insulation pattern 143, when the first thickness T1 is greater than or equal to (or substantially similar to) the second thickness T2, the first surface SP1_S1 of the shielding pattern SP1 can be located at a higher level than the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 can be located at a higher level than the second surface SP2_S2 of the second shielding pattern SP2.

[0300] exist Figure 8 In this paper, the arrangement and width relationship of the first shielding pattern SP1 and the second shielding pattern SP2 are described when the thickness of the first shielding insulating pattern 113 is greater than the thickness of the second shielding insulating pattern 143. However, compared with... Figure 8 Unlike the example shown, in some example embodiments, the thickness of the first shielding insulation pattern 113 may be less than the thickness of the second shielding insulation pattern 143.

[0301] In this case, the above-mentioned arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 due to the thickness difference between the first shielding insulation pattern 113 and the second shielding insulation pattern 143 can be applied substantially the same way, and therefore will not be described in detail again.

[0302] according to Figure 9The semiconductor device of at least one example embodiment shown differs from the semiconductor device according to the above embodiment in that the width and arrangement of the second shielding pattern SP2 located on word lines WL1 and WL2 are different.

[0303] The above reference Figure 4 The description of the first shielding pattern SP1 may be the same as or substantially similar to the first shielding pattern SP1 according to the present at least one example embodiment, and therefore will not be described in detail.

[0304] Reference Figure 9 The back gate electrode BG may have a first width W1, word lines WL1 and WL2 may each have a second width W2, the first shielding pattern SP1 may have a third width W3, and the second shielding pattern SP2 may have a fourth width W4.

[0305] Here, the first width W1, the second width W2, the third width W3, and the fourth width W4 can refer to the width in the second direction Y.

[0306] In at least one example embodiment, the first width W1 may be greater than the second width W2 and the third width W3, and less than the fourth width W4. In other words, the width of the back gate electrode BG may be greater than the width of the first shielding pattern SP1 and the widths of the word lines WL1 and WL2, respectively, and less than the width of the second shielding pattern SP2.

[0307] The second width W2 can be smaller than the first width W1, the third width W3, and the fourth width W4. That is, the widths of the word lines WL1 and WL2 can be smaller than the widths of the back gate electrode BG, the first shielding pattern SP1, and the second shielding pattern SP2, respectively.

[0308] The third width W3 can be smaller than the first width W1 and the fourth width W4, and larger than the second width W2. In other words, the width of the first shielding pattern SP1 can be smaller than the width of the back gate electrode BG and the second shielding pattern SP, and larger than the width of each word line in word lines WL1 and WL2.

[0309] The fourth width W4 can be greater than the first width W1, the second width W2, and the third width W3. In other words, the width of the second shielding pattern SP2 can be greater than the widths of the back gate electrode BG, the first shielding pattern SP1, and the word lines WL1 and WL2, respectively.

[0310] Therefore, the width of the first shielding cover pattern 115 located on the first shielding pattern SP1 can be smaller than the width of the second shielding cover pattern 145 located on the second shielding pattern SP2.

[0311] In at least one example embodiment, the second shielding pattern SP2 may be located on word lines WL1 and WL2, which are situated between the first active pattern AP1 and the second active pattern AP2. In other words, the second shielding pattern SP2 may be positioned to overlap with the first word line WL1 and the second word line WL2 in the third direction Z.

[0312] Therefore, the second shielding pattern SP2 can be positioned to overlap with multiple word lines WL1 and WL2 in the third direction Z.

[0313] Furthermore, the second shielding pattern SP2 can be positioned to overlap with the gate isolation pattern 141 in the third direction Z. The second shielding pattern SP2 can cover the first word line WL1, the second word line WL2, and the gate isolation pattern 141.

[0314] In at least one example embodiment, the thickness of the first shielding insulating pattern 113 surrounding the first surface SP1_S1 and the two side surfaces SP1_S3 and SP1_S4 of the first shielding pattern SP1 can be the same as (or substantially similar to) the thickness of the second shielding insulating pattern 143 surrounding the first surface SP2_S1 and the two side surfaces SP2_S3 and SP2_S4 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the thickness of the first shielding insulating pattern 113 and the thickness of the second shielding insulating pattern 143 can be different.

[0315] In at least one example embodiment, the second shielding insulating pattern 143 may be located between the second shielding pattern SP2 and word lines WL1 and WL2, and between the second shielding pattern SP2 and gate isolation pattern 141. The second shielding insulating pattern 143 may extend along the first surface SP2_S1 of the second shielding pattern SP2 and may cover word lines WL1 and WL2, as well as gate isolation pattern 141.

[0316] In at least one example embodiment, the first shielding pattern SP1 has a first thickness T1, the second shielding pattern SP2 has a second thickness T2, and the first thickness T1 may be the same as (or substantially similar to) the second thickness T2.

[0317] Therefore, the first surface SP1_S1 of the first shielding pattern SP1 can be positioned at a substantially the same level as the first surface SP2_S1 of the second shielding pattern SP2, and the second surface SP1_S2 of the first shielding pattern SP1 can be positioned at a substantially the same level as the second surface SP2_S2 of the second shielding pattern SP2. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 can be changed differently depending on the thickness of the first shielding insulating pattern 113 and the second shielding insulating pattern 143.

[0318] With Figure 9 As shown, in some example embodiments, the first thickness T1 of the first shielding pattern SP1 may be different from the second thickness T2 of the second shielding pattern SP2. For example, the first thickness T1 may be greater than the second thickness T2. As another example, the first thickness T1 may be less than the second thickness T2.

[0319] Accordingly, the arrangement relationship between the first shielding pattern SP1 and the second shielding pattern SP2 can be changed in various ways.

[0320] according to Figure 9 The semiconductor device shown in at least one example embodiment can have substantially the same effect as the semiconductor device according to the above embodiments.

[0321] according to Figure 10 and Figure 11 The semiconductor device of at least one example embodiment shown differs from the semiconductor device according to the above embodiment in that the back gate electrode BG is omitted.

[0322] According to Figure 10 The semiconductor device of at least one example embodiment shown, with Figure 4 Unlike at least one example embodiment shown, the back gate electrode (see Figure 4 The figure shows the reference numeral "BG" and the back gate insulation pattern (see Figure 1). Figure 4 The reference numeral "111" in the figure is omitted, and may further include an isolation insulation pattern 150 and an isolation cover pattern 170 located between the first active pattern AP1 and the second active pattern AP2.

[0323] Furthermore, according to at least one example embodiment, a padding insulation pattern 110 may also be included to surround the side surfaces of the isolation insulation pattern 150, the isolation cover pattern 170, and the first shielding insulation pattern 113.

[0324] Specifically, refer to Figure 10 The first word line WL1 can be positioned on one side of the second direction Y of one of the active patterns AP1 and AP2, and the isolation insulation pattern 150 can be positioned on the other side of the second direction Y of said active patterns AP1 and AP2. Further, the isolation insulation pattern 150 can be positioned on one side of the second direction Y of the other active pattern AP1 and AP2, and the second word line WL2 can be positioned on the other side of the second direction Y of the other active pattern AP1 and AP2.

[0325] Therefore, word lines WL1 and WL2 can be located on either side of the active patterns AP1 and AP2.

[0326] The insulating pattern 150 may include a first surface 150_S1 and a second surface 150_S2 facing each other in a third direction Z. Here, the first surface 150_S1 may refer to the lower surface of the insulating pattern 150, and the second surface 150_S2 may refer to the upper surface.

[0327] The first surface 150_S1 of the insulating pattern 150 can be positioned at substantially the same level as the first surface of each of the word lines WL1 and WL2, and the second surface 150_S2 can be positioned at substantially the same level as the second surface of each of the word lines WL1 and WL2. However, this disclosure is not limited thereto, and the arrangement of the insulating pattern 150 with respect to the word lines WL1 and WL2 can be varied.

[0328] In at least one example embodiment, the first shielding pattern SP1 may be located on the isolation insulation pattern 150, and the second shielding pattern SP2 may be located on word lines WL1 and WL2, respectively.

[0329] The above reference Figures 4 to 9 The description of the first shielding pattern SP1 and the second shielding pattern SP2 can be applied substantially similarly to the first shielding pattern SP1 and the second shielding pattern SP2 according to the present at least one example embodiment, and therefore will not be described in detail.

[0330] The isolation cover pattern 170 can be positioned on the first surface 150_S1 of the isolation insulation pattern 150.

[0331] The padding insulation pattern 110 may extend in the third direction Z along each side surface of the sequentially stacked isolation cover pattern 170, isolation insulation pattern 150 and first shielding insulation pattern 113.

[0332] The first shielding insulation pattern 113 can be positioned between the isolation insulation pattern 150 and the first shielding pattern SP1. The first shielding insulation pattern 113 can be positioned between the first shielding pattern SP1 and the padding insulation pattern 110, and between the first shielding cover pattern 115 and the padding insulation pattern 110.

[0333] Each of the gasket insulation pattern 110, the isolation insulation pattern 150, and the isolation cover pattern 170 may contain an insulating material. For example, the insulating material may contain silicon oxide, silicon nitride, silicon nitride, etc., but is not limited to these, and various modifications may be made.

[0334] According to Figure 11 The semiconductor device of at least one example embodiment shown, with Figure 4Unlike at least one example embodiment shown, the back gate electrode located between the first active pattern AP1 and the second active pattern AP2 is omitted (see [reference]). Figure 4 The attached diagram is labeled "BG" and the back gate insulation pattern is shown in the figure. Figure 4 (See attached figure “111”), first shielding insulation pattern (see attached figure) Figure 4 (See attached figure "113"), first shielding pattern (see attached figure "113") Figure 4 The attached diagram shows the reference numeral "SP1" and the pattern of the first shielding cover (see attached diagram). Figure 4 The figure is labeled “115”, and a first word line WL1 and a second word line WL2 are also included between the first active pattern AP1 and the second active pattern AP2.

[0335] refer to Figure 11 The first character line WL1 and the second character line WL2 can be located between the active patterns AP1 and AP2, respectively.

[0336] Specifically, the first character line WL1 can be positioned on one side of the first active pattern AP1 in the second direction Y, and the second character line WL2 can be positioned on the other side of the first active pattern AP1 in the second direction Y.

[0337] Furthermore, the first character line WL1 can be positioned on one side of the second active pattern AP2 in the second direction Y, and the second character line WL2 can be positioned on the other side of the second active pattern AP2 in the second direction Y.

[0338] Therefore, word lines WL1 and WL2 can be located on either side of each of the first active pattern AP1 and the second active pattern AP2.

[0339] In at least one example embodiment, multiple shielding patterns SP may be located on multiple word lines WL1 and WL2, respectively.

[0340] Multiple shielding patterns SP may each have substantially the same thickness in the third direction Z and / or substantially the same width in the second direction Y. However, this disclosure is not limited thereto, and references are made to... Figures 5 to 9 The above description of the shielding pattern SP can also be applied to the arrangement, width, and thickness relationships of multiple shielding patterns SP, so they will not be described in detail.

[0341] exist Figure 11 The diagram shows two side surfaces of each of the first active pattern AP1 and the second active pattern AP2 overlapping with word lines WL1 and WL2. However, the arrangement of the first active pattern AP1, the second active pattern AP2, and the word lines WL1 and WL2 is not limited to this and can be varied.

[0342] With Figure 11 Unlike the example shown, in some example embodiments, word lines WL1 and WL2 may surround the two side surfaces of the first active pattern AP1 and the second active pattern AP2, respectively. For example, word lines WL1 and WL2 may be integrally formed and have a gate-all-around (GAA) structure surrounding the four side surfaces of each of the first active pattern AP1 and the second active pattern AP2.

[0343] When word lines WL1 and WL2 are integrally formed and have the structure described above surrounding all side surfaces of each of the first active pattern AP1 and the second active pattern AP2, the shielding pattern SP, the shielding insulation pattern 142, and the shielding cover pattern 144 located on the first word line WL1 and the second word line WL2 can be integrally formed and have the structure surrounding all side surfaces of each of the first active pattern AP1 and the second active pattern AP2.

[0344] according to Figure 10 and Figure 11 The semiconductor device of at least one example embodiment shown may have the same or substantially similar effects as the semiconductor device according to the above embodiments.

[0345] Figure 12 This is a cross-sectional view showing a semiconductor device according to some example embodiments. Figure 13 yes Figure 12 A magnified view of region R1.

[0346] Specifically, Figure 12 This is a cross-sectional view showing a substrate 300 of a semiconductor device according to some example embodiments and a unit structure CS located on the substrate 300. According to Figure 12 The semiconductor device in at least one example embodiment shown may be a vertically stacked DRAM (VS DRAM).

[0347] The semiconductor device according to at least one example embodiment may include a plurality of memory cells arranged in three dimensions. The plurality of memory cells may also include a memory transistor MT and a cell capacitor DSP. Each of the plurality of memory cells may be connected to a bit line BL and a word line WL. In this at least one example embodiment, the two word lines WL may share a back gate electrode BG.

[0348] The semiconductor device according to at least one example embodiment may include a substrate 300 and a cell structure CS located on the substrate 300.

[0349] The cell structure CS may include a substrate 300, a bit line BL extending in a third direction Z perpendicular to the substrate 300, a plurality of active patterns AP connected to the bit line BL and extending in a first direction X parallel to the substrate 300, a pair of word lines WL located on both sides of the plurality of active patterns AP, a back gate electrode BG located between adjacent active patterns AP, a cell capacitor DSP connected to the plurality of active patterns AP, and a plurality of shielding patterns SP located at a horizontal position between the word line WL and the cell capacitor DSP and / or at a horizontal position between the back gate electrode BG and the cell capacitor DSP.

[0350] exist Figure 12 The image shows a semiconductor device according to at least one example embodiment of the present invention comprising three memory cells that are commonly connected to a bit line BL and stacked in a third direction Z perpendicular to the substrate 300; however, the present disclosure is not limited thereto.

[0351] In addition, Figure 12 The diagram illustrates that each stacked structure LS includes one memory cell; however, this disclosure is not limited thereto. For example, each stacked structure LS may further include... Figure 12 The memory cell shown is a mirror-symmetric memory cell. For example, the semiconductor device according to some example embodiments may further include memory cells that are mirror-symmetric with... Figure 12 The stacked structure LS is mirror-symmetric and positioned on the substrate 300. The stacked structure LS and the stacked structure mirror-symmetric to the stacked structure LS can form a pair.

[0352] Specifically, the substrate 300 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Multiple stacked structures LS can be sequentially stacked on the substrate 300. Each stacked structure LS can constitute a memory cell array of a semiconductor device.

[0353] Despite Figure 12 As shown in the figures, the semiconductor device according to at least one example embodiment may also include a peripheral circuit structure (not shown in the figures) that includes peripheral circuitry for operating the memory cell array.

[0354] The peripheral circuit structure may include wiring electrically connected to bit lines BL and word lines WL, and the wiring may be connected to peripheral circuitry. The peripheral circuit structure may be positioned on or below the cell structure CS to overlap it in the third direction Z. For example, the cell structure CS and the peripheral circuit structure may be joined and connected using a hybrid copper bonding method substantially similar to that used in semiconductor devices according to the embodiments described above. However, the joining method between the cell structure CS and the peripheral circuit structure is not limited to this. For example, the cell structure CS and the peripheral circuit structure may be connected in a direct bonding manner via a single via.

[0355] Reference Figure 12 and Figure 13 On one side of the multiple stacked structures LS, a bit line BL can be positioned. The bit line BL can extend in a third direction Z perpendicular to the substrate 300. The bit line BL can have a line shape or a pillar shape extending in the third direction Z.

[0356] Each of the multiple stacked structures LS may include an active pattern AP, a pair of word lines WL located on either side of the active pattern AP in the third direction Z, and a unit capacitor DSP connected to the active pattern AP. The pair of word lines WL may be positioned on either side of the active pattern AP in the third direction Z.

[0357] The active pattern AP can extend in a first direction X that is perpendicular to the extension direction of the bit line BL. In other words, the active pattern AP can extend in a first direction X that is parallel to the substrate 300.

[0358] The active pattern AP may include a first doped region SDR1 connected to the bit line BL, a second doped region SDR2 connected to the unit capacitor DSP, and a channel region CHR located between the first doped region SDR1 and the second doped region SDR2. The first doped region SDR1 and the second doped region SDR2 of each of the active patterns AP1 and AP2 may correspond to the first source / drain electrode and the second source / drain electrode of the storage transistor MT, and the channel region CHR may correspond to the channel of the storage transistor MT.

[0359] refer to Figure 4 The above description of the active patterned AP can also be applied substantially equivalently to the active patterned AP according to at least one example embodiment, and therefore will not be described in detail thereafter.

[0360] The semiconductor device according to at least one example embodiment may further include an interlayer insulating layer 330 located between stacked structures LS adjacent to each other.

[0361] The word line WL, active pattern AP, back gate electrode BG, and unit capacitor DSP included in each stacked structure LS can be located on the interlayer insulating layer 330. The interlayer insulating layer 330 can be positioned between the substrate 300 and the stacked structure LS located at the lowest level.

[0362] The interlayer insulation layer 330 may comprise an insulating material, such as at least one of silicon nitride, silicon oxide, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxide, combinations thereof, and / or the like.

[0363] Multiple word lines WL can extend in a first direction X, which intersects perpendicularly with a third direction Z, which is the extension direction of the bit line BL. The multiple word lines WL can extend in the first direction X, which is parallel to the upper surface of the substrate 300.

[0364] The stacked structure LS may include two word lines WL. The stacked structure LS may include a first word line WL1 and a second word line WL2 spaced apart in the third direction Z. Between the first word line WL1 and the second word line WL2 spaced apart in the third direction Z, two active patterns AP may be positioned.

[0365] Each word line WL can be positioned to correspond to the channel region CHR of an active pattern AP. The first word line WL1 can be located on the third Z-direction side of the channel region CHR of any of the multiple active pattern APs positioned adjacent to each other, and the second word line WL2 can be located on the other Z-direction side of the channel region CHR of another of the multiple active pattern APs positioned adjacent to each other.

[0366] The materials contained in the bit line BL and word line WL according to at least one example embodiment are the same as those included in the bit line BL and word line in the semiconductor device according to the above embodiment (see...). Figure 4 The materials contained in the accompanying reference numerals “WL1” and “WL2” are the same (or substantially similar) and will not be described in detail.

[0367] The semiconductor device according to at least one example embodiment may further include a gate cover pattern 323 located between the bit line BL and the word line WL, and a gate insulating pattern GOX surrounding the side surfaces of the gate cover pattern 323 and the word line WL.

[0368] The gate cover pattern 323 may contain an insulating material and insulate the bit line BL and word line WL from each other. For example, the gate cover pattern 323 may contain silicon oxide, silicon nitride, or a combination thereof.

[0369] The gate insulating pattern GOX can cover the side surfaces of the gate cover pattern 323 and the word line WL to conform to them.

[0370] The material contained in the gate insulating pattern GOX according to at least one example embodiment is the same (or substantially similar) to the material contained in the gate insulating pattern GOX included in the semiconductor device according to the above embodiments, and therefore will not be described in detail.

[0371] The stacked structure LS may include a back gate electrode BG. The back gate electrode BG may be located between a first word line WL1 and a second word line WL2. The back gate electrode BG may be located between active patterns AP that are adjacent to each other in the third direction Z. The back gate electrode BG may be positioned to correspond to the channel region CHR of the active pattern AP.

[0372] On one side of the active pattern AP in the third direction Z, a word line WL can be positioned, and on the other side in the third direction Z, a back gate electrode BG can be positioned. On the two sides of the active pattern AP facing each other in the third direction Z, the word line WL and the back gate electrode BG can be positioned respectively.

[0373] The material contained in the back gate electrode BG according to at least one example embodiment is the same as (or substantially similar to) the material contained in the back gate electrode BG included in the semiconductor device according to the above embodiments, and will not be described in detail.

[0374] Furthermore, in at least one example embodiment, the arrangement relationship between the word line WL and the back gate electrode BG and / or the width relationship between the word line WL and the back gate electrode BG in the third direction Z can be applied substantially equivalently to the word line arrangement according to the above embodiment (see [link to example embodiment]). Figure 4 The figure references “WL1” and “WL2”) and the back gate electrode BG (see Figure 1) Figure 4 The arrangement of the reference numerals "BG" in the attached diagram and the lettering (see...) Figure 4 The reference numerals “WL1” and “WL2” in the attached figures) and the back gate electrode (see Figure 1). Figure 4 The content regarding the width relationship between the reference numerals "BG" in the attached figures is not described in detail here.

[0375] The semiconductor device according to at least one example embodiment may further include a back gate cover pattern 313 located between the bit line BL and the back gate electrode BG, and a back gate insulating pattern 311 surrounding the side surfaces of the back gate cover pattern 313 and the back gate electrode BG.

[0376] The back gate cover pattern 313 may include an insulating material and insulate the bit line BL and the back gate electrode BG from each other. The back gate insulating pattern 311 may cover the side surfaces of the back gate cover pattern 313 and the back gate electrode BG to conform to them.

[0377] The back gate insulating pattern 311 and the back gate cover pattern 313 may comprise silicon oxide, silicon nitride, or a combination thereof. However, this disclosure is not limited thereto.

[0378] Multiple shielding patterns SP can be positioned between the word line WL and the unit capacitor DSP, and between the back gate electrode BG and the unit capacitor DSP.

[0379] In at least one example embodiment, the shielding pattern SP may overlap with the second doped region SDR2 of at least one of the plurality of active patterns APs in a third direction Z, which is a vertical direction. For example, the shielding pattern SP may be positioned to overlap with the second doped region SDR2 of each of the plurality of active patterns APs in a third direction Z, which is a vertical direction. The shielding pattern SP may be positioned to overlap with a portion of the active pattern AP in a third direction Z, which is the extension direction of the bit line BL. In other words, the shielding pattern SP may be positioned to overlap with the second doped region SDR2 of each of the plurality of active patterns APs in a third direction Z, which intersects perpendicularly with the first direction X of the word line WL.

[0380] In at least one example embodiment, multiple shielding patterns SP may be located on at least one of the back gate electrode BG and multiple word lines WL. For example, as Figure 12 As shown, multiple shielding patterns SP can be located on each of the back gate electrode BG and multiple word lines WL.

[0381] Multiple shielding patterns SP may include a first shielding pattern SP1 located on the back gate electrode BG and a second shielding pattern SP2 located on the word line WL.

[0382] The first shielding pattern SP1 can be positioned between the back gate electrode BG and the unit capacitor DSP, and the second shielding pattern SP2 can be positioned between the word line WL and the unit capacitor DSP.

[0383] exist Figure 12 The diagram shows multiple shielding patterns SP located between the back gate electrode BG and the cell capacitor DSP, and between the word line WL and the cell capacitor DSP, respectively. However, the arrangement of the multiple patterns SP is not limited to this and can be varied. Although not shown in the figures, for example, the multiple patterns SP can be arranged according to... Figure 5 and Figure 6 The pattern SP shown in at least one example embodiment is arranged in a substantially similar manner.

[0384] The back gate insulating pattern 311 can be located between the first shielding pattern SP1 and the back gate electrode BG, and the gate insulating pattern GOX can be located between the second shielding pattern SP2 and the word line WL.

[0385] Each first shielding pattern SP1 can be positioned to overlap with the back gate electrode BG in the first direction X, and the second shielding pattern SP2 can be positioned to overlap with the word line WL in the first direction X. In other words, the first shielding pattern SP1 and the back gate electrode BG can be positioned parallel to each other along the first direction X, and the second shielding pattern SP2 and the word line WL can be positioned parallel to each other along the first direction X.

[0386] Each first shielding pattern SP1 may extend in a first direction X between the back gate electrode BG and the cell capacitor DSP, and the second shielding pattern SP2 may extend in the first direction X between the word line WL and the cell capacitor DSP.

[0387] Multiple shielding patterns SP can be positioned between adjacent active patterns AP in the third direction Z. The length of each shielding pattern SP in the first direction X can be less than the lengths of active patterns AP1 and AP2 in the first direction X.

[0388] The length of the shielding pattern SP in the first direction X can be less than the length of the second dopant region SDR2 in the first direction X. Therefore, the shielding pattern SP can overlap with a portion of the second dopant region SDR2 in the third direction Z.

[0389] In addition, the references can be applied essentially equally to the materials, arrangement relationships, width relationships, thickness relationships, impurity concentrations, and work functions of multiple shielding patterns SP. Figures 1 to 11 The above-described content will therefore not be described in detail.

[0390] The semiconductor device according to at least one example embodiment may further include a first shielding insulating pattern 315 located between the back gate electrode BG and the first shielding pattern SP1, a first shielding cover pattern 317 located between the first shielding pattern SP1 and the unit capacitor DSP, a second shielding insulating pattern 325 located between the word line WL and the second shielding pattern SP2, and a second shielding cover pattern 327 located between the second shielding pattern SP2 and the unit capacitor DSP.

[0391] The first shielding insulating pattern 315 may be positioned between the first shielding pattern SP1 and the second dopant region SDR2 of the active pattern AP, and between the first shielding pattern SP1 and the back gate insulating pattern 311. The first shielding insulating pattern 315 may extend conformally along the surfaces of the first shielding pattern SP1 and the first shielding cover pattern 317.

[0392] The second shielding insulating pattern 325 may be positioned between the second shielding pattern SP2 and the second doped region SDR2 of the active pattern AP, and between the second shielding pattern SP2 and the gate insulating pattern GOX. The second shielding insulating pattern 325 may extend conformally along the surfaces of the second shielding pattern SP2 and the second shielding cover pattern 327.

[0393] The first shielding insulation pattern 315, the first shielding cover pattern 317, the second shielding insulation pattern 325, and the second shielding cover pattern 327 may contain an insulating material. For example, the insulating material may include at least one of silicon oxide, silicon nitride, combinations thereof, and / or the like. However, the insulating material is not limited to this and can be modified in various ways.

[0394] The unit capacitor DSP may include a first electrode 351, a second electrode 355, and a dielectric layer 353 inserted between the first electrode 351 and the second electrode 355.

[0395] Regarding the first electrode included in the unit capacitor DSP according to the above embodiment (see...) Figure 3 (See attached figure "251"), second electrode (see attached figure "251") Figure 4 The figure reference numeral "252" and the dielectric layer (see Figure 252) Figure 3 The reference numeral "253" in the accompanying drawings can also be applied substantially equivalently to the first electrode 351, the second electrode 355, and the dielectric layer 353 included in the unit capacitor DSP according to at least one exemplary embodiment of the present invention, and therefore will not be described in detail.

[0396] In at least one example embodiment, the storage contact BC may be located between the second doped region SDR2 of the active pattern AP and the unit capacitor DSP. The storage contact BC may contact the unit capacitor DSP. For example, the storage contact BC may be connected to the first electrode 351 of the unit capacitor DSP.

[0397] In at least one example embodiment, the storage contact BC overlaps with the shielding pattern SP in the third-direction Z, and may not overlap with the shielding cover patterns 317 and 327. However, this disclosure is not limited thereto, and is related to, for example... Figure 12 Unlike the example shown, in some example embodiments, the storage contact BC may overlap with at least a portion of the shielding pattern SP on the third-direction Z.

[0398] and Figure 12 Unlike the example shown, in some exemplary embodiments, the storage contact BC can be omitted. When the storage contact BC is omitted, the second doped region SDR2 of the active pattern AP can be directly connected to the first electrode 351 of the unit capacitor DSP.

[0399] In addition, the storage contact BC according to at least one example embodiment can be connected with according to Figure 4 The storage contact BC shown in at least one example embodiment is the same (or substantially similar), and therefore will not be described in detail. In other words, the description of the impurity type and concentration included in the storage contact BC according to this at least one example embodiment, as well as the description of the work function of the storage contact BC, can be found in the above reference. Figure 4 The descriptions of the storage contacts BC are the same (or substantially similar).

[0400] The semiconductor device according to at least one example embodiment may further include a first capacitor isolation pattern 341 and a second capacitor isolation pattern 343 located between the first electrodes 351 of the unit capacitor DSP.

[0401] The first capacitor isolation pattern 341 and the second capacitor isolation pattern 343 may be located between the first electrodes 351 of the unit capacitor DSP and are alternately stacked in the third direction Z.

[0402] A first capacitor isolation pattern 341 may extend from the interlayer insulating layer 330 in the first direction X, and a second capacitor isolation pattern 343 may extend from the first shielding cover pattern 317 in the first direction X. The first electrode 351 of each unit capacitor DSP may be isolated and insulated by the first capacitor isolation pattern 341 and the second capacitor isolation pattern 343.

[0403] The first capacitor isolation pattern 341 and the second capacitor isolation pattern 343 may comprise an insulating material such as silicon oxide. However, this disclosure is not limited thereto.

[0404] like Figure 13 As shown, the first shielding pattern SP1 may have a first thickness T1, and the second shielding pattern SP2 may have a second thickness T2.

[0405] Here, the first thickness T1 and the second thickness T2 can refer to the thickness in the first direction X. In other words, the first thickness T1 and the second thickness T2 can refer to the thickness of the first shielding pattern SP1 and the second shielding pattern SP2 in their extension directions, respectively.

[0406] In at least one example embodiment, the first thickness T1 may be the same as (or substantially similar to) the second thickness T2. Further, the thickness of the first shielding insulating pattern 315 surrounding the first shielding pattern SP1 and the thickness of the second shielding insulating pattern 325 surrounding the second shielding pattern SP2 may be substantially the same. However, this disclosure is not limited thereto, and the relationship between the first thickness T1 and the second thickness T2 and / or the thickness relationship between the first shielding insulating pattern 315 and the second shielding insulating pattern 325 can be varied.

[0407] With Figure 13 Unlike the examples shown, in some exemplary embodiments, the relationship between the first thickness T1 and the second thickness T2 and / or the thickness relationship between the first shielding insulation pattern 315 and the second shielding insulation pattern 325 can be substantially equivalently applied to the relationship based on... Figure 7The relationship between the first thickness T1 and the second thickness T2 in at least one example embodiment shown and / or according to Figure 8 The content of the thickness relationship between the first shielding insulation pattern 113 and the second shielding insulation pattern 143 in at least one example embodiment shown.

[0408] Therefore, the arrangement of the first shielding pattern SP1, the second shielding pattern SP2, the first shielding insulation pattern 315, and the second shielding insulation pattern 325 can be changed in different ways.

[0409] In at least one example embodiment, the first shielding pattern SP1 may have a first width W1, and the second shielding pattern SP2 may have a second width W2. Here, the first width W1 and the second width W2 may refer to the width in the third direction Z.

[0410] Furthermore, each of the first shielding cover pattern 317 and the second shielding cover pattern 327 may have a first width W1 and a second width W2. For example, the first width W1 may be greater than the second width W2. However, this disclosure is not limited to this, and the relationship between the first width W1 and the second width W2 may be varied.

[0411] Furthermore, in at least one example embodiment, the first width W1 may be smaller than the width of the back gate electrode BG in the third direction Z, and the second width W2 may be smaller than the width of the word line WL in the third direction Z. However, the relationship between the first width W1 and the second width W2, the relationship between the first width W1 and the width of the back gate electrode BG, and the relationship between the second width W2 and the width of the word line WL are not limited thereto, and various changes can be made.

[0412] and Figure 13 Unlike at least one example embodiment shown, in some example embodiments, due to the thickness difference between the first shielding insulation pattern 315 and the second shielding insulation pattern 325, such as Figure 8 As shown, the first width W1 and the second width W2 can be substantially the same.

[0413] In addition, with Figure 13 Unlike at least one exemplary embodiment shown, in some exemplary embodiments, the first width W1 may be greater than, or the same as (or substantially similar to) the width of the back gate electrode BG in the third direction Z, and the second width W2 may be greater than, or the same as (or substantially similar to) the width of the word line WL in the third direction Z.

[0414] According to Figure 12 and Figure 13The semiconductor device of at least one example embodiment shown has a shielding pattern SP formed between doped regions of an active pattern AP connected to a unit capacitor DSP, and can have substantially the same effect as the semiconductor device according to the above embodiment.

[0415] Figure 14 and Figure 15 This is a partially enlarged cross-sectional view showing a semiconductor device according to some example embodiments. Specifically, Figure 14 and Figure 15 It is shown that... Figure 12 A magnified view of regions R2 and R3 corresponding to region R1 according to some example embodiments.

[0416] According to Figure 14 The semiconductor device of at least one example embodiment shown, with Figure 13 Unlike at least one example embodiment shown, the back gate electrode (see Figure 13 (See attached figure reference "BG"), back gate insulation pattern (see attached figure reference "BG") Figure 13 (see attached reference numeral "311") and the back gate cover pattern ..."). Figure 13 The reference numeral "313" is omitted, and may further include an isolation insulating pattern 350 located between adjacent active patterns AP.

[0417] Specifically, refer to Figure 14 On one side of any of the multiple active pattern APs in the third direction Z, a first word line WL1 may be positioned, and on the other side of the third direction Z, an isolation insulation pattern 350 may be positioned.

[0418] Furthermore, the isolation insulation pattern 350 may be located on one side of another of the plurality of active pattern APs in the third direction Z, and the second word line WL2 may be located on the other side of another of the plurality of active pattern APs in the third direction Z. In other words, according to at least one example embodiment, the word line WL may be located on only one side or the other side of the active pattern AP.

[0419] In at least one example embodiment, the first shielding pattern SP1 may be located on the isolation insulating pattern 350, and the second shielding pattern SP2 may be located on the word line WL. In other words, the first shielding pattern SP1 may be positioned to overlap with the isolation insulating pattern 350 in the first direction X, and the second shielding pattern SP2 may be positioned to overlap with the word line WL in the first direction X.

[0420] The insulating pattern 350 may include insulating material. For example, the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon nitride oxide, etc., and may be modified in various ways.

[0421] In addition, the shielding pattern SP according to at least one exemplary embodiment can be substantially equivalently applied to the shielding pattern SP according to the present embodiment. Figure 13 The content of the shielding pattern SP shown in at least one exemplary embodiment will not be described in detail.

[0422] According to Figure 15 The semiconductor device of at least one example embodiment shown, with Figure 13 Unlike at least one example embodiment shown, the back gate electrode located between adjacent active patterned APs is omitted (see [reference]). Figure 13 The attached diagram is labeled "BG" and the back gate insulation pattern is shown in the figure. Figure 13 (See attached figure "311"), back gate cover pattern (see attached figure "311") Figure 13 (See attached figure "313"), first shielding insulation pattern (see attached figure "313") Figure 13 (See attached diagram "315"), pattern of the first shielding cover (see attached diagram "315") Figure 13 The attached figure reference numeral "317" and the first shielding pattern (see Figure 317) Figure 13 The figure is labeled “SP1”, and the first word line WL1 and the second word line WL2 are also included between adjacent active patterns AP.

[0423] According to at least one example embodiment, a stacked structure (see...) Figure 12 The reference numeral "LS" in the attached diagram may include four word lines WL.

[0424] Specifically, a first word line WL1 can be positioned on one side of the third direction Z of any of the plurality of active pattern APs included in a stacked structure LS, and a second word line WL2 can be positioned on the other side of the third direction Z of any of the plurality of active pattern APs.

[0425] Furthermore, a first word line WL1 can be positioned on one side of the third direction Z of another active pattern AP among the multiple active pattern APs, and a second word line WL2 can be positioned on the other side of the third direction Z of another active pattern AP among the multiple active pattern APs.

[0426] Therefore, word lines WL can be located on both sides of the third direction Z of each of the multiple active pattern APs. That is, word lines WL can be located on the two sides of the multiple active pattern APs facing each other in the third direction Z. In other words, word lines WL can be located on the two side surfaces of the multiple active pattern APs that face each other in the third direction Z.

[0427] The semiconductor device according to at least one example embodiment may also include a word line isolation pattern 360, which is located between a plurality of word lines WL and insulates and isolates them.

[0428] The word line isolation pattern 360 can be located between adjacent word lines WL in the third direction Z, and isolates and insulates adjacent word lines WL.

[0429] For example, the word line isolation pattern 360 can be located between the first word line WL1 and the second word line WL2, with the first word line WL1 located on one side of the third direction Z of any of the multiple active pattern APs, and the second word line WL2 located on the other side of the third direction Z of any of the multiple active pattern APs.

[0430] The word line isolation pattern 360 may contain an insulating material, such as at least one of silicon nitride, silicon oxide, carbon-containing silicon oxide, carbon-containing silicon nitride, or carbon-containing silicon oxide.

[0431] In at least one example embodiment, a plurality of shielding patterns SP can be positioned such that a plurality of word lines WL are in a first direction X. Figure 15 The diagram shows that the two side surfaces of the side surface of each of the multiple active patterns AP overlap with the word line WL. However, the arrangement relationship between each active pattern AP and the word line WL is not limited to this and can be changed in various ways.

[0432] and Figure 15 Unlike other examples, in some exemplary embodiments, word lines WL can surround all side surfaces of each of the plurality of active pattern APs. For example, word lines WL1 and WL2 can be integrally formed and have a gate-all-around (GAA) structure surrounding all four side surfaces of each of the plurality of active pattern APs.

[0433] When word lines WL1 and WL2 are integrally formed and have the structure described above surrounding all side surfaces of each active pattern AP, the shielding pattern SP, shielding insulation pattern 324, and shielding cover pattern 326 located on the first word line WL1 and the second word line WL2 can be integrally formed and have the structure surrounding all side surfaces of each active pattern AP.

[0434] according to Figure 14 The semiconductor device of at least one example embodiment shown may have the same characteristics as those according to... Figure 10 The semiconductor devices of at least one example embodiment shown have the same or substantially similar effects, and according to Figure 15 The semiconductor device of at least one example embodiment shown may have the same characteristics as those according to... Figure 11The semiconductor devices shown in at least one example embodiment have the same or substantially similar effects.

[0435] The following is for reference Figures 16 to 23 The manufacturing method of the semiconductor device is described below. In the following text, components that are the same as (or substantially similar to) the components described above will be indicated by the same reference numerals, and their redundant descriptions will be omitted or will be briefly given; the differences between them and the components described above will be mainly described.

[0436] Figures 16 to 23 It is a cross-sectional view used to explain a method of manufacturing a semiconductor device according to at least one example embodiment.

[0437] Specifically, Figures 16 to 23 Along each manufacturing process step Figure 1 A cross-sectional view taken along line C-C' is used to explain a method of manufacturing a semiconductor device according to at least one example embodiment.

[0438] First, refer to Figure 16 A buried insulating layer 201 and an active layer 202 can be formed on the sub-substrate 200.

[0439] Specifically, an insulating layer 201 and an active layer 202 can be formed on the sub-substrate 200. The sub-substrate 200, the buried insulating layer 201, and the active layer 202 can be silicon-on-insulator (SOI) substrates.

[0440] The buried insulating layer 201 can be, for example, a buried oxide (BOX) formed by an oxygen injection separation (SIMOX) method or a bonding and layer transfer method. As another example, the buried insulating layer 201 can be an insulating layer formed by chemical vapor deposition.

[0441] The buried insulating layer 201 may contain an insulating material, such as at least one of silicon oxide, silicon nitride, silicon nitride and / or a low dielectric constant material.

[0442] The active layer 202 may be a single-crystal semiconductor layer. The active layer 202 may be at least one of, for example, a single-crystal silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0443] Subsequently, a mask pattern MP can be formed on the active layer 202.

[0444] The mask pattern MP may include a first mask pattern 11 and a second mask pattern 12 stacked in sequence. The second mask pattern 12 may contain a material that is etch-selective to the first mask pattern 11. For example, the first mask pattern 11 may contain silicon oxide and the second mask pattern 12 may contain silicon nitride; however, this disclosure is not limited thereto.

[0445] Subsequently, a component isolation layer (STI) can be formed inside the active layer 202. The component isolation layer STI can be formed inside the active layer 202 in the peripheral circuit region (see [link]). Figure 3 (The attached figure is labeled "PAR").

[0446] The component isolation layer STI can be formed by forming component isolation trenches to expose the buried insulating layer 201 through patterned active layer 202, and then filling the component isolation trenches with insulating material. With the formation of the component isolation layer STI, the cell array region can be defined (see...). Figure 3 (The attached image is labeled "CAR").

[0447] Subsequently, the first back gate insulating pattern 111, the back gate electrode BG, the first shield insulating pattern 113, the first shield pattern SP1, and the first shield cover pattern 115 can be formed sequentially.

[0448] Specifically, after forming the back gate trench BG_T by removing some portions of the active layer 202 and the mask pattern MP, a first back gate insulating pattern 111 can be formed on the bottom and side surfaces of the back gate trench BG_T.

[0449] Subsequently, the back gate electrode BG can be formed by filling the back gate trench BG_T with the conductive material used to form the back gate electrode BG, and then an etch-back operation is performed on a portion of the conductive material. The back gate electrode BG can fill a portion of the back gate trench BG_T.

[0450] Subsequently, a first shielding insulation pattern 113 can be conformally formed along the inner sidewall of the back gate trench BG_T and the upper surface of the back gate electrode BG located in the back gate trench BG_T.

[0451] The first shielding insulation pattern 113 can be formed using at least one of atomic layer deposition (ALD), chemical oxidation, thermal oxidation, ultraviolet oxidation, dual plasma oxidation, physical vapor deposition (PVD), thermal chemical vapor deposition (TCVD), low-pressure chemical vapor deposition (LP-CVD), and plasma-enhanced chemical vapor deposition (PE-CVD). However, this disclosure is not limited thereto, and the method for forming the first shielding insulation pattern 113 can be modified differently.

[0452] Subsequently, after forming the first shielding insulating pattern 113, the remaining space in the back gate trench BG_T is filled with the conductive material used to form the first shielding pattern SP1, and a portion of the conductive material can be etched back to form the first shielding pattern SP1 on the first shielding insulating pattern 113.

[0453] In at least one example embodiment, the conductive material used to form the first shielding pattern SP1 may include, for example, polycrystalline silicon doped with n-type impurities or a metallic material having an n-type work function.

[0454] The metallic material having an n-type work function may include at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), or titanium nitride (TiN). However, this disclosure is not limited thereto, and the conductive material used to form the first shielding pattern SP1 may be varied.

[0455] In some example embodiments, after the material for the first shielding pattern SP1 is formed, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed to dop the impurities into the first shielding pattern (SP1) or to further dop the impurities.

[0456] The thickness of the first shielding pattern SP1 in the third direction Z can be less than the thickness of the back gate electrode BG in the third direction Z. The first shielding pattern SP1 can fill the portion of the back gate trench BG_T left after the formation of the first shielding insulating pattern 113.

[0457] Subsequently, after forming the first shielding insulation pattern 113 and the first shielding pattern SP1, the first shielding cover pattern 115 can be formed by filling the back gate trench BG_T with the insulating material used to form the first shielding cover pattern 115, and then removing a portion of the insulating material by performing an etch-back process or a planarization process, thereby forming the first shielding cover pattern 115 on the first shielding pattern SP1.

[0458] The first shielding cover pattern 115 can fill the remaining portion of the back gate trench BG_T after the first shielding pattern SP1 is formed. Here, after the first shielding pattern SP1 is formed, the remaining space of the back gate trench BG_T can be defined by the first shielding insulating pattern 113.

[0459] The upper surface of the first shielding cover pattern 115 may be at the same (or substantially similar) level as the upper surface of the mask pattern MP and the component isolation layer STI.

[0460] In some example embodiments, the active layer 202 exposed by the back gate trench BG_T can be doped with impurities by performing a vapor phase doping (GPD) process or a plasma doping (PLAD) process before forming the first back gate insulating pattern 111.

[0461] Furthermore, in some example embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed prior to the formation of the first shielding pattern SP1 and / or the first shielding cover pattern 115. In other words, impurities can be doped into the active layer 202 through the back gate trench BG_T in which the back gate electrode BG is formed. However, this disclosure is not limited thereto, and the process sequence and method for doping impurities into the active layer 202 may be varied.

[0462] Here, the impurities can be n-type impurities, such as phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), etc. However, this disclosure is not limited to this, and the types of impurities doped into the active layer 202 can be varied.

[0463] Subsequently, with Figure 17 Refer to together Figure 16 A pair of spacer patterns 121 can be formed on the two side surfaces of the first shielding cover pattern 115 located in the back gate trench BG_T by removing some portions of the mask pattern MP.

[0464] Specifically, the second mask pattern 12 of the mask pattern MP can be removed, thereby exposing the first mask pattern 11. Accordingly, the first shielding cover pattern 115 can have a shape that protrudes from the upper surface of the first mask pattern 11.

[0465] Subsequently, a spacer film (not shown in the figures) can be formed along the upper surface of the first mask pattern 11, the side surface of the first back gate insulating pattern 111, and the upper surface of the first shielding cover pattern 115. The spacer film can then be patterned, thereby forming the spacer pattern 121. The width of the active pattern can be determined depending on the deposition thickness of the spacer film (see [reference]). Figure 18 (See the attached figures labeled "AP1" and "AP2").

[0466] The spacer film may contain an insulating material. The spacer film may contain at least one of, for example, silicon oxide, silicon nitride, silicon nitride, silicon carbide (SiC), and silicon carbonitride (SiCN).

[0467] Subsequently, reference Figure 17 Together Figure 18 A pair of first active patterns AP1 and second active patterns AP2 can be formed by patterning the active layer 202.

[0468] Specifically, the spacer pattern 121 can be used as an etching mask to pattern the active layer 202. The step of patterning the active layer 202 may include, for example, performing an anisotropic etching process on the active layer 202.

[0469] When the active layer 202 is patterned, a pair of first active patterns AP1 and second active patterns AP2 can be formed on both sides of the back gate electrode BG. The first active patterns AP1 and second active patterns AP2 can be formed on the side surface of the first back gate insulating pattern 111.

[0470] In the process steps of forming the first active pattern AP1 and the second active pattern AP2, the buried insulating layer 201 can be exposed as the active layer 202 is removed. Although Figure 18 Not shown, but in some example embodiments, some portions of the patterned active layer 202 may remain on the side surface of the element isolation layer STI.

[0471] The first active pattern AP1 and the second active pattern AP2, which are adjacent to each other, can define the word line groove WL_T. In other words, the word line groove WL_T can be formed between the first active pattern AP1 and the second active pattern AP2, which are adjacent to each other.

[0472] The bottom surface of the word line trench WL_T may be defined by the buried insulating layer 201, and the two sidewalls of the word line trench WL_T may be defined by the first active pattern AP1 and the second active pattern AP2.

[0473] Subsequently, reference Figure 18 Together Figure 19 The gate insulating pattern (GOX) and the initial word line (PWL) for forming the word lines can be formed sequentially (see [link to documentation]). Figure 22 (See the attached figures labeled "WL1" and "WL2").

[0474] The gate insulating pattern GOX can be formed along the bottom surface and sidewalls of the word line trench WL_T to conform to them. The gate insulating pattern GOX can be formed along the side surfaces of the first active pattern AP1 and the second active pattern AP2, the top surface of the first back gate insulating pattern 111, the top surface of the first shielding cover pattern 115, the top surface of each spacer pattern 121, and the top surface of the buried insulating layer 201 to conform to them.

[0475] The gate insulation pattern GOX can be formed using any of the methods used to form the first shielding insulation pattern 113 described above. However, this disclosure is not limited thereto.

[0476] The initial word line (PWL) can be formed conformally along the surface of the gate insulation pattern (GOX). The initial word line (PWL) can also be formed conformally along the bottom surface and sidewalls of the word line trench (WL_T).

[0477] The initial word line (PWL) may contain a conductive material. For example, the initial word line may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and / or metal.

[0478] Subsequently, a gate isolation pattern 141 can be formed on the initial word line PWL, and then some portions of the initial word line PWL can be removed.

[0479] Specifically, the gate isolation pattern 141 can be formed such that it completely covers the initial word line PWL and fills the word line trench WL_T.

[0480] Subsequently, a portion of the gate isolation pattern 141 covering the initial word line PWL can be removed, thereby exposing a portion of the initial word line PWL. During the process step of removing a portion of the gate isolation pattern 141, a portion of the gate insulation pattern GOX can be exposed.

[0481] Subsequently, an etching process can be performed on the exposed initial word lines (PWL).

[0482] For example, the etching process on the initial word line (PWL) can be a dry etch-back process.

[0483] An etching process can be performed on the initial word line (PWL) until the upper surface of the initial word line (PWL) is at the same (or substantially similar) level as the upper surface of the back gate electrode (BG) or at a higher level than the upper surface of the back gate electrode (BG). However, the invention is not limited thereto, and the level of the upper surface of the initial word line (PWL) can be varied during the etching process steps on the initial word line (PWL).

[0484] With a portion of the initial word line PWL removed, the remaining initial word line PWL can have a generally U-shaped cross-section inside the word line trench WL_T. In other words, the remaining initial word line PWL can be positioned along the bottom surface and sidewalls of the word line trench WL_T, and covers a portion of the bottom surface of the gate isolation pattern 141 and some of its adjacent side surfaces.

[0485] As the initial word line PWL is etched, the upper surface of the initial word line PWL can be positioned at a lower level than the upper surface of the gate isolation pattern 141.

[0486] Subsequently, a second shielding insulation pattern 143 and a second shielding pattern SP2 can be sequentially formed on the initial word line PWL.

[0487] Specifically, the second shielding insulation pattern 143 can be formed on the gate isolation pattern GOX, the initial word line PWL, and the gate isolation pattern 141 located in the word line trench WL_T.

[0488] The second shielding insulation pattern 143 may be conformally formed along the gate insulation pattern GOX, the upper surface of the initial word line PWL located in the word line trench WL_T, the upper and side surfaces of the gate isolation pattern 141 located in the word line trench WL_T, and the upper surface of the element isolation layer STI.

[0489] The second shielding insulation pattern 143 can be formed using any of the methods used to form the first shielding insulation pattern 113 described above. For example, the second shielding insulation pattern 143 can be formed using atomic layer deposition (ALD). However, this disclosure is not limited thereto, and the method for forming the second shielding insulation pattern 143 can be varied.

[0490] Subsequently, a second shielding pattern SP2 can be formed on the second shielding insulation pattern 143.

[0491] Specifically, after forming the gate isolation pattern GOX, the initial word line PWL, the gate isolation pattern 141, and the second shielding insulation pattern 143, the conductive material used to form the second shielding pattern SP2 can be filled into the remaining space in the word line trench WL_T, and a portion of the conductive material can be etched back to form the second shielding pattern SP2 on the second shielding insulation pattern 143.

[0492] The conductive material used to form the second shielding pattern SP2 can be formed to fill the space between the gate isolation pattern GOX and the gate isolation pattern 141 located in the word line trench WL_T.

[0493] In the process of etching back a portion of the conductive material used to form the second shielding pattern SP2, the remaining conductive material is positioned on the upper surface of the initial word line PWL located in the word line trench WL_T and can form the second shielding pattern SP2.

[0494] In at least one example embodiment, the conductive material used to form the second shielding pattern SP2 may be the same as the conductive material used to form the first shielding pattern SP1 described above. However, this disclosure is not limited thereto, and the conductive material used to form the first shielding pattern SP1 and the conductive material used to form the second shielding pattern SP2 may be different.

[0495] In some example embodiments, after forming and etching back the material to form the second shielding pattern SP2, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed to dope or additionally dope the second shielding pattern SP2 with impurities.

[0496] An etch-back process can be performed on the conductive material used to form the second shielding pattern SP2 until the upper surface of the conductive material used to form the second shielding pattern SP2 is positioned at substantially the same level as the upper surface of the first shielding pattern SP1. However, this disclosure is not limited thereto, and the arrangement relationship between the upper surfaces of the first shielding pattern SP1 and the second shielding pattern SP2 can be varied during the step of performing the etch-back process on the conductive material used to form the second shielding pattern SP2.

[0497] Accordingly, the first shielding pattern SP1 and the second shielding pattern SP2 can be formed such that their thicknesses in the third direction Z are approximately the same.

[0498] In some example embodiments, any one of the process steps for forming the first shielding insulation pattern 113 and the first shielding pattern SP1, as well as the process steps for forming the second shielding insulation pattern 143 and the second shielding pattern SP2, may be omitted.

[0499] Subsequently, referring to Figure 20 The second shielding cover pattern 145 can be formed on the second shielding pattern SP2.

[0500] Specifically, a second shielding cover pattern 145 can be formed to cover the second shielding pattern SP2 and the gate isolation pattern 141. After forming the initial word line PWL, the gate isolation pattern 141, the second shielding insulation pattern 143, and the second shielding pattern SP2, the second shielding cover pattern 145 can fill the remaining space in the word line trench (see...). Figure 19 (See the attached figure labeled "WL_T").

[0501] Subsequently, after forming the second shielding cover pattern 145, a planarization process step can be performed. In the planarization process step, the first mask pattern 11 and each spacer pattern 121 located on the first active pattern AP1 and the second active pattern AP2 can be removed, so that the upper surfaces of the first active pattern AP1 and the second active pattern AP2 are exposed.

[0502] Furthermore, during the planarization process, a portion of the first back gate insulating pattern 111, a portion of the first shielding cover pattern 115, a portion of the gate insulating pattern GOX, a portion of the first active pattern AP1 and the second active pattern AP2, a portion of the second shielding cover pattern 145, and a portion of the component isolation layer STI can be removed together.

[0503] Therefore, the upper surface of the first back gate insulating pattern 111, the upper surface of the first shielding cover pattern 115, the upper surface of the gate insulating pattern GOX, the upper surface of the first active pattern AP1 and the second active pattern AP2, the upper surface of the second shielding cover pattern 145, and the upper surface of the element isolation layer STI can be substantially planarized.

[0504] Accordingly, the first shielding cover pattern 115 and the second shielding cover pattern 145 can be formed such that the thickness in the third direction Z is substantially the same.

[0505] Subsequently, referring to Figure 21 A contact interlayer insulating layer 271, including contact holes for interpreting the contact holes of the first active pattern AP1 and the second active pattern AP2, can be formed on the upper surface of the first back gate insulating pattern 111, the upper surface of the first shielding cover pattern 115, the upper surface of the gate insulating pattern GOX, the upper surface of the first active pattern AP1 and the second active pattern AP2, the upper surface of the second shielding cover pattern 145, and the upper surface of the element isolation layer STI.

[0506] Subsequently, multiple storage contacts BC can be formed inside the contact holes of the interlayer insulating layer 271. These multiple storage contacts BC can be formed on the first active pattern AP1 and the second active pattern AP2.

[0507] In at least one exemplary embodiment, the storage contact BC can be formed of polysilicon doped with impurities. For example, the storage contact BC can be formed of polysilicon doped with n-type impurities. However, this disclosure is not limited thereto, and various modifications can be made to the conductive material used to form the storage contact BC.

[0508] In some example embodiments, the process steps for forming the storage contact BC may include performing a heat treatment process.

[0509] As a result of the heat treatment process, some of the impurities included in the storage contact BC may migrate to the active patterns AP1 and AP2 that are in contact with the storage contact BC via thermal diffusion.

[0510] Therefore, the impurity concentration in the active patterns AP1 and AP2 can gradually decrease as they move away from the interface that contacts the storage contact BC.

[0511] Subsequently, a pad isolation insulating layer 273, including pad holes, can be formed on the contact interlayer insulating layer 271. Then, a plurality of landing pads LP can be formed inside the pad holes of the pad isolation insulating layer 273. The plurality of landing pads LP can be formed on a plurality of storage contacts BC.

[0512] Subsequently, a contact etch stop layer 275 can be formed on the pad isolation insulating layer 273. Then, a first electrode 251, a dielectric film 253 covering the first electrode 251 and connected to multiple landing pads LP, can be sequentially formed through the contact etch stop layer 275 and connected to multiple landing pads LP. The first electrode 251, the dielectric film 253 and the second electrode 255 can constitute a unit capacitor DSP.

[0513] Subsequently, a third unit insulating layer 277 can be formed to completely cover the unit capacitor DSP.

[0514] Subsequently, with Figure 22 Let's refer to each other. Figure 21 The back surface polishing step of removing the sub-substrate 200 can be performed. Removing the sub-substrate 200 may include sequentially performing polishing and etching processes to expose the buried insulating layer 201.

[0515] Subsequently, the buried insulating layer 201 can be removed. With the buried insulating layer 201 removed, the first active pattern AP1 and the second active pattern AP2, the gate insulating pattern GOX, and the first back gate insulating pattern 111 can be exposed.

[0516] Subsequently, the exposed gate insulating pattern GOX and the first back gate insulating pattern 111 can be removed. Therefore, the back gate electrode BG and the initial word line PWL can be exposed.

[0517] Subsequently, a portion of the back gate electrode BG can be removed by performing an etch-back process, and then a second back gate insulating pattern 117 can be formed on the back gate electrode BG.

[0518] Furthermore, by performing an etch-back process or a patterning process to remove a portion of the initial word line PWL, a pair of first word lines WL1 and second word lines WL2 can be formed on both sides of the gate isolation pattern 141. Then, a gate cover pattern 147 can be formed to cover the first word lines WL1 and second word lines WL2 as well as the gate isolation pattern 141.

[0519] The process steps for forming the second back gate insulating pattern 117 and the gate cover pattern 147 may include a planarization process. Therefore, the first active pattern AP1 and the second active pattern AP2, the first back gate insulating pattern 111, the second back gate insulating pattern 117, the gate insulating pattern GOX, and the gate cover pattern 147 can be substantially planarized.

[0520] Subsequently, a polysilicon layer 161, a first metal layer 163, a second metal layer 165, and a bit line capping layer 167 can be sequentially formed on the active patterns AP1 and AP2. The polysilicon layer 161, the first metal layer 163, the second metal layer 165, and the bit line capping layer 167 can constitute a bit line BL.

[0521] Subsequently, a second unit insulating layer 173 can be formed on the component isolation layer STI. Then, on the bit line BL and the second unit insulating layer 173, a spacer insulating layer 175, a first unit insulating layer 177, a bit line shielding pattern BS, and a bit line shielding cap layer 179 can be formed sequentially. However, the order in which the bit line BL, the second unit insulating layer 173, the spacer insulating layer 175, the first unit insulating layer 177, the bit line shielding pattern BS, and the bit line shielding cap layer 179 are formed is not limited to this and can be varied.

[0522] Subsequently, after forming a second bonding insulation layer 216 on the first unit insulation layer 177 and the bit line shielding cap layer 179, unit connection wiring 232, unit connection wiring contact 231 and second bonding pad 222 can be formed in the second bonding insulation layer 216.

[0523] exist Figure 22 The diagram shows that the second bonding insulating layer 216 is a single layer; however, the second bonding insulating layer 216 may have a structure in which multiple layers are stacked, and the multiple layers may be formed by separate processes.

[0524] Subsequently, reference Figure 3 and Figure 23 A peripheral circuit structure PS can be formed on the substrate 100. The peripheral circuit structure PS includes peripheral circuit PC, peripheral circuit contacts PCT1, PCT2 and PCT3, peripheral circuit wiring PCL1 and PCL2, peripheral circuit insulating layer 212, first bonding insulating layer 214 and first bonding pad 221.

[0525] Subsequently, the first bonding pad 221 and the second bonding pad 222 can be joined such that the peripheral circuit structure PS formed on the substrate 100 faces each other, and the first bonding insulating layer 214 and the second bonding insulating layer 216 can be joined together. Therefore, the first bonding pad 221 and the second bonding pad 222 can contact each other to form a metal bonding, and the first bonding insulating layer 214 and the second bonding insulating layer 216 can contact each other to form a junction insulating layer.

[0526] Subsequently, within the third unit insulating layer 277, the first unit wiring contact 261 and the first unit wiring 262 can be formed. Subsequently, on the third unit insulating layer 277, the fourth unit insulating layer 279, the second unit wiring contact 263, and the second unit wiring 264 can be formed.

[0527] While this disclosure has been described in conjunction with some examples which are now considered practical embodiments, it should be understood that the invention and / or inventive concept are not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0528] Cross-references to related applications

[0529] This application claims priority and benefit to Korean Patent Application No. 10-2024-0193162, filed with the Korean Intellectual Property Office on December 20, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Substrate; A bit line on the substrate, the bit line extending in a first horizontal direction; The bit line has a plurality of word lines, each of which extends in a second horizontal direction intersecting the first horizontal direction; The first active pattern and the second active pattern are positioned between the plurality of word lines such that the first active pattern and the second active pattern are spaced apart in the first horizontal direction. One or more unit capacitors, said one or more unit capacitors comprising at least one unit capacitor on at least one of the first active pattern and the second active pattern; and Multiple shielding patterns are positioned at a level between the level of the multiple word lines and the level of the one or more unit capacitors. Each of the first active pattern and the second active pattern includes: The first dopant region is connected to the bit line. The second doped region is connected to the one or more unit capacitors, and The channel region is located between the first dopant region and the second dopant region. The plurality of shielding patterns includes at least one of a shielding pattern that overlaps with the second dopant region of the first active pattern in the first horizontal direction and a shielding pattern that overlaps with the second dopant region of the second active pattern in the first horizontal direction. The plurality of shielding patterns include at least one of a metallic material having an n-type work function and polycrystalline silicon doped with impurities.

2. The semiconductor device according to claim 1, wherein the work function of the plurality of shielding patterns is less than or equal to the work function of the second dopant region.

3. The semiconductor device according to claim 2, further comprising: One or more storage contacts, said one or more storage contacts including at least one of a storage contact between the first active pattern and the one or more unit capacitors and a storage contact between the second active pattern and the one or more unit capacitors. The work function of the plurality of shielding patterns is greater than or equal to the work function of one or more of the storage contacts.

4. The semiconductor device according to claim 1, wherein, The plurality of shielding patterns are located on the plurality of letter lines.

5. The semiconductor device according to claim 1, further comprising: A back gate electrode is located between the first active pattern and the second active pattern, and the back gate electrode extends in the second horizontal direction.

6. The semiconductor device according to claim 5, wherein, The plurality of shielding patterns include: The first shielding pattern on the back gate electrode, and The second shielding pattern on the plurality of word lines.

7. The semiconductor device according to claim 6, wherein, The width of the first shielding pattern is smaller than the width of the back gate electrode, and The width of the second shielding pattern is smaller than the width of each of the plurality of word lines.

8. The semiconductor device according to claim 6, wherein, The width of the first shielding pattern is different from the width of the second shielding pattern.

9. The semiconductor device according to claim 6, further comprising: One or more storage contacts, said one or more storage contacts including at least one of a storage contact between the first active pattern and the one or more unit capacitors and a storage contact between the second active pattern and the one or more unit capacitors. The work function of the plurality of shielding patterns is greater than or equal to the work function of the one or more storage contacts. The first shielding pattern includes a first surface adjacent to the back gate electrode and a second surface adjacent to the one or more storage contacts. The second shielding pattern includes a first surface adjacent to the plurality of word lines and a second surface adjacent to the one or more storage contacts, and The second surface of the first shielding pattern and the second surface of the second shielding pattern are at different levels from each other.

10. The semiconductor device according to claim 6, wherein: The plurality of word lines includes a first word line and a second word line that are adjacent to each other, and The second shielding pattern is on the first character line and the second character line.

11. The semiconductor device according to claim 1, further comprising: An insulating pattern is positioned between the first active pattern and the second active pattern. The plurality of shielding patterns include The first shielding pattern on the insulating pattern, and The second shielding pattern on the plurality of word lines.

12. The semiconductor device according to claim 1, wherein: The impurity is an n-type impurity.

13. The semiconductor device according to claim 1, wherein: The metal-containing material having the n-type work function includes at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), and combinations thereof.

14. A semiconductor device, comprising: Substrate; A bit line on the substrate, the bit line extending in a first horizontal direction; The bit line has multiple word lines that extend in a second horizontal direction that intersects with the first horizontal direction; The first active pattern and the second active pattern are positioned between the plurality of word lines such that the first active pattern and the second active pattern are spaced apart in the first horizontal direction. A back gate electrode is located between the first active pattern and the second active pattern, and the back gate electrode extends in the second horizontal direction. One or more storage contacts, said one or more storage contacts including at least one of storage contacts on the first active pattern and storage contacts on the second active pattern; One or more unit capacitors on one or more storage contacts; and Multiple shielding patterns are applied to at least one of the multiple word lines and the back gate electrode. Each of the first active pattern and the second active pattern includes: The first dopant region connected to the bit line The second dopant region connected to the storage contact, and The channel region is located between the first dopant region and the second dopant region. The plurality of shielding patterns includes at least one of a shielding pattern that overlaps with the second dopant region of the first active pattern in the first horizontal direction and a shielding pattern that overlaps with the second dopant region of the second active pattern in the first horizontal direction. The work function of the plurality of shielding patterns is less than or equal to the work function of the second dopant region.

15. The semiconductor device of claim 14, wherein the work function of the plurality of shielding patterns is greater than or equal to the work function of the one or more storage contacts.

16. The semiconductor device according to claim 14, wherein, Each of the plurality of shielding patterns, the second dopant region of the first active pattern, and the second dopant region of the second active pattern include n-type impurities, and The concentration of the n-type impurity in the plurality of shielding patterns is greater than or equal to the concentration of the n-type impurity in at least one of the second dopant region of the first active pattern and the second dopant region of the second active pattern.

17. The semiconductor device according to claim 14, wherein, Each of the plurality of shielding patterns includes a first surface and a second surface facing each other in a vertical direction, the vertical direction intersecting the first horizontal direction and the second horizontal direction, and The semiconductor device further includes: The shielding cover pattern on the first surface of at least one of the plurality of shielding patterns, and A shielding insulating pattern surrounding the second surface and two side surfaces of at least one of the plurality of shielding patterns and the side surface of the shielding cover pattern.

18. A semiconductor device, comprising: Substrate; Bit lines on the substrate, the substrate extending in a first horizontal direction; The bit line has multiple word lines that extend in a second horizontal direction that intersects with the first horizontal direction; Multiple active patterns are positioned between the multiple character lines, such that the multiple active patterns are spaced apart in the first horizontal direction. A back gate electrode between the plurality of active patterns, the back gate electrode extending in the second horizontal direction; At least one storage contact on the plurality of active patterns; At least one unit capacitor on the at least one storage contact; and Multiple shielding patterns, including a first shielding pattern on the back gate electrode and a second shielding pattern on the multiple word lines. Each of the plurality of active patterns includes: The first dopant region connected to the bit line The second dopant region connected to the storage contact, and The channel region is located between the first dopant region and the second dopant region. Each of the plurality of shielding patterns overlaps in the first horizontal direction with the second dopant region of at least one corresponding active pattern among the plurality of active patterns. The first shielding pattern and the second shielding pattern comprise at least one of a metallic material having an n-type work function and polycrystalline silicon doped with n-type impurities. The work function of each of the first and second shielding patterns is lower than or equal to the work function of the second doped region of the corresponding active pattern, and The work function of each of the first shielding pattern and the second shielding pattern is greater than or equal to the work function of the at least one storage contact.

19. The semiconductor device according to claim 18, wherein: The width of the first shielding pattern is the same as the width of the second shielding pattern.

20. The semiconductor device according to claim 18, wherein, The thickness of the first shielding pattern extending upwards from the third party and the thickness of the second shielding pattern extending upwards from the third party are different from each other, and The third direction intersects with the first horizontal direction and the second horizontal direction.

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