METHOD FOR FORMING A WIDE BANDGAP SEMICONDUCTOR DEVICE

Abstract

Method for forming a wide bandgap semiconductor device (100), the method comprising: forming a mask pattern for a columnar region (116) over the first surface (1041) of the wide bandgap semiconductor body (104), the mask pattern having an opening that exposes part of a transistor cell area (TCA) of the wide bandgap semiconductor body (104); and forming the columnar region (116), comprising introducing dopants of the first conductivity type through the opening on the first surface (1041) into the transistor cell area (TCA) of the wide bandgap semiconductor body (104) by ion implantation;and then forming a trench-gate mask pattern (120) over a first surface (1041) of a wide-bandgap semiconductor body (104), wherein the trench-gate mask pattern (120) has an opening that exposes the trench-gate region of the transistor cell area (TCA) of the wide-bandgap semiconductor body (104); and etching a trench (102) into the wide-bandgap semiconductor body (104) over the opening in the trench-gate mask pattern (120), wherein the trench (102) extends deeper into the semiconductor body than the columnar region (116);Forming a shielding region (106), comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body (104) through a bottom and / or a side wall of the trench (102) by ion implantation, wherein the mask pattern (120) for a trench-gate region serves as an ion implantation mask for forming the shielding region (106) and subsequently expanding the trench (102), comprising an expansion process to form a sacrificial oxide (122) lining the side walls and a bottom of the trench (102) by thermal oxidation and removal of the sacrificial oxide (122).

Description

TECHNICAL AREA The present disclosure relates to a method for forming a semiconductor device, in particular to a method for forming a semiconductor device comprising a wide bandgap semiconductor body. BACKGROUND Technological development of new generations of wide-bandgap semiconductor devices, such as insulated-gate field-effect transistors (IGFETs), like metal-oxide-semiconductor field-effect transistors (MOSFETs), or insulated-gate bipolar transistors (IGBTs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. Reference is made, for example, to the disclosures in US 2023 / 0411446A1 and US 2022 / 0052152A1. Although costs can be reduced by shrinking device geometries, a variety of trade-offs and challenges must be addressed when increasing device functionality per unit area.For example, reducing the area-specific resistivity, RonxA, can be challenging with respect to process-related variations in the arrangement of trenches relative to doped areas or doped areas relative to each other. Such process-related variations can be caused by process technology that incorporates different lithographic levels. For example, the formation of contacts, such as contact plugs or vias, on mesa areas as the width of the mesa shrinks can pose a challenge to reducing the area-specific resistivity, RonxA. There is a need to improve the fabrication processes for wide bandgap semiconductor devices. SUMMARY The invention is defined in claim 1. Further developments are the subject of dependent claims. The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and form part of this specification. The drawings illustrate embodiments for forming wide-bandgap semiconductor devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and the claims. Fig. 1 schematically and by way of example illustrates process features for forming a wide-bandgap semiconductor device. Figs. 2A to 2C are cross-sectional views to illustrate exemplary process features for forming a wide-bandgap semiconductor device. Figs. 3A to 3H are schematic cross-sectional views to illustrate process features for forming a SiC semiconductor device comprising a channel region on a sidewall of a gate trench.Figures 4A to 4G are schematic cross-sectional views illustrating process features for forming a SiC semiconductor device comprising a channel region on opposite first and second side walls of a gate trench. Figures 5A and 5B are schematic cross-sectional views illustrating exemplary process features for forming a columnar region and a connection region. Figures 6A to 6C are schematic cross-sectional views illustrating exemplary process features for forming a current propagation layer. Figures 7A and 7B are schematic cross-sectional views illustrating exemplary process features for forming a connection region. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings, which form part of it and show specific examples for illustration in which semiconductor substrates can be processed. It is understood that other examples may be used and structural or logical modifications may be made without infringing upon the scope of protection of this disclosure. For example, features illustrated or described for one example may be used in or in conjunction with other examples to produce yet another example. It is intended that this disclosure encompasses such modifications and variations. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise indicated. The terms "have," "contain," "comprise," "exhibit," and the like are open-ended, indicating the presence of the specified structures, elements, or features, but not excluding the presence of additional elements or features. The articles "a," "an," and "the" are intended to encompass both the plural and the singular unless the context clearly indicates otherwise. The term "electrically connected" can describe a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" can encompass the fact that one or more intermediate elements, designed for signal and / or power transmission, may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements. Ranges specified for physical dimensions include the limit values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least". The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer. The term "on" should not be interpreted as meaning only "directly on". Rather, if one element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" the substrate). The description and drawings merely illustrate the principles of revelation. Furthermore, all examples presented here are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of revelation and the concepts contributed by inventors to the advancement of the state of the art. All statements herein that reproduce principles, aspects, and examples of revelation, as well as specific examples thereof, are intended to include equivalents thereof. It is understood that the disclosure of multiple steps, processes, operations, or functions in the description or claims should not be interpreted as being in a specific order unless explicitly or implicitly stated otherwise, for example, by expressions such as "thereafter," perhaps for technical reasons. Therefore, the disclosure of multiple steps or functions does not restrict them to a particular order unless these steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single step, function, process, operation, or operation may comprise or be broken down into multiple sub-steps, functions, processes, operations, or operations.Such partial steps may be included and be part of the disclosure of that single step, unless they are explicitly excluded. An example configuration of a method for forming a wide-bandgap semiconductor device may include forming a trench extending from a first surface of the wide-bandgap semiconductor body into the wide-bandgap semiconductor body. The method may further include forming a shielding region, comprising introducing dopants of a first conductivity type into the wide-bandgap semiconductor body through a bottom and / or a side wall of the trench by ion implantation. The method may then further include expanding the trench, comprising an expansion process to form a sacrificial oxide lining the side walls and a bottom of the trench by thermal oxidation and removal of the sacrificial oxide. The wide-bandgap semiconductor device can be, for example, part of an integrated circuit, or it can be a discrete semiconductor device or module. The wide-bandgap semiconductor device can be, for example, an insulated-gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated-gate bipolar transistor (IGBT), or it can include one. The wide-bandgap semiconductor device can be a vertical semiconductor device exhibiting a load current flow between the first surface and a second surface opposite the first surface. The vertical power semiconductor device can be configured to conduct currents greater than 1 A, 10 A, 30 A, 50 A, 75 A, or even 100 A, and can further be configured to carry voltages between load electrodes, e.g.,The blocking voltage is to be applied between the collector and emitter of an IGBT or between the drain and source of a MOSFET, in the range of several hundred to several thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device. The wide-bandgap semiconductor device can be based on a wide-bandgap semiconductor body made of a crystalline wide-bandgap semiconductor material with a bandgap larger than that of silicon, i.e., greater than 1.12 eV. The wide-bandgap semiconductor material can have a hexagonal crystal lattice and can be, for example, silicon carbide (SiC). For example, the semiconductor material can be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. In one example, the semiconductor material is silicon carbide of the 4H polytype (4H-SiC). The semiconductor body can include or consist of a semiconductor substrate that has no, one, or more than one semiconductor layer on it, e.g., epitaxially grown layers. One of the semiconductor layers can, for example, be a doped semiconductor layer of a current-propagation layer. The first surface can be a front surface or a top surface of the wide-bandgap semiconductor body, and the wide-bandgap semiconductor body can further have a second surface, which can be, for example, a rear surface or a back surface of the wide-bandgap semiconductor body. The wide-bandgap semiconductor body can, for example, be mounted on a conductor frame via the second surface. Bond pads can, for example, be arranged over the first surface of the wide-bandgap semiconductor body, and bond wires can be bonded to the bond pads. For example, the trench can be strip-shaped and can define the dimensions of a trench gate structure formed in the trench. To achieve a desired current-carrying capacity, the wide-bandgap semiconductor device can be configured with a large number of parallel-connected wide-bandgap semiconductor cells. These parallel-connected wide-bandgap semiconductor cells can, for example, be arranged in the form of a strip or a strip segment. Of course, the wide-bandgap semiconductor cells can also have any other shape, such as circular, elliptical, polygonal (e.g., hexagonal), or octahedral. The wide-bandgap semiconductor cells can be arranged within the transistor cell region of the wide-bandgap semiconductor body.The transistor cell region can be an area in which an emitter region of an IGBT (or a source region of a MOSFET) and a collector region of an IGBT (or a drain region of a MOSFET) are arranged opposite each other along the vertical direction. In the transistor cell region, a load current can enter or exit the wide-bandgap semiconductor body of the semiconductor device, for example, via contact plugs on the first surface of the wide-bandgap semiconductor body. The wide-bandgap semiconductor device can further include an edge termination region, which may include a termination structure. In a blocking mode or a reverse-biased mode of the wide-bandgap semiconductor device, the blocking voltage between the transistor cell region and a field-free region drops laterally across the termination structure.The termination structure can have a higher or slightly lower voltage blocking capability than the transistor cell area. The termination structure can, for example, include a junction termination extension (JTE) with or without variation of lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof. The first mask pattern can be formed as a first hard mask pattern, e.g., an oxide hard mask pattern. The first mask pattern can be defined, for example, by a photolithography process. The dimensions and arrangement of opening(s) in the first mask pattern can, for example, define a trench layout to form the trench-gate structure of the semiconductor device. The trench(s) can be formed, for example, by an etching process. Prior to forming the first mask pattern, the process can further include the introduction of dopants into the wide-bandgap semiconductor body, e.g., by ion implantation, to define semiconductor layers within the wide-bandgap semiconductor body, e.g., a current-propagation layer and / or a body layer and / or a source layer. The ion implantation of dopants for the shielding region can be based on non-tilted and / or inclined ion implantation. By varying the inclination angle, dopants can, for example, also be implanted through a lower part of the trench's sidewall into the wide-bandgap semiconductor body. Before performing the ion implantation process(s) through the bottom and / or sidewall of the trench, a shielding dielectric, such as a shielding oxide with a thickness of, for example, 20 nm to 200 nm, can be formed on the bottom and / or sidewalls of the trench. This can reduce or prevent channeling effects and absorb ions scattered at the trench's sidewalls. The shielding dielectric can also be formed from materials other than oxides, such as polycrystalline silicon, silicon nitride, or aluminum oxide. The expansion process is initiated by thermal oxidation through the formation of sacrificial oxide, which lines the sidewalls and bottom of the trench. Lateral and vertical expansion of the trench can be precisely controlled, for example, by oxidation time, temperature, and oxygen partial pressure. Optionally, hydrogen treatment can be performed prior to the formation of the sacrificial oxide. The methods described here can enable the self-alignment of a shielding region relative to a trench-gate structure. Critical alignment parameters of the shielding region, such as lateral distance to the trench-gate sidewall, vertical extent from the base of the trench-gate structure, and the width of the trench-gate structure, can be effectively controlled by ion implantation parameters (e.g., energy) of the ion implantation process for the shielding region and oxidation parameters (e.g., temperature, time, and oxygen partial pressure) of the sacrificial oxide. This can simplify the reduction of the mesa width, including the source / body regions, to decrease the area-specific transmittance. For example, the expansion process can be repeated multiple times. Thus, the formation of the sacrificial oxide through thermal oxidation and removal can be repeated several times. The thickness of the subsequently formed sacrificial oxides can differ from one another or be the same, for example, by controlling the thermal oxidation times for each sacrificial oxide. Repeating the sacrificial oxide formation and removal can counteract thickness limitations of a single sacrificial oxide, which can be caused, for example, by a decreasing oxide growth rate with increasing oxide thickness. For example, the width of the trench can be expanded by 10% to 80% at a first horizontal reference level. In other words, each sidewall of opposite trench walls can be laterally displaced by 5% to 40% of the original trench width compared to the trench width before the expansion process. The first horizontal reference level can be the same vertical distance to the first surface as to the bottom of the trench before the expansion process. For example, the widening of the trench can range from one or more tens of nanometers to one or more hundred nanometers. For example, the formation of the wide-bandgap semiconductor device can further include the formation of a trench-gate dielectric in the trench after the expansion process. One or more surface conditioning cleaning processes can be performed between the expansion process and the trench-gate dielectric, or directly upstream of the trench-gate dielectric. The trench-gate dielectric can be formed by or include an oxidation process, such as a thermal oxidation process and / or an oxide deposition process. Other dielectric materials can be used in addition to or as an alternative to the oxide. For example, high-k materials can be used. For instance, the trench-gate dielectric layer can include a high-k dielectric layer comprising at least one of Al₂O₃, ZrO₂, HfO₂, AlN, aluminosilicate AlSiOx, silicon La- or sidoted HfO₂, TiO₂, Y₂O₃, or Si₃N₄.For example, the trench-gate dielectric can comprise at least a first dielectric sublayer and a second dielectric sublayer. The first dielectric sublayer, adjacent to a channel region, can have a dielectric constant that is less than that of the high-k dielectric sublayer, e.g., equal to or greater than the dielectric constant of SiO₂. For example, the first dielectric layer can comprise at least one of SiO₂, AlN, or Si₃N₄. The trench-gate electrode can comprise one or more conductive materials, e.g., metal, metal alloys (e.g., Cu, Au, AlCu, Ag, or alloys thereof), metal compounds (e.g., TiN), or highly doped semiconductor material (e.g., highly doped polycrystalline silicon). The one or more conductive materials can, for example, form a stack of layers.The trench-gate electrode can be electrically connected to a gate pad via a gate junction structure, such as a gate runner. The gate pad / junction structure and, for example, a first load electrode pad, such as a source pad of a MOSFET or an emitter pad of an IGBT, can form part of a wiring region above the wide-bandgap semiconductor body. The wiring region can consist of one or more than one, such as two, three, four, or even more wiring levels. Each wiring level can be formed by a single or a stack of conductive layers, such as metal layer(s). The wiring levels can be structured, for example, lithographically. A dielectric interlayer structure can be placed between stacked wiring levels.Contact plug(s) and / or contact conductor(s) can be formed in openings of the dielectric interlayer structure to electrically connect parts, e.g., metal conductors or contact areas, of different wiring levels. For example, the method may further include forming a first mask pattern over the first surface of the wide-bandgap semiconductor body prior to trench formation. The first mask pattern may have an opening that exposes a transistor cell region of the wide-bandgap semiconductor body. The method may further include forming a source layer, comprising introducing dopants of a second conductivity type into the transistor cell region of the wide-bandgap semiconductor body through the first surface by ion implantation. The ion implantation may be blanket ion implantation within the transistor cell region. In other words, the source layer may be formed across an entire region of the transistor cell area.The method can further include forming a body layer, comprising introducing dopants of the first conductivity type into the transistor cell region of the wide-bandgap semiconductor body through the first surface by ion implantation. Similar to the source layer, the body layer can be formed by blanket ion implantation in the transistor cell region. The method can further include forming a current propagation layer comprising dopants of the second conductivity type. Similar to the source and body layers, forming the current propagation layer can include introducing dopants of the second conductivity type into the transistor cell region of the wide-bandgap semiconductor body through the first surface by blanket ion implantation in the transistor cell region.In addition to or as an alternative to epitaxial deposition, at least part of the current propagation layer can also be formed by an epitaxial deposition process. This deposition process can be part of a layer deposition on a wide-bandgap semiconductor substrate. The layer deposition can form the topmost region of the wide-bandgap semiconductor body, where the mesa regions bounded by gate trenches are formed. Doping of the current propagation layer with second-type conductivity dopants can be performed, for example, in situ or by blanket ion implantation after the epitaxial deposition process. A bottom surface of the current propagation layer can be located beneath a bottom surface of the trench. In other words, a bottom surface of the current propagation layer can have a greater vertical distance to the first surface than a bottom surface of the trench. For example, a bottom surface of the shielding region can be positioned at a smaller vertical distance to the first surface than a bottom surface of the current propagation layer. This allows a pn junction between the shielding region and the current propagation layer to be defined, at least at the bottom surface of the shielding region. For example, the method may further include forming a second mask pattern over the first surface of the wide-bandgap semiconductor body prior to trench formation. This second mask pattern may have an opening that exposes a portion of the transistor cell region of the wide-bandgap semiconductor body. The method may further include forming a columnar region, comprising introducing first-type conductivity dopants through the opening on the first surface into the transistor cell region of the wide-bandgap semiconductor body by ion implantation. The columnar region may, for example, contribute to electrically connecting the shielding region to an electrode pad over the first surface. For example, a bottom surface of the columnar region may be positioned between a bottom surface of the body region and a bottom surface of the stream propagation layer. In some examples, the bottom surface of the columnar region may also be positioned between a bottom surface of the body region and a bottom surface of the trench, or between a bottom surface of the source layer and a bottom surface of the body layer. For example, the method can further include, after trench formation, the formation of a junction region, comprising the introduction of first-type conductivity dopants into the wide-bandgap semiconductor body through a sidewall of the trench by ion implantation. The bottom of the junction region can be configured by adjusting the ion implantation angle and by considering the thickness of an ion implantation mask. The junction region can provide electrical coupling between the shielding region and the columnar region. For example, dopants of the first conductivity type of the junction region can be introduced into the wide-bandgap semiconductor body through the bottom of the trench by ion implantation. For example, the dopants can be implanted simultaneously through the bottom and side walls by adjusting the ion implantation angle. As an alternative or in addition to implanting the dopants through the side wall and optionally the bottom, another ion implantation process, e.g., at a flat angle or with a smaller angle, can be performed to introduce the dopants through the bottom of the trench. For example, the method can further include forming a third mask pattern over the first surface of the wide-bandgap semiconductor body. The third mask pattern can have an opening that exposes a trench-gate region of the transistor cell region of the wide-bandgap semiconductor body. The method can further include etching the trench into the wide-bandgap semiconductor body through the opening in the third mask pattern. The third mask pattern can serve as an ion implantation mask for forming the shielding region. For example, prior to etching the trench, a connection area can be formed by introducing dopants of the first conductivity type into the wide bandgap semiconductor body through the opening in the third mask pattern by ion implantation, e.g., inclined ion implantation. For example, removing the sacrificial oxide may involve wet etching. This wet etching may be based on, for example, a hydrofluoric acid, HF, or etching solution. For example, the process, after trench formation and before forming the shielding region, may further include the formation of an auxiliary dielectric that lines the sidewalls and bottom of the trench. For example, the auxiliary dielectric may be an oxide and may be formed by thermal oxidation and / or deposition. The auxiliary dielectric may, for example, serve as a shielding dielectric on the bottom and / or sidewall of the trench for the ion implantation process of the shielding region. The auxiliary dielectric may also be formed from materials other than oxides, such as polycrystalline silicon, silicon nitride, or aluminum oxide. For example, the procedure, after forming the shielding area and before widening the trench, may further include the removal of the auxiliary oxide. The auxiliary area can be removed by wet etching. Wet etching can be based, for example, on a hydrofluoric acid, HF, or etching solution. Details regarding the structure, function, or technical benefits of features described above in relation to a wide-bandgap semiconductor device, such as a FET or IGBT, apply equally to the exemplary processes described below. The processing of the wide-bandgap semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more of the examples described above or below. Some of the preceding and following examples are described in connection with a silicon carbide substrate. Alternatively, a wide-bandgap semiconductor substrate, such as a wide-bandgap wafer, can be used, which may, for example, have a wide-bandgap semiconductor material other than silicon carbide. The wide-bandgap semiconductor wafer can have a bandgap larger than that of silicon (1.12 eV). For example, the wide-bandgap semiconductor wafer could be a silicon carbide (SiC) wafer or a gallium arsenide (GaAs) wafer. Functional and structural details described in relation to the preceding examples apply equally to the exemplary embodiments illustrated in the figures and described below. The illustrated examples depict n-channel FETs or IGBTs. However, the examples described here can also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs. The process illustration in Fig. 1 relates to process features for forming a wide-bandgap semiconductor device. An exemplary and more detailed illustration of the process features from Fig. 1 is shown in the cross-sectional views of Figs. 2A to 2C. The first conductivity type can, for example, be an n-type, and the second conductivity type can, for example, be a p-type for an n-channel FET. Alternatively, the first conductivity type can also be a p-type, and the second conductivity type can, for example, be an n-type for a p-channel FET. Referring to the process feature S100 of Fig. 1 and the exemplary cross-sectional view of Fig. 2A, the process feature S100 comprises the formation of a trench (e.g., the trench 102 in Fig. 2A) extending from a first surface (e.g., the first surface 1041 in Fig. 2A) of the wide bandgap semiconductor body into a wide bandgap semiconductor body (e.g., the wide bandgap semiconductor body 104 in Fig. 2A). Referring to process feature S110 of Fig. 1 and the exemplary cross-sectional view of Fig. 2B, process feature S110 comprises forming a shielding region (e.g., the shielding region 106 in Fig. 2B), comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body through a bottom and / or side wall of the trench by ion implantation. Referring to process feature S120 of Fig. 1 and the exemplary cross-sectional view of Fig. 2C, process feature S120 comprises trench expansion, including an expansion process to form a sacrificial oxide lining side walls and bottom of the trench by thermal oxidation and removal of the sacrificial oxide. Referring to Fig. 2C, the width of the trench 102 is extended by 10% to 80% on a first horizontal reference level href1. Before the extension process, the first horizontal reference level href1 has the same vertical distance to the first surface 1041 as to a bottom surface 1021 of the trench 102. The schematic cross-sectional views of Fig. 3A to 3H illustrate process features for forming a configuration example of a wide bandgap semiconductor device 100 comprising a channel region on one of opposite side walls of a trench-gate structure. Referring to Fig. 3A, an n+-doped source layer 110 is formed in a transistor cell region (TCA) of a SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is blanket or unmasked with respect to the TCA. However, masked regions can be formed outside the TCA (not illustrated in Fig. 3A). A p-doped body layer 112 is formed in the TCA of the SiC semiconductor body 1043 by ion implantation of p-type dopants through the first surface 1041. An optional n-doped current-propagation layer 114 is formed in the TCA of the SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is either blanket / flat or unmasked with respect to the transistor cell area TCA.The ion implantation process of the n-doped current propagation layer 114 can also be masked to achieve minimal overlap with the p-type shielding structure (patterned current propagation, as illustrated in Fig. 6A, Fig. 6B). This can be advantageous, for example, to avoid leakage currents in blocking mode. Alternatively, or in addition to implanting n-type dopants to form the n-doped current propagation layer 114, the current propagation layer 114 can be formed by an epitaxial deposition process on a SiC-based substrate if a semiconductor layer stack is defined on the SiC-based substrate. In this case, the formation of the current propagation layer 114 can be partially or completely completed before the source and / or body layers 110, 112 are formed. A p-doped columnar region 116 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by a masked ion implantation process of p-type dopants through the first surface 1041 (ion implantation mask, not shown in Fig. 3A). A bottom surface of the p-doped columnar region 116 is positioned between a bottom surface of the p-doped body region 112 and a bottom surface of the n-doped current propagation layer 114. Referring to Fig. 3B, a mask pattern 120 is formed over the first surface 1041 of the SiC semiconductor body 1043. The mask pattern 120 has an opening that exposes a trench-gate region of the transistor cell region TCA of the SiC semiconductor body 1043. A trench 102 is etched into the SiC semiconductor body 1043 through the opening in the mask pattern 120. Etching the trench 102 structures the source layer 110 into source regions 1101 and further structures the body layer 112 into body regions 1121. On a first side wall of trench 102, a portion each of source area 1101, body area 1121, and stream propagation layer 114 is exposed. On a second side wall of trench 102, opposite the first side wall, a portion each of columnar area 116 and stream propagation layer 114 is exposed. Referring to Fig. 3C, p-type dopants are introduced into the SiC semiconductor body 1043 by ion implantation through at least one of the bottom or side walls of the groove 102, e.g., at an angle of no inclination or a slight inclination (the inclination angles can also differ with respect to opposite side walls), as illustrated in Fig. 3C for the angle of no inclination. This forms a p-doped shielding region 106. The mask pattern 120 can be used as an ion implantation mask for the ion implantation process of the p-type dopants for the shielding region 106. Referring to Fig. 3D, p-type dopants are introduced into the SiC semiconductor body 1043 through a side wall and / or bottom of the groove 102 by ion implantation, e.g., inclined ion implantation, as illustrated in Fig. 3D (the inclination angle can be larger than in Fig. 3C, for example). This forms a p-doped junction region 118. The mask pattern 120 can be used as an ion implantation mask for the p-type dopants in the junction region 118. The junction region 118 electrically connects the shielding region 106 and the columnar region 116. After the formation of the junction region 118, the mask pattern 120 is removed, e.g., by wet etching using, for example, an RF solution. High-temperature annealing (HTA) can then follow. Referring to Fig. 3E, an expansion process of the trench 102 is initiated by thermal oxidation through the formation of a sacrificial oxide 122, which lines the side walls and underside of the trench 102. Lateral and vertical expansion of the trench 102 can be precisely controlled, for example, by oxidation time, temperature, and oxygen partial pressure. Optionally, hydrogen treatment can be performed before or after the formation of the sacrificial oxide 122. Referring to Fig. 3F, the sacrificial oxide 122 is removed from the transistor cell area TCA, e.g., by wet etching using, for example, an RF solution. The trench expansion process 102 illustrated in Fig. 3E and Fig. 3F can be repeated once or several times. The sacrificial oxide can be retained in parts of the SiC semiconductor body 1043 outside the transistor cell area TCA, e.g., in inactive chip regions, by a resist mask that protects the sacrificial oxide 122 from the etching process. Referring to Fig. 3G, a trench-gate structure 124 is formed in the trench 102. The formation of the trench-gate structure 124 comprises the formation of a trench-gate dielectric 1241 in the trench 102, e.g., by thermal oxidation or deposition. The formation of the trench-gate structure 124 further comprises the formation of a trench-gate electrode 1242 on the trench-gate dielectric 1241. The formation of the trench-gate structure 124 may also include post-oxidation annealing in a nitrogen-containing atmosphere, for example. The trench-gate electrode 1242 may comprise one or a stack of conductive materials, e.g., highly doped polycrystalline silicon. Referring to Fig. 3H, an interlayer dielectric 126 is formed over the SiC semiconductor body 1043. A first load electrode 128, e.g., source or emitter electrode, is formed over the interlayer dielectric 126. The interlayer dielectric 126 electrically insulates the trench-gate electrode 1242 from the first load electrode 128. Contact openings in the interlayer dielectric 126 enable electrical contact between the first load electrode 128 and the SiC semiconductor body 1043, e.g., the source and body regions 1101, 1121. A second load electrode 130, e.g., drain or collector electrode, is formed over a second surface 1042 of the SiC semiconductor body 1043. In some examples, not illustrated in Fig. 3H, the interlayer dielectric 126 can be formed in an upper or top part of the trench 102. The schematic cross-sectional views of Fig. 4A to 4G illustrate process features for forming a configuration example of a wide bandgap semiconductor device 100 comprising a channel region on both of opposite side walls of a trench-gate structure. Referring to Fig. 4A, an n+-doped source layer 110 is formed in a transistor cell region TCA of a SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is blanket / sheet or unmasked with respect to the transistor cell region TCA. A p-doped body layer 112 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of p-type dopants through the first surface 1041. An n-doped current propagation layer 114 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is either blanket / flat or unmasked with respect to the transistor cell area TCA.Instead of or in addition to implanting n-type dopants to form the n-doped current-propagation layer 114, the current-propagation layer 114 can be formed by an epitaxial deposition process on a SiC-based substrate once the semiconductor layer stack of the SiC semiconductor body 1043 is defined. In this case, the formation of the current-propagation layer 114 can be partially or completely completed before the source and / or body layers 110, 112 are formed. A mask pattern 120 is formed over the first surface 1041 of the SiC semiconductor body 1043. The mask pattern 120 has an opening that exposes a trench-gate region in the transistor cell region TCA of the SiC semiconductor body 1043. A trench 102 is etched into the SiC semiconductor body 1043 through the opening in the mask pattern 120.The etching of trench 102 structures the source layer 110 into source regions 1101 and further structures the body layer 112 into body regions 1121. On a first side wall of trench 102, a portion of the source region 1101, the body region 1121, and the stream propagation layer 114 is exposed. Similarly, on a second side wall of trench 102 opposite the first side wall, a portion of the source region 1101, the body region 1121, and the stream propagation layer 114 is exposed. Referring to Fig. 4B, p-type dopants are introduced into the SiC semiconductor body 1043 through at least one of the bottom or side walls of the groove 102 by ion implantation, e.g., non-inclined ion implantation, as illustrated in Fig. 4B. Prior to ion implantation, an optional auxiliary or shielding dielectric, e.g., an oxide, can be formed and line the side walls and one of the bottom walls of the groove 102. The auxiliary dielectric can be formed, for example, by thermal oxidation and / or deposition. This creates a p-doped shielding region 106. For the ion implantation process of the p-type dopants for the shielding region 106, the mask pattern 120 can be used as an ion implantation mask. Referring to Fig. 4C, an expansion process of the trench 102 is initiated by thermal oxidation through the formation of a sacrificial oxide 122, which lines the side walls and underside of the trench 102. Lateral and vertical expansion of the trench 102 can be precisely controlled, for example, by oxidation time, temperature, and oxygen partial pressure. Optionally, hydrogen treatment can be performed before or after the formation of the sacrificial oxide 122. Referring to Fig. 4D, the sacrificial oxide 122 is removed from the transistor cell area TCA, e.g., by wet etching using, for example, an RF solution. The trench expansion process 102 illustrated in Fig. 4C and Fig. 4D can be repeated once or several times. The sacrificial oxide 122 can be retained in parts of the SiC semiconductor body 1043 outside the transistor cell area TCA, e.g., in inactive chip regions, by a resist mask that protects the sacrificial oxide 122 from the etching process. Referring to Fig. 4E, a trench-gate structure 124 is formed in the trench 102. The formation of the trench-gate structure 124 comprises the formation of a trench-gate dielectric 1241 in the trench 102, e.g., by thermal oxidation. The formation of the trench-gate structure 124 further comprises the formation of a trench-gate electrode 1242 on the trench-gate dielectric 1241. The trench-gate electrode 1242 can comprise one or a stack of conductive materials, e.g., highly doped polycrystalline silicon. The formation of the trench-gate structure 124 can further comprise post-oxidation annealing in a nitrogen-containing atmosphere, for example. Referring to Fig. 4F, an interlayer dielectric 126 is formed over the SiC semiconductor body 1043. A first load electrode 128, e.g., source or emitter electrode, is formed over the interlayer dielectric 126. The interlayer dielectric 126 electrically insulates the trench-gate electrode 1242 from the first load electrode 128. Contact openings in the interlayer dielectric 126 enable electrical contact between the first load electrode 128 and the SiC semiconductor body 1043, e.g., the source and body regions 1101, 1121. A second load electrode 130, e.g., drain or collector electrode, is formed over a second surface 1042 of the SiC semiconductor body 1043. In some examples, not illustrated in Fig. 4F, the interlayer dielectric 126 can be formed in an upper or top part of the trench 102. For example, the interlayer dielectric can be formed entirely within the trench 102. The schematic cross-sectional view of Fig. 4G illustrates an example of joining the p-doped shielding region 106, which is formed in the process illustrated in Figs. 4A to 4F. For example, a p-doped columnar region 116, similar to the columnar region illustrated in Fig. 3A, is formed in the process stage of forming the source layer 110, the body layer 112, and the current-propagation layer 114. The columnar region 116 is formed by a masked ion implantation process and extends deeper into the SiC semiconductor body 1043 as a bottom surface of the trench 102. The schematic cross-sectional view of Fig. 5A illustrates another exemplary process feature based on Fig. 3A, but differing from the example illustrated in Fig. 3A by a vertical extension of the p-doped columnar region 116. The p-doped columnar region 116 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by a masked ion implantation process of p-type dopants through the first surface 1041 (ion implantation mask, not illustrated in Fig. 5A). A bottom surface of the p-doped columnar region 116 in the example of Fig. 5A is positioned between a bottom surface of the n+-doped source layer 110 and a bottom surface of the p-doped body region 112. Process features similar to Fig. 3B and Fig. 3C may follow. Referring to Fig. 5B (which is based on Fig. 3D), p-type dopants are introduced into the SiC semiconductor body 1043 through a side wall and / or bottom of the groove 102 by ion implantation, e.g., inclined ion implantation, as illustrated in Fig. 5D. This forms a p-doped junction region 118. For the ion implantation process of the p-type dopants for the junction region 118, the mask pattern 120 can be used as an ion implantation mask. The junction region 118 electrically connects the shielding region 106 and the columnar region 116. After the formation of the junction region 118, the mask pattern 120 is removed, e.g., by wet etching using, for example, an RF solution. High-temperature annealing (HTA) can follow. Further process features can follow, e.g., B. as illustrated in Figs. 3E to 3H. The process features illustrated in Figs. 3A, 4A, and 5A are based on an ion implantation process of the n-doped current-propagation layer 114, which is either blanketed or unmasked with respect to the transistor cell region (TCA). The following exemplary process features can be used equally well for forming the current-propagation layer 114. With reference to Fig. 6A, the ion implantation process of n-type dopants for forming the n-doped current-propagation layer 114 can also be masked. For example, a mask pattern 1201 can be used, which is the inverse of the mask pattern 120 illustrated in Figs. 3B, 4B, and 5B. Referring to Fig. 6B, the n-type dopants for forming the n-doped current propagation layer 114 can also be introduced through a side wall of the trench 102 by an inclined ion implantation process.In addition to process features for forming the current propagation layer 114, as illustrated in Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 6B, a sub-region 1141 of the current propagation layer 114 under the shielding region 106 can be formed by an ion implantation process through a bottom of the trench 102. The schematic cross-sectional views of Fig. 7A and Fig. 7B illustrate another configuration example for forming the interconnection region 118. The schematic cross-sectional view of Fig. 7A is based on Fig. 5A and illustrates the mask pattern 120 for forming the trench. Referring to the schematic cross-sectional view of Fig. 7B, an interconnection region 118 is formed by introducing dopants of the first conductivity type into the wide-bandgap semiconductor body 104 through the opening in the third mask pattern 120 by inclined ion implantation. The formation of the trench 102 can then follow by etching. The configuration example illustrated in Fig. 7B differs from the example illustrated in Fig. 5B in that the interconnection region 118 is formed, for example, before the etching of the trench 102. The aspects and features mentioned and described in conjunction with one or more of the examples and figures described above can also be combined with one or more of the other examples to replace a similar feature of the other example or to introduce the feature additionally into the other example.

Claims

Method for forming a wide bandgap semiconductor device (100), the method comprising: forming a mask pattern for a columnar region (116) over the first surface (1041) of the wide bandgap semiconductor body (104), the mask pattern having an opening that exposes part of a transistor cell area (TCA) of the wide bandgap semiconductor body (104); and forming the columnar region (116), comprising introducing dopants of the first conductivity type through the opening on the first surface (1041) into the transistor cell area (TCA) of the wide bandgap semiconductor body (104) by ion implantation;and then forming a trench-gate mask pattern (120) over a first surface (1041) of a wide-bandgap semiconductor body (104), wherein the trench-gate mask pattern (120) has an opening that exposes the trench-gate region of the transistor cell area (TCA) of the wide-bandgap semiconductor body (104); and etching a trench (102) into the wide-bandgap semiconductor body (104) over the opening in the trench-gate mask pattern (120), wherein the trench (102) extends deeper into the semiconductor body than the columnar region (116);Forming a shielding region (106), comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body (104) through a bottom and / or a side wall of the trench (102) by ion implantation, wherein the mask pattern (120) for a trench-gate region serves as an ion implantation mask for forming the shielding region (106) and subsequently expanding the trench (102), comprising an expansion process to form a sacrificial oxide (122) lining the side walls and a bottom of the trench (102) by thermal oxidation and removal of the sacrificial oxide (122). Method according to the preceding claim, wherein the expansion process is repeated several times. Method according to one of the preceding claims, wherein a width of the trench (102) on a first horizontal reference level (href1) is extended by 10% to 80%, wherein the first horizontal reference level (href1) has the same vertical distance to the first surface (1041) as to a bottom (1021) of the trench (102) before the extension process. Method according to one of the preceding claims, further comprising the formation of a trench-gate dielectric (1241) in the trench (102) after the expansion process. A method according to any of the preceding claims, further comprising, prior to etching the trench (102): forming a first mask pattern over the first surface (1041) of the wide-bandgap semiconductor body (104), wherein the first mask pattern has an opening that exposes a transistor cell area (TCA) of the wide-bandgap semiconductor body (104); forming a source layer (110) comprising introducing dopants of a second conductivity type into the transistor cell area (TCA) of the wide-bandgap semiconductor body (104) through the first surface (1041) by ion implantation; forming a body layer (112) comprising introducing dopants of the first conductivity type into the transistor cell area (TCA) of the wide-bandgap semiconductor body (104) through the first surface (1041) by ion implantation; and forming a current propagation layer (114) comprising dopants of the second conductivity type. Method according to the preceding claim, wherein an underside of the shielding area (106) is positioned at a smaller vertical distance to the first surface (1041) than an underside of the current propagation layer (114). Method according to one of the two preceding claims wherein a bottom side of the column-shaped region (116) is positioned between a bottom side of the body layer (112) and a bottom side of the current propagation layer (114) or is positioned between a bottom side of the source layer (110) and a bottom side of the body layer (112). Method according to one of the preceding claims, further comprising, after etching the trench (102): forming a connection area (118), comprising introducing dopants of the first conductivity type into the wide band gap semiconductor body (104) through a side wall of the trench (102) by ion implantation. Method according to the preceding claim, wherein the dopants of the first conductivity type of the junction area (118) are further introduced into the wide band gap semiconductor body (104) through a bottom side of the trench (102) by ion implantation. The method of claim 1, which further comprises, prior to etching the trench (102): forming a connection area (118), comprising introducing dopants of the first conductivity type into the wide bandgap semiconductor body (104) through the opening in the mask pattern (120) for a trench-gate region by ion implantation. Method according to any of the preceding claims, wherein the removal of the sacrificial oxide (122) comprises wet etching. A method according to any of the preceding claims, further comprising, after forming the trench (102) and before forming the shielding area (106): forming an auxiliary dielectric lining the side walls and underside of the trench (102). The method according to the preceding claim, further comprising, after forming the shielding area (106) and before expanding the trench (102): removal of the auxiliary dielectric.

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