Circuit abnormality positioning device

Abstract

The utility model embodiment provides a kind of circuit abnormality positioning device. Circuit abnormality positioning device is used for display panel, including general asynchronous transceiver and serial port detection component. General asynchronous transceiver has first RX pin and first TX pin, and first RX pin and first TX pin are connected to general asynchronous transceiver respectively, and display panel includes logic board, and logic board has second TX pin, and second TX pin is connected with first RX pin;Serial port detection component is connected with first TX pin, and serial port detection component and logic board are communicated by general asynchronous transceiver between UART, and serial port detection component is used to detect the data output by logic board. The utility model embodiment provides circuit abnormality positioning device can simplify test procedure, reduce test complexity.

Description

Technical Field

[0001] This utility model relates to the field of display panel technology, and more specifically to a circuit anomaly location device. Background Technology

[0002] Currently, displays are widely used in various fields, with LCDs (Liquid Crystal Displays) being one of the most common display products and widely adopted. Taking TFT-LCD (Thin Film Transistor Liquid Crystal Display) as an example, the television circuit architecture of a TFT-LCD mainly includes a Power board (power control board), a SOC board (System-on-a-Chip board), a logic board (TCON board, timing controller), and an XB board (horizontal drive board). The Power board is responsible for powering the backlight, SOC board, and logic board, and is generally manufactured by the OEM (Original Equipment Manufacturer). The logic board generates video signals and usually includes an operating system, also generally manufactured by the OEM. The logic board generates timing signals for driving the panel and handles optical adjustments, and is generally manufactured by the panel manufacturer. The XB board is responsible for positioning and transmitting video signal data, and is generally manufactured by the panel manufacturer. The logic board mainly includes a timing control chip, a DC-DC converter circuit, and a GAMMA module. The timing control chip generates timing signals for driving the panel and handles optical adjustments; the DC-DC converter circuit powers the timing control chip; and the GAMMA module generates the GAMMA reference voltage for the XB board.

[0003] As can be seen, the circuit architecture of TFT-LCD TVs is complex, and different boards are manufactured by different companies and departments. Therefore, when a TFT-LCD malfunctions, it is difficult to determine the source of the malfunction, especially when the logic board circuit is faulty. Locating the logic board circuit is cumbersome, requires a lot of time and effort, and is not very accurate. Utility Model Content

[0004] Therefore, to overcome at least some of the defects and deficiencies in the prior art, this utility model provides a convenient circuit anomaly location device. The circuit anomaly location device, used for a display panel, includes:

[0005] A universal asynchronous transceiver has a first RX pin and a first TX pin. The display panel includes a logic board with a second TX pin, which is connected to the first RX pin.

[0006] A serial port detection component is connected to the first TX pin. The serial port detection component communicates with the logic board via the universal asynchronous transceiver (UART). The serial port detection component is used to detect the data output by the logic board.

[0007] In some embodiments, the baud rate of the universal asynchronous transceiver is the same as the baud rate of the serial port detection component.

[0008] In some embodiments, the second TX pin is detachably connected to the first RX pin.

[0009] In some embodiments, the system further includes a first anomaly location component, which includes a PNP transistor, a first alarm element, and a first ground terminal. The PNP transistor has a base, an emitter, and a collector. The display panel also includes a SOC board, and the logic board has a VAA voltage terminal.

[0010] The base of the PNP transistor is electrically connected to the VAA voltage terminal;

[0011] The emitter of the PNP transistor is electrically connected to the SOC board;

[0012] The first alarm element is connected between the collector of the PNP transistor and the first ground terminal.

[0013] In some embodiments, the logic board includes a DC-DC circuit, and the base is connected to the DC-DC circuit.

[0014] In some embodiments, the first anomaly location component further includes a first resistor connected between the logic board and the base;

[0015] And / or, the first anomaly location component further includes a second resistor, one end of which is connected between the first resistor and the base, and the other end of which is connected between the SOC board and the emitter;

[0016] And / or, the first anomaly location component further includes a third resistor connected between the first alarm element and the first ground terminal.

[0017] In some embodiments, the second anomaly location component is detachably connected to the SOC board and the logic board.

[0018] In some embodiments, the circuit anomaly location device further includes a second anomaly location component, the logic board includes a timing control chip with an I / O interface, and the second anomaly location component includes a second alarm element and a second ground terminal, the second alarm element being connected between the I / O interface and the second ground terminal.

[0019] In some embodiments, the second anomaly location component further includes a fourth resistor connected between the second alarm element and the logic board.

[0020] In some embodiments, the second anomaly location component is detachably connected to the logic board.

[0021] The beneficial effects achieved by this utility model are as follows:

[0022] The circuit anomaly location device provided in this embodiment connects a serial port detection component to a logic board via a universal asynchronous transceiver, enabling UART communication between the logic board and the serial port detection component. Therefore, the serial port detection component can detect and determine the location of any anomalies on the logic board. This circuit anomaly location device requires no additional hardware and improves testing accuracy. It reduces testing steps, lowers testing costs, significantly simplifies the testing process, and reduces testing complexity. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a circuit anomaly location device in one embodiment of this utility model.

[0024] Figure 2 This is a circuit diagram of the first abnormality location component in one embodiment of the present invention.

[0025] Figure 3 This is a circuit diagram of the second abnormality location component in one embodiment of the present invention.

[0026] Explanation of reference numerals in the attached figures

[0027] 10. Circuit anomaly location device; 21. Universal asynchronous transceiver; 22. First RX pin; 23. First TX pin; 30. Serial port detection component; 40. First anomaly location component; 41. PNP transistor; 42. First alarm element; 50. Second anomaly location component; 51. Second alarm element; 60. Display panel; 61. Logic board; 611. Second TX pin; 613. DC-DC circuit; 614. Timing control chip; 615. IO interface; 62. SOC board. Detailed Implementation

[0028] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0029] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] It should also be noted that the division of multiple embodiments in this utility model is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0032] Currently, displays are widely used in various fields, among which liquid crystal displays (LCDs), as one of the most common display products, have become widely popular. Taking TFT-LCD as an example, the circuit architecture of TFT-LCD televisions is complex, and different boards are manufactured by different companies and departments. Therefore, when a TFT-LCD malfunctions, it is difficult to determine the source of the malfunction, especially when the logic board circuit is faulty. Locating the logic board circuit malfunction is cumbersome, requires a lot of time and effort, and is not very accurate.

[0033] Based on this, see Figure 1This utility model provides a circuit anomaly location device 10 for a display panel 60, including a universal asynchronous transceiver 21 and a serial port detection component 30. The display panel 60 includes a logic board 61, which has a second TX pin 611. The universal asynchronous transceiver 21 includes a first RX pin 22 and a first TX pin 23. The second TX pin 611 is connected to the first RX pin 22. Specifically, the second TX pin is used to transmit data inside the logic board 61 serially. The serial port detection component 30 is connected to the first TX pin 23, and the serial port detection component 30 communicates with the logic board 61 via the universal asynchronous transceiver 21 using UART. The serial port detection component 30 is used to detect the data output by the logic board 61. Logic board 61 is connected to universal asynchronous transceiver 21 via the second TX pin 611 and the first RX pin 22. Universal asynchronous transceiver 21 is connected to serial port detection component 30 via the first TX pin 23. Thus, logic board 61 and serial port detection component 30 can communicate via UART through universal asynchronous transceiver 21. Logic board 61 can transmit data to serial port detection component 30 through universal asynchronous transceiver 21. For example, the specific model of universal asynchronous transceiver 21 can be XR21V14x universal asynchronous transceiver. Serial port detection component 30 can read data from logic board 61, thereby determining circuit abnormalities in logic board 61 based on abnormal data conditions. For example, serial port detection component 30 can detect the TX waveform of logic board 61 to determine abnormalities; or, serial port detection component 30 can detect whether the received data contains errors, such as data loss, misalignment, or verification failure, thereby judging the abnormal state of logic board 61. For example, the serial port detection component 30 is a host computer configured with detection software, specifically, the detection software can be UartAssist or VOFA+, etc. Implementing UART communication requires less hardware, has a simpler structure, and allows for flexible baud rate settings, good compatibility, and easy adaptation to different logic boards 61. Specifically, the logic board 61 includes a timing control chip 614, which has a second TX pin 611. The second TX pin 611 is a GPIO pin, configured in UART TX transmit mode to transmit 8-bit data generated by the timing control chip 614. It is understood that the baud rate of the universal asynchronous transceiver 21 is the same as that of the serial port detection component 30 to ensure correct data transmission between the universal asynchronous transceiver 21 and the serial port detection component 30 and improve reliability. Furthermore, the data output by the logic board 61 is 8-bit data.

[0034] The circuit anomaly location device 10 provided in this embodiment connects the serial port detection component 30 to the logic board 61 via a universal asynchronous transceiver 21, enabling UART communication between the logic board 61 and the serial port detection component 30. Therefore, the serial port detection component 30 can detect and determine the location of an anomaly on the logic board 61. The circuit anomaly location device 10 requires no additional hardware and improves testing accuracy. It reduces testing steps, lowers testing costs, greatly simplifies the testing process, and reduces testing complexity.

[0035] In some specific embodiments, the second TX pin 611 and the first RX pin 22 are detachably connected. This allows the serial port detection component 30 and the universal asynchronous transceiver 21 to be reused, facilitating the detection of different display panels 60. Specifically, the second TX pin 611 and the first RX pin 22 are respectively provided with a snap-fit ​​portion or a snap-fit ​​component, and the second TX pin 611 and the first RX pin 22 are snap-fit ​​connected through the snap-fit ​​portion or the snap-fit ​​component, thus facilitating easy snap-fit ​​assembly and disassembly.

[0036] In some embodiments, see Figure 2 The circuit anomaly location device 10 also includes a first anomaly location component 40, which includes a PNP transistor 41, a first alarm element 42, and a first ground terminal. The PNP transistor 41 has a base (B), an emitter (E), and a collector (C). The display panel 60 also includes a SOC board 62, and the logic board 61 has a VAA voltage terminal. The base (B) of the PNP transistor 41 is electrically connected to the VAA voltage terminal. The emitter (E) of the PNP transistor 41 is electrically connected to the SOC board 62. The first alarm element 42 is connected between the collector (C) of the PNP transistor 41 and the first ground terminal. The first alarm element 42 is used to trigger an alarm when power is applied. The SOC board 62 is connected to the logic board 61 and can output power and data to the logic board 61. The SOC board 62 has a VCC voltage terminal, which is connected to the logic board 61 and is used to output voltage to the logic board 61. The VCC voltage terminal has a second voltage V2, which remains stable when the SOC board 62 is working normally.

[0037] The VAA voltage terminal is used to input voltage to the logic board 61. The VAA voltage terminal has normal and abnormal states. In the normal state, the first voltage V1 of the VAA voltage terminal satisfies: V1-V2>0.7V. At this time, the PNP transistor 41 is in the cutoff state, and there is no current at any of the three electrodes of the PNP transistor 41. The PNP transistor 41 is equivalent to an open switch, and the first alarm element 42 is not powered on and does not alarm. In the abnormal state, the third voltage V3 of the VAA voltage terminal satisfies: V3-V2<0.7V. At this time, the PNP transistor 41 is in the saturation state, which is equivalent to a closed switch. Current flows from the base B to the emitter E. Therefore, the first alarm element 42 is powered on and alarms, indicating that there is a circuit fault in the logic board 61.

[0038] Thus, since the VAA voltage terminal only has two states during operation—normal and abnormal—and the PNP transistor 41 can operate in different states with different conduction conditions, the first alarm element 42 can correctly trigger an alarm, preventing a situation where the VAA voltage terminal is abnormal but the first alarm element 42 fails to trigger an alarm. Through the PNP transistor and the first alarm element 42, it is convenient and quick to determine whether the power supply section of the logic board 61 is abnormal. The first abnormality location component 40 can quickly and conveniently determine whether the power supply section of the logic board 61 is abnormal, enabling the circuit abnormality location device 10 to also determine circuit abnormalities even when the power supply of the logic board 61 is abnormal. This facilitates the use of the universal asynchronous transceiver 21 and the serial port detection component 30, expanding the operating conditions of the circuit abnormality location device 10.

[0039] It should be noted that during the power-on process of the display panel 60, the voltage at the VAA terminal requires a certain amount of time to form. Therefore, even if the logic board 61 circuit is normal, there will be a period of time during which the voltage at the VAA terminal minus the second voltage V2 is less than 0.7V. During this process, the first alarm element 42 will also alarm. As the voltage at the VAA terminal gradually stabilizes, if the logic board 61 circuit is normal, the VAA terminal will have a first voltage V1, where V1-V2 > 0.7V, and the first alarm element 42 will not alarm. If the logic board circuit is abnormal, the VAA terminal will have a third voltage V3, where V3-V2 < 0.7V, and the first alarm element 42 will continue to alarm. Therefore, when performing testing, after the display panel 60 is powered on, it is necessary to wait for a period of time before making a judgment based on the alarm status of the first alarm element 42.

[0040] Specifically, see Figure 2The logic board 61 includes a DC-DC converter circuit 613, which has a VAA voltage terminal. Thus, the first anomaly location component 40 can conveniently and quickly determine whether the DC-DC converter circuit 613 is faulty. The logic board 61 includes a timing control chip 614, the DC-DC converter circuit 613, and a GAMMA module, etc. The DC-DC converter circuit 613 is responsible for powering the entire logic board 61; therefore, the first anomaly location component 40 can conveniently and quickly detect whether the power supply section of the logic board 61 is faulty.

[0041] Furthermore, the first voltage V1 of the VAA voltage terminal under normal conditions is 16.8V, and the third voltage V3 of the VAA voltage terminal under abnormal conditions is 0V. The second voltage V2 of the VCC voltage terminal is 12V. Therefore, under normal conditions, 16.8V - 12V > 0.7V, the PNP transistor 41 operates in the cutoff state, and there is no current at any of the three electrodes of the PNP transistor 41. The PNP transistor 41 is equivalent to an open switch, and the first alarm element 42 is not powered on and does not alarm. Under abnormal conditions, 0V - 12V < 0.7V, the PNP transistor 41 operates in the saturation state, and current flows from the base B to the emitter E. The first alarm element 42 is powered on and alarms, indicating a circuit fault on the logic board 61.

[0042] In some embodiments, the first anomaly location component 40 is detachably connected to the SOC board 62 and the logic board 61. This allows the first anomaly location component 40 to be reused, facilitating the detection of different display panels 60.

[0043] In some embodiments, see Figure 2 The first anomaly location component 40 also includes a first resistor R1, which is connected between the logic board 61 and the base B. Thus, the base B current controls the collector C current. The first resistor R1 limits the current flowing into the base B, preventing excessive base B current and consequently excessive collector C current, protecting the PNP transistor 41 from damage. The first resistor R1 also prevents noise signals from causing malfunctions in the PNP transistor 41, ensuring circuit stability. Specifically, the resistance of the first resistor R1 is 52kΩ.

[0044] In some embodiments, see Figure 2 The first abnormality location component 40 also includes a second resistor R2. One end of the second resistor R2 is connected between the first resistor R1 and the base B, and the other end of the second resistor R2 is connected between the SOC board 62 and the emitter E. The second resistor R2 helps to reduce the impact of temperature changes on the PNP transistor 41. Specifically, the resistance of the second resistor R2 is 10kΩ.

[0045] In some embodiments, see Figure 2The first abnormal location component 40 also includes a third resistor R3, which is connected between the first alarm element 42 and the first ground terminal. The third resistor R3 can limit the collector current C to prevent the PNP transistor 41 from being damaged due to overcurrent, and at the same time, it can also ensure that the first alarm element 42 operates under a suitable current. Specifically, the resistance of the third resistor R3 is 5.1kΩ.

[0046] In some embodiments, see Figure 3 The circuit anomaly location device 10 also includes a second anomaly location component 50. The logic board 61 includes a timing control chip 614, which has an I / O interface 615. The second anomaly location component 50 includes a second alarm element 51 and a second grounding terminal. The second alarm element 51 is connected between the I / O interface 615 and the second grounding terminal.

[0047] The timing control chip 614 has a signal parsing module for parsing the received front-end video signal. The I / O interface 615 has a first output state and a second output state. When the signal parsing module malfunctions in parsing the video signal, the I / O interface 615 is in the first output state, providing a 3.3V output. Therefore, the second alarm element 51 is powered on and triggers an alarm, indicating that the timing control chip 614 is malfunctioning. When the signal parsing module parses the video signal normally, the I / O interface 615 is in the second output state, providing a 0V output. Therefore, the second alarm element 51 is not powered on and does not trigger an alarm. This allows for convenient and quick determination of whether the timing control chip 614 has a circuit malfunction, facilitating further detection of circuit malfunctions on the logic board 61 using the universal asynchronous transceiver 21 and the serial port detection component 30.

[0048] Specifically, the signal analysis module is the TCON VBYONE RX IP, which can analyze video signals.

[0049] For some specific embodiments, see Figure 3 The second anomaly location component 50 also includes a fourth resistor R4, which is electrically connected between the second alarm element 51 and the logic board 61. The fourth resistor R4 helps to ensure that the second alarm element 51 operates at an appropriate current.

[0050] In some specific embodiments, the second anomaly location component 50 is detachably connected to the logic board 61. This allows the second anomaly location component 50 to be reused, facilitating the detection of different display panels 60.

[0051] In some specific embodiments, the first alarm element 42 is an LED light or a buzzer. Thus, the LED light can light up to trigger an alarm when powered on, and the buzzer can sound to trigger an alarm when powered on.

[0052] In some specific embodiments, the second alarm element 51 is an LED light or a buzzer. Thus, the LED light can light up to trigger an alarm when powered on, and the buzzer can sound to trigger an alarm when powered on.

[0053] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A circuit fault location device (10) for a display panel (60), characterized in that, include: A universal asynchronous transceiver (21) has a first RX pin (22) and a first TX pin (23). The display panel (60) includes a logic board (61) having a second TX pin (611) connected to the first RX pin (22). A serial port detection component (30) is connected to the first TX pin (23). The serial port detection component (30) communicates with the logic board (61) via the universal asynchronous transceiver (21) using UART. The serial port detection component (30) is used to detect the data output by the logic board (61).

2. The circuit anomaly location device (10) according to claim 1, characterized in that, The baud rate of the universal asynchronous transceiver (21) is the same as that of the serial port detection component (30).

3. The circuit anomaly location device (10) according to any one of claims 1 or 2, characterized in that, The second TX pin (611) is detachably connected to the first RX pin (22).

4. The circuit anomaly location device (10) according to claim 1, characterized in that, It also includes a first abnormality location component (40), which includes a PNP transistor (41), a first alarm element (42) and a first ground terminal. The PNP transistor (41) has a base, an emitter and a collector. The display panel (60) also includes a SOC board (62) and the logic board (61) has a VAA voltage terminal. The base of the PNP transistor (41) is electrically connected to the VAA voltage terminal; The emitter of the PNP transistor (41) is electrically connected to the SOC board (62); The first alarm element (42) is connected between the collector of the PNP transistor (41) and the first ground terminal.

5. The circuit anomaly location device (10) according to claim 4, characterized in that, The logic board (61) includes a DC-DC circuit (613), and the base is connected to the DC-DC circuit (613).

6. The circuit anomaly location device (10) according to claim 4, characterized in that, The first anomaly location component (40) further includes a first resistor, which is connected between the logic board (61) and the base. And / or, the first abnormal location component (40) further includes a second resistor, one end of which is connected between the first resistor and the base, and the other end of which is connected between the SOC board (62) and the emitter; And / or, the first abnormal location component (40) further includes a third resistor connected between the first alarm element (42) and the first ground terminal.

7. The circuit anomaly location device (10) according to any one of claims 4 to 6, characterized in that, The first anomaly location component (40) is detachably connected to the SOC board (62) and the logic board (61).

8. The circuit anomaly location device (10) according to claim 4, characterized in that, The circuit anomaly location device (10) further includes a second anomaly location component (50). The logic board (61) includes a timing control chip (614), which has an I / O interface (615). The second anomaly location component (50) includes a second alarm element (51) and a second ground terminal. The second alarm element (51) is connected between the I / O interface (615) and the second ground terminal.

9. The circuit anomaly location device (10) according to claim 8, characterized in that, The second abnormal location component (50) also includes a fourth resistor, which is connected between the second alarm element (51) and the logic board (61).

10. The circuit anomaly location device (10) according to any one of claims 8 or 9, characterized in that, The second anomaly location component (50) is detachably connected to the logic board (61).

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