A watchdog based delay start circuit
By implementing hardware control of the delayed startup circuit, the problem of infinite loops during the startup phase of the microcontroller was solved, optimizing system reliability and startup time, and ensuring efficient startup in complex electromagnetic environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI LONGCHEER TECH CO LTD
- Filing Date
- 2025-06-26
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, microcontrollers suffer from dead loops caused by watchdog chip erroneously triggering resets during the startup phase. This makes it impossible to find a balance between ensuring system reliability and startup time, which significantly prolongs startup time, especially in scenarios with high real-time requirements such as automotive electronics.
A watchdog-based delayed start circuit is adopted. A delayed control signal is generated through an RC network to control the switching device to achieve phased start-up at the hardware level. The reset signal is blocked and the watchdog chip is enabled after the delay ends, ensuring that the MCU initialization and watchdog start-up processes overlap.
It effectively avoids the infinite loop in the microcontroller initialization phase, improves the reliability and stability of system startup, significantly shortens the total startup time, and meets real-time requirements.
Smart Images
Figure CN224383687U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, and in particular to a watchdog-based delayed start circuit. Background Technology
[0002] In modern electronic systems, watchdog chips are widely used to monitor the operating status of microcontrollers (MCUs). By periodically checking the MCU's "feed" signal, they determine whether the system is working properly. When the MCU experiences abnormal conditions such as crashing or program malfunction, the watchdog chip outputs a reset signal to force a restart of the MCU, thereby ensuring system reliability.
[0003] However, existing watchdog application solutions have significant technical shortcomings during the system startup phase. The MCU needs to undergo multiple steps during power-on startup, including hardware initialization, software loading, and system configuration. This initialization process typically takes a considerable amount of time. In applications such as automotive electronics, the MCU initialization time often exceeds 100 milliseconds. Meanwhile, the watchdog chip begins operating immediately after system power-on, requiring the MCU to send a "feed the watchdog" signal within a specified timeout period; otherwise, a reset operation will be triggered.
[0004] This timing conflict leads to a serious startup infinite loop problem. When the MCU's initialization time exceeds the watchdog timeout, the MCU is forcibly reset by the watchdog before it has completed initialization. After the reset, the MCU restarts initialization, but because the initialization time still exceeds the watchdog timeout, the system is reset again. This cycle repeats, forming an infinite loop, which prevents the system from starting normally.
[0005] Existing technologies typically employ a software approach to address this issue, which involves initializing the watchdog-related GPIO ports and initiating the "watchdog feeding" operation as early as possible in the MCU's startup code. However, this method has reliability vulnerabilities: software initialization itself takes time, and the MCU remains in an unstable state until initialization is complete; the software approach relies on the correct execution of the code, and if the startup code itself has problems or the MCU hardware malfunctions, the infinite loop problem cannot be avoided.
[0006] Another existing approach is to serialize MCU initialization and watchdog timer startup, i.e., wait for the MCU to be fully initialized before starting the watchdog function. While this method avoids infinite loops, it significantly increases the overall system startup time. In applications with strict startup speed requirements, such as automotive electronic systems that need to respond to the first frame of the CAN bus within 120 milliseconds, excessively long startup times will prevent the system from meeting real-time requirements.
[0007] Existing technical solutions cannot optimize startup time while ensuring reliable system startup, resulting in an irreconcilable contradiction between reliability and real-time performance. Utility Model Content
[0008] The purpose of this invention is to provide a watchdog-based delayed startup circuit to solve the problem of dead loop caused by false triggering and reset of the watchdog during the startup phase of a microcontroller in the prior art.
[0009] To achieve the above objectives, this utility model provides a watchdog-based delayed start circuit, comprising:
[0010] A watchdog chip has a reset signal output terminal, an enable control terminal, and a signal input terminal;
[0011] The delay circuit, including an RC network, is used to generate a first delay control signal and a second delay control signal;
[0012] A control switching device includes a control terminal, a first conducting terminal, and a second conducting terminal; the control terminal is connected to the first delayed control signal output terminal, the first conducting terminal is connected to the reset signal output terminal, and the second conducting terminal is connected to the reset input terminal of the monitored processor;
[0013] The control switch is in an off state during the delay period of the first delay control signal and in an on state after the delay ends; the watchdog chip is enabled after the second delay control signal reaches a preset threshold.
[0014] Optionally, the RC network is composed of a series resistor and a capacitor bank, wherein the capacitor bank is composed of at least two capacitors connected in parallel.
[0015] Optionally, the control switching device includes a transistor, with the control terminal being the base, the first conducting terminal being the collector, and the second conducting terminal being the emitter.
[0016] Optionally, a logic control circuit may also be included, disposed between the output port of the monitored processor and the signal input terminal.
[0017] Optionally, the delay period of the first delay control signal is longer than the initialization time of the monitored processor.
[0018] Optionally, the initialization process of the monitored processor and the startup process of the watchdog chip overlap in time, and the total system startup time is equal to the larger of the initialization time of the monitored processor and the startup time of the delay control signal plus the watchdog chip.
[0019] Optionally, the total system startup time is less than the arithmetic sum of the initialization time of the monitored processor and the startup time of the watchdog chip.
[0020] Optionally, a protection circuit may also be included, which includes a diode for protecting the control switch.
[0021] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0022] The delay control signal generated by the delay circuit controls the switching device to open during the first time period, blocking the reset signal transmitted from the watchdog chip to the monitored processor. Simultaneously, the watchdog chip is enabled after the delay control signal reaches a preset threshold, achieving phased startup control at the hardware level. This effectively solves the problem of repeated resets caused by watchdog timeouts during microcontroller initialization, avoids system startup deadlocks, and significantly improves system startup reliability. The delay circuit is implemented using a pure hardware RC network, independent of software code, and has higher stability and reliability, ensuring normal operation even under software anomalies.
[0023] Furthermore, by configuring the parameters of the resistors and parallel capacitors in the RC network, the timing characteristics of the delay control signal can be precisely adjusted, optimizing the time overlap between the microcontroller initialization process and the watchdog chip startup process. This results in a significantly shorter overall system startup time compared to traditional serial startup methods. The transistor switch structure is simple, reliable, and has a fast response speed, ensuring precise control of the reset signal. The logic control circuit ensures that the watchdog signal only takes effect after the microcontroller is fully initialized, further enhancing system security. The diode configuration in the protection circuit effectively prevents damage to the control switching devices from reverse current and voltage spikes, improving the circuit's anti-interference capability and long-term stability in complex electromagnetic environments. Attached Figure Description
[0024] Figure 1 This is a circuit diagram of the watchdog-based delayed start circuit in an embodiment of this utility model;
[0025] Figure 2 This is a simplified block diagram illustrating the basic principle in the embodiments of this utility model;
[0026] Figure 3 This is a timing control strategy diagram in an embodiment of the present invention;
[0027] Figure 4 This is a standard timing diagram from a watchdog chip implementation example;
[0028] Figure 5 This is a schematic diagram of the system startup process in an embodiment of this utility model. Detailed Implementation
[0029] The following is a more detailed description of a watchdog-based time-delay start circuit of the present invention, with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.
[0030] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this patent.
[0031] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0032] This embodiment provides a watchdog-based delayed startup circuit; please refer to [reference needed]. Figure 1 It includes: watchdog chip U1, delay circuit and control switching device.
[0033] The watchdog chip U1 has a reset signal output terminal, an enable control terminal, and a signal input terminal.
[0034] Specifically, the watchdog chip U1 is model SGM823-TQN5G / TR, where the VCC pin is connected to the 3.3V power supply LDO_3V3, the GND pin is grounded, the nRESET pin is connected to the MCU reset terminal MCU_RESET_B_3V3_N, the WDI pin is connected to the MCU's watchdog signal MCU_EWDG_IN, and the nMR pin is used as the enable control terminal.
[0035] The delay circuit includes an RC network for generating a first delay control signal and a second delay control signal. The first delay signal, delay1, controls the switching of the reset signal path, ensuring that the MCU is not interfered with by reset during initialization. The second delay signal, delay2, controls the enable state of the watchdog chip and can be set with a different delay time than delay1.
[0036] In a specific example, the output of the delay circuit is divided into two paths: the first path is connected to the control switching device, and the second path is fed back to the enable control terminal of the watchdog chip U1.
[0037] The RC network consists of a resistor R3 and a capacitor bank connected in series, and the capacitor bank consists of capacitors C4 and C5 connected in parallel.
[0038] In a specific example, the resistance of resistor R3 is 100KΩ, and the capacitance of capacitors C4 and C5 is 10μF.
[0039] The specific connection relationships of the RC network are as follows:
[0040] One end of the resistor R3 is connected to the LDO_3V3 power supply, and the other end is connected to one end of the capacitors C4 and C5 and serves as the output terminal of the delay control signal. The other ends of the capacitors C4 and C5 are grounded.
[0041] Furthermore, the control switching device includes a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal is connected to the first delayed control signal output terminal, the first conducting terminal is connected to the reset signal output terminal, and the second conducting terminal is connected to the reset input terminal MCU_RESET_B_3V3_N of the monitored processor.
[0042] In this embodiment, the control switch is in an off state during the delay period T_delay1 of the first delay control signal, blocking the watchdog chip U1 from transmitting a reset signal to the monitored processor; after the delay ends, it is in an on state, allowing the reset signal to be transmitted, and the watchdog chip U1 is enabled after the second delay control signal reaches a preset threshold.
[0043] That is, during T_delay1, the reset signal is blocked, and the MCU can be safely initialized; during T_delay2, the watchdog chip U1 is disabled; when T_delay1 ends, the reset path is restored, and when T_delay2 ends, the watchdog chip is enabled and begins monitoring.
[0044] Please refer to Figure 2 The basic principle of this embodiment can be simplified as follows: the watchdog chip U1 is connected to the MCU via switch S1, the nReset signal is transmitted to the MCU through the control switch, and the MCU sends a "feed the watchdog" signal back to the watchdog chip U1 via the Data signal. This solution adds a controllable switch to the reset signal path to achieve delayed start control.
[0045] Please refer to Figure 3 The timing control strategy in this embodiment includes the following key time nodes:
[0046] MCU initialization time T1: Starting from the power-on of LDO_3V3, the MCU completes the entire process of hardware startup, BOOT initialization, signature verification, jump, and APP startup.
[0047] Watchdog start time Trp(T2): The time from when the watchdog chip U1 releases the nReset signal to when it is fully ready.
[0048] Delay switch control time T3 (T_delay1): The delay control time of the Watchdog-MCU switch, during which the transmission of the watchdog reset signal to the MCU is blocked.
[0049] Watchdog timeout time Twd: The monitoring timeout time of watchdog chip U1.
[0050] from Figure 3 It can be seen that through the delay control of T3 (T_delay1), the MCU can complete the key initialization operation during the delay switch control time without being disturbed by the watchdog. The watchdog's startup time is partially overlapped in the later stage of MCU initialization, thus achieving startup timing optimization.
[0051] Reference Figure 4 The standard timing diagram of the watchdog chip U1 shown indicates that:
[0052] The chip starts to work normally when the VCC voltage reaches the VRST+VHYS threshold; the nRESET pin remains low for a time Trp after power-on, and then releases to a high level; the WDI pin needs to receive a valid watchdog pulse within the Twd window period; if no valid watchdog signal is received after the Twd time, the nRESET pin outputs a low-level reset signal.
[0053] Combination Figure 3 and Figure 4 Based on timing analysis, this embodiment of the invention ensures that the MCU is not disturbed by watchdog reset during the Trp period and the critical initialization phase through delay control, while ensuring the effectiveness of the watchdog monitoring function after the system is running normally.
[0054] Furthermore, the control switching device includes a transistor Q1, which is an AD-UMD10N type NPN transistor.
[0055] The base of transistor Q1 is connected to the output of the RC network, the collector is connected to the nRESET output of watchdog chip U1, and the emitter is connected to the reset input MCU_RESET_B_3V3_N of the MCU.
[0056] During the delay period T_delay1 of the first delay control signal, the RC network outputs a low level, the transistor Q1 is in the off state, and the reset signal transmission path is blocked. When the first delay ends, the transistor Q1 turns on, and the reset signal transmission path is restored. Simultaneously, the watchdog chip U1 is enabled after the second delay control signal reaches a preset threshold.
[0057] Furthermore, it also includes a logic control circuit, which is disposed between the output port of the monitored processor and the signal input terminal.
[0058] The logic control circuit includes logic gate circuits to ensure that the watchdog signal can only be transmitted to the watchdog chip U1 after the monitored processor has completed initialization and is in a ready state.
[0059] In a specific example, the logic control circuit can be implemented using digital logic devices such as AND gates, OR gates, or buffers, or it can be implemented using devices such as analog switches or relays, which are common practices for those skilled in the art.
[0060] In this embodiment, the timing coordination is as follows:
[0061] The delay period of the first delay control signal is greater than the initialization time of the monitored processor, ensuring that the reset signal is effectively blocked before the processor completes critical initialization. The initialization process of the monitored processor and the startup process of the watchdog chip U1 overlap in time, making the total system startup time shorter than the arithmetic sum of the initialization time of the monitored processor and the startup time of the watchdog chip U1.
[0062] Traditional method: T_total ’ =T1 + T2 (serial superposition);
[0063] This solution: T_total = MAX(T1, T_delay1 + T2);
[0064] Due to the existence of time overlap, T_total was implemented. <T1+T2。
[0065] Where T1 is the MCU initialization time, T2(Trp) is the watchdog chip U1 startup time, and T_delay1(T3) represents the delay switch control time.
[0066] In this embodiment, the MCU completes initialization within time T1, the delay circuit controls the delay within T_delay1 to block the reset signal, and the calculation starts from the end of the delay. The watchdog is started and ready within time T2.
[0067] Furthermore, it also includes a protection circuit, which includes diodes D1 and D2 for protecting the control switching device.
[0068] In this embodiment, the working principle of the watchdog-based delayed start circuit is as follows:
[0069] When the system is powered on, the delay circuit begins the charging process and generates a delay control signal.
[0070] During the delay period T_delay1 of the first delay control signal, the RC network outputs a low level, the control switch is in the off state, blocking the reset signal transmission path from the watchdog chip U1 to the monitored processor, ensuring that the monitored processor is not reset by the watchdog during initialization.
[0071] Meanwhile, the enable control terminal nMR of the watchdog chip U1 remains disabled until the delay control signal reaches the preset threshold, and does not perform monitoring functions.
[0072] The watchdog chip is enabled after the second delay control signal reaches a preset threshold, and begins normal monitoring functions.
[0073] Because the watchdog timer is partially overlapped with the later stages of MCU initialization, the total startup time is significantly shorter than that of traditional serial overlay time. This optimizes the response speed of the first frame of the CAN bus and effectively solves the system dead loop problem caused by the watchdog timer's false triggering and reset during the MCU power-on initialization phase.
[0074] In practical applications, the parameters of the RC network can be adjusted to adapt to different MCUs and watchdog chip U1, ensuring that the delay time meets the system requirements.
[0075] like Figure 5 The system startup flow shown demonstrates the timing optimization effect of this solution. Through the control of the delay circuit, the MCU can complete critical initialization processes during the delay protection period, including hardware startup, BOOT initialization, signature verification, jump, and APP startup, without worrying about accidental watchdog resets. After the delay ends, the watchdog function is activated normally and begins monitoring the system. This design achieves optimized overlap between MCU initialization and watchdog startup, significantly shortening the total system startup time, improving the response speed of the first CAN bus message, and effectively solving the reset dead loop problem during the MCU initialization phase in traditional solutions.
[0076] In summary, the watchdog-based delayed startup circuit provided by this invention solves the startup dead loop problem caused by watchdog mis-triggers in traditional MCU systems from a hardware perspective through a delayed control architecture. A hardware delay circuit is used to control the timing of the watchdog reset signal. The delayed control signal generated by the RC network controls the blocking and recovery of the reset signal and controls the enable state of the watchdog chip. The control switch physically blocks the reset signal transmission path during the delay of the first delayed control signal, ensuring that the MCU is not interfered with by the watchdog during the initialization phase. Simultaneously, the watchdog chip remains disabled until the delayed control signal reaches a preset threshold, avoiding false monitoring in an unready state. By overlapping the initialization process of the monitored processor with the startup process of the watchdog chip in time, the total system startup time is shorter than the arithmetic sum of the initialization time of the monitored processor and the startup time of the watchdog chip, significantly improving system startup efficiency. It is implemented purely in hardware, without relying on software logic, and has extremely high reliability. Its simple structure facilitates mass production. It improves the stability and lifespan of the circuit and has significant promotional value.
[0077] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A watchdog based delay start circuit, characterized by, include: A watchdog chip has a reset signal output terminal, an enable control terminal, and a signal input terminal; The delay circuit, including an RC network, is used to generate a first delay control signal and a second delay control signal; A control switching device includes a control terminal, a first conducting terminal, and a second conducting terminal; the control terminal is connected to the first delayed control signal output terminal, the first conducting terminal is connected to the reset signal output terminal, and the second conducting terminal is connected to the reset input terminal of the monitored processor; The control switch is in an off state during the delay period of the first delay control signal and in an on state after the delay ends; the watchdog chip is enabled after the second delay control signal reaches a preset threshold.
2. The watchdog-based delayed start circuit according to claim 1, characterized in that: The RC network consists of a series connection of resistors and capacitors, and the capacitor group consists of at least two capacitors connected in parallel.
3. The watchdog-based delayed start circuit according to claim 1, characterized in that: The control switching device includes a transistor, with the control terminal being the base, the first conducting terminal being the collector, and the second conducting terminal being the emitter.
4. The watchdog-based delayed start circuit according to claim 1, characterized in that: It also includes a logic control circuit, which is disposed between the output port of the monitored processor and the signal input terminal.
5. The watchdog-based delayed start circuit according to claim 1, characterized in that: The delay period of the first delay control signal is greater than the initialization time of the monitored processor.
6. The watchdog-based delayed start circuit according to claim 5, characterized in that: The initialization process of the monitored processor and the startup process of the watchdog chip overlap in time. The total system startup time is equal to the larger of the initialization time of the monitored processor and the startup time of the delay control signal plus the watchdog chip.
7. The watchdog-based delayed start circuit according to claim 6, characterized in that: The total system startup time is less than the arithmetic sum of the initialization time of the monitored processor and the startup time of the watchdog chip.
8. The watchdog-based delayed start circuit according to claim 1, characterized in that: It also includes a protection circuit, which includes a diode for protecting the control switch.