Wafer baking chamber and semiconductor apparatus

Abstract

A wafer baking chamber and a semiconductor device, the wafer baking chamber is provided with a cover structure and a groove structure of a partition structure, which at least enclose a connecting space and a wiring channel communicated with the connecting space, so that the first connecting line and the second connecting line in the connecting unit corresponding to the partition structure and the base can be orderly arranged in the connecting space and the wiring channel, avoiding the disorder of the connecting line arrangement in the wafer baking chamber. In addition, the base bottom in the upper process chamber of the adjacent process chambers is communicated with the connecting space in the partition structure below, so that the first connecting line led out from the base bottom can be introduced into the connecting space and led out from the cavity through the wiring channel. At the same time, the second connecting line corresponding to the partition structure can also be introduced into the connecting space and enter the wiring channel, which reduces the difficulty of installation and maintenance of the wiring and improves the baking efficiency and quality of the baking chamber.

Description

Technical Field

[0001] This application relates to the semiconductor field, specifically to a wafer baking chamber and semiconductor equipment. Background Technology

[0002] In dry etching systems used in semiconductor manufacturing, there are typically two main parts: a reaction apparatus and a baking apparatus. The reaction apparatus uses a specific ratio of special gases to react on the wafer surface under specific temperature conditions, while the baking apparatus uses temperature control to evaporate excess dielectric material from the wafer surface after the reaction.

[0003] To improve the space utilization and production efficiency of baking equipment, the industry has proposed a multi-chamber wafer baking device.

[0004] In existing technologies, the wiring arrangement of electrical components in multi-chamber wafer baking apparatuses is often messy and disordered, which affects baking efficiency. Therefore, a new wiring method for multi-chamber baking is needed to reduce installation and maintenance difficulties, and improve baking efficiency and product quality. Utility Model Content

[0005] The problem solved by this utility model embodiment is to provide a wafer baking chamber and semiconductor equipment, so that the connecting lines in the wafer baking chamber are arranged in an orderly manner, thereby improving the baking efficiency and quality of the wafer baking chamber.

[0006] To address the aforementioned issues, this application provides a wafer baking chamber, comprising: a cavity including an internal space; one or more partition structures disposed within the cavity, dividing the internal space of the cavity into multiple process chambers stacked vertically, each partition structure comprising: a partition body; multiple groove structures spaced apart on the top of the partition body along a first direction; a cover structure disposed on the groove structures, wherein the cover structure and the groove structures at least enclose a connecting space, and a wiring channel communicating with the connecting space; a base located within the process chambers, the base being used to support the wafer, and the bottom of the base in the upper process chamber of an adjacent process chamber communicating with the connecting space; and a connecting unit disposed within the connecting space and the wiring channel, comprising a first connecting line and a second connecting line, the first connecting line extending from the bottom of the base, and the second connecting line extending from the partition structure.

[0007] Optionally, the partition structure further includes: a wiring channel outlet located at the bottom of the wiring channel away from the connection space; the cavity further includes: a cavity through hole located below the wiring channel outlet and corresponding to the wiring channel outlet, the cavity through hole penetrating the side wall of the lower cavity in the height direction.

[0008] Optionally, one side wall of the lower process chamber in the second direction is located inside the corresponding side wall of the upper process chamber in the second direction, wherein the second direction is perpendicular to the first direction.

[0009] Optionally, the groove structure includes: a first groove located on the top of the partition body, the bottom surface of the first groove abutting against the cover plate structure; a second groove located in a portion of the bottom surface of the first groove; and a third groove located in a portion of the bottom surface of the second groove.

[0010] Optionally, the first groove includes a main groove area and a side groove area located on one side of the main groove area, the side groove area and the main groove area are connected; the second groove includes a lead wire transition area and a wiring area located on one side of the lead wire transition area, the lead wire transition area is located at the bottom of the main groove area, and the wiring area is located at the bottom of the side groove area; the third groove is located at the bottom of the lead wire transition area.

[0011] Optionally, the cover plate structure includes: a plate body and a through hole located on the plate body, wherein the through hole is located directly above the third groove.

[0012] Optionally, the base is disposed on the cover plate structure, and the base includes: a wafer carrier disk; and a support portion located at the bottom of the wafer carrier disk, the support portion having a line channel communicating with the through hole.

[0013] Optionally, the plate body includes: a first part located at the top of the connection space, the first part having the through hole; a second part located on one side of the first part and connected to the first part, the second part being located at the top of the wiring channel; the cover plate structure further includes: a strip groove disposed on the second part facing the wiring channel, the strip groove communicating with the connection space and the wiring channel.

[0014] Optionally, the cover plate structure further includes: a sealing groove located on the side of the cover plate structure facing the groove structure, the sealing groove being located around the through hole and the strip groove; and a sealing ring disposed in the sealing groove.

[0015] Optionally, the wafer baking chamber further includes: a first heating unit disposed inside the partition body for heating the partition structure, and the first heating unit is connected to the second connecting line; and a second heating unit disposed inside the base for heating the base, and the second heating unit is connected to the first connecting line.

[0016] Optionally, at least one of the first heating unit and the second heating unit includes a connection end disposed in the connection space; and a temperature sensor disposed in the connection space and spaced apart from the connection end.

[0017] Optionally, both the first heating unit and the second heating unit include a heating wire.

[0018] Optionally, the wafer baking chamber further includes: an air inlet communicating with the process chamber and located on one side of the process chamber in a second direction, the second direction being perpendicular to the first direction; an air extraction port communicating with the process chamber and located on the other side of the process chamber in the second direction; the groove structure is disposed close to the air extraction port in the second direction.

[0019] Optionally, the groove structure extends along the second direction, and one end of the groove structure in the second direction is an open end, which is connected to the side wall of the partition body in the second direction.

[0020] This application provides a semiconductor device, including: the aforementioned wafer baking chamber.

[0021] Compared with the prior art, the technical solution of the embodiments of this application has the following advantages:

[0022] The wafer baking chamber provided in this embodiment includes a cavity and one or more partition structures. The partition structures are disposed within the cavity, dividing the internal space of the cavity into multiple process chambers stacked vertically, thus realizing a multi-layer baking chamber structure and improving the space utilization of the wafer baking chamber. The cover plate structure and groove structure of the partition structure at least enclose a connecting space and a wiring channel communicating with the connecting space. This allows the first and second connecting lines in the connecting units corresponding to the partition structure and the base to be arranged orderly in the connecting space and the wiring channel, avoiding the chaotic arrangement of connecting lines in the wafer baking chamber. Furthermore, the bottom of the base in the upper process chamber of an adjacent process chamber communicates with the connecting space in the partition structure below it. This allows the first connecting line extending from the bottom of the base to enter the connecting space and exit the cavity through the wiring channel. Simultaneously, the second connecting line corresponding to the partition structure can also be introduced into the connecting space and enter the wiring channel, reducing the difficulty of wiring installation and maintenance and improving the baking efficiency and quality of the baking chamber. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 This is an isometric view of a wafer baking chamber according to an embodiment of the present invention;

[0025] Figure 2 This is a cross-sectional view of the wafer baking chamber according to an embodiment of the present invention;

[0026] Figure 3 This is a cross-sectional view of the upper chamber of the wafer baking chamber according to an embodiment of the present invention;

[0027] Figure 4 This is a cross-sectional view of the lower chamber of the wafer baking chamber according to an embodiment of the present invention;

[0028] Figure 5 This is a cross-sectional schematic diagram of the partition structure and base in a wafer baking chamber according to an embodiment of the present invention;

[0029] Figure 6 This is a structural diagram of the partition structure in the wafer baking chamber according to an embodiment of the present invention;

[0030] Figure 7 This is a cross-sectional view of the partition structure in the wafer baking chamber of an embodiment of the present invention along the extension direction of the groove structure;

[0031] Figure 8 This is a cross-sectional view of the partition structure in the wafer baking chamber of an embodiment of the present invention in a horizontal plane;

[0032] Figure 9 This is a top view of the cover plate structure in the wafer baking chamber according to an embodiment of the present invention;

[0033] Figure 10 This is a bottom view of the cover plate structure in the wafer baking chamber according to an embodiment of this utility model. Detailed Implementation

[0034] Currently, in existing technologies, the wiring arrangement of electrical components within the wafer baking chamber is often messy and disordered, which affects baking efficiency. Therefore, a new wiring lead-out method is needed to adapt to the multi-chamber layout of wafer baking chambers, reduce installation and maintenance difficulties, and improve baking efficiency and product quality.

[0035] The wafer baking chamber provided in this embodiment includes a cavity and one or more partition structures. The partition structures are disposed within the cavity, dividing the internal space of the cavity into multiple process chambers stacked vertically, thus realizing a multi-layer baking chamber structure and improving the space utilization of the wafer baking chamber. The cover plate structure and groove structure of the partition structure at least enclose a connecting space and a wiring channel communicating with the connecting space. This allows the first and second connecting lines in the connecting units corresponding to the partition structure and the base to be arranged orderly in the connecting space and the wiring channel, avoiding the chaotic arrangement of connecting lines in the wafer baking chamber. Furthermore, the bottom of the base in the upper process chamber of an adjacent process chamber communicates with the connecting space in the partition structure below it. This allows the first connecting line extending from the bottom of the base to enter the connecting space and exit the cavity through the wiring channel. Simultaneously, the second connecting line corresponding to the partition structure can also be introduced into the connecting space and enter the wiring channel, reducing the difficulty of wiring installation and maintenance and improving the baking efficiency and quality of the baking chamber.

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0038] refer to Figures 1 to 10 The diagram shows a schematic diagram of the wafer baking chamber according to the first embodiment of the present invention.

[0039] The wafer baking chamber includes: a cavity 100, including an internal space; and one or more partition structures 101 (such as...). Figure 2 As shown), it is arranged in the cavity 100, dividing the internal space of the cavity 100 into multiple process chambers 102 stacked in the vertical direction Z (as shown). Figure 2 As shown), the partition structure 101 includes: a partition body 1011 (as shown) Figure 5 As shown); multiple groove structures 1012 (such as...) Figure 6 As shown), the cover plate structure 104 is arranged at intervals along the first direction X on the top of the partition body 1011; Figure 9 or Figure 10 As shown), it is disposed on the groove structure 1012, and the cover plate structure 104 and the groove structure 1012 at least enclose a connecting space 101a, and the connecting space 101a (as shown) is disposed on the groove structure 1012, and the cover plate structure 104 and the groove structure 1012 at least enclose a connecting space 101a (as shown) Figure 5 The wiring channel 101b connected (as shown) Figure 5 (As shown); base 103, located in the process chamber 102, the base 103 is used to support the wafer, and the bottom of the base 103 in the upper process chamber 102 of the adjacent process chamber 102 is connected to the connection space 101a; connection unit (not shown in the figure), disposed in the connection space 101a and wiring channel 101b, including a first connection line (not shown in the figure) and a second connection line (not shown in the figure), the first connection line is led out from the bottom of the base 103, and the second connection line is led out from the partition structure 101.

[0040] The wafer baking chamber provided in this embodiment of the present invention includes a cavity 100 and one or more partition structures 101. The partition structure 101 is disposed in the cavity 100, dividing the internal space of the cavity 100 into multiple process chambers 102 stacked in the vertical direction Z, thereby realizing the construction of a multi-layer baking chamber and improving the space utilization of the wafer baking chamber. The cover structure 104 and groove structure 1012 of the partition structure 101 at least enclose a connection space 101a and a wiring channel 101b communicating with the connection space 101a. This allows the first and second connecting lines in the connection units corresponding to the partition structure 101 and the base 103 to be arranged in an orderly manner in the connection space 101a and the wiring channel 101b, avoiding the messy and disordered arrangement of connecting lines in the wafer baking chamber. In addition, the bottom of the base 103 in the upper process chamber 102 of the adjacent process chamber 102 is connected to the connection space 101a in the partition structure below it. This allows the first connecting line at the bottom of the base 103 to be introduced into the connection space 101a and led out of the process chamber through the wiring channel 101b. At the same time, the second connecting line corresponding to the partition structure 101 can also be introduced into the connection space 101a and enter the wiring channel 101b. The connection unit allows the first and second connection lines to be neatly arranged in the connection space 101a and wiring channel 101b after being led out from the base 103 and the partition structure 101, respectively. This reduces the difficulty of wiring installation and maintenance and improves the baking efficiency and quality of the baking chamber.

[0041] In this embodiment, the cavity 100 includes an internal space. The internal space is used to accommodate the partition structure 101, the cover structure 104, and the base 103, providing a sealed environment for wafer baking.

[0042] In this embodiment, the cavity 100 is rectangular. In other embodiments, the cavity 100 may also be a disk or other shapes suitable for wafer baking processes.

[0043] In this embodiment, one or more partition structures 101 are disposed in the cavity 100, dividing the internal space of the cavity 100 into multiple process chambers 102 stacked in the vertical direction Z. Each process chamber 102 can independently perform wafer baking, improving production efficiency. Moreover, the partition structure 101 is used to divide the cavity 100 into multiple independent process chambers 102, and each process chamber 102 can independently control process parameters such as temperature and atmosphere, thereby realizing differentiated baking treatment for different batches of wafers, improving production flexibility and efficiency.

[0044] Specifically, such as Figure 6 As shown, the partition structure 101 includes a partition body 1011 and a plurality of groove structures 1012, which are spaced apart on the top of the partition body 1011 along a first direction X.

[0045] In this embodiment, the partition body 1011 is the main part of the partition structure 101, and the partition body 1011 has a plate-like structure.

[0046] In this embodiment, multiple groove structures 1012 are spaced apart along the first direction X on the top of the partition body 1011. The groove structures 1012 provide installation positions for the cover plate structure 104 and together with the cover plate structure 104 form a connecting space 101a (e.g., Figure 5 (as shown) and wiring channel 101b (as shown) Figure 5 (As shown). The shape and size of the groove structure 1012 match the shape and size of the cover structure 104 to ensure the sealing of the connection space 101a and the wiring channel 101b. Thus, the presence of the groove structure 1012 allows the first connecting line connected to the base 103 and the second connecting line connected to the partition structure 101 to be arranged in an orderly manner in the connection space 101a and the wiring channel 101b, avoiding the messiness of the wiring.

[0047] It should be noted that the wafer baking chamber further includes: a first heating unit 111 (e.g., Figure 8 As shown), it is disposed inside the partition body 1011 for heating the partition structure 101, and the connection end 110 of the first heating unit 111 (as shown) .... Figure 6 (As shown) The first heating unit 111 is led out to the connection space 101a and connected to the second connection line in the connection unit. When working in the wafer baking chamber, the first heating unit 111 is connected to the external power supply through the connection terminal 110 and the second connection line to heat the partition structure 101.

[0048] In this embodiment, the groove structure 1012 extends along the second direction Y, and one end of the groove structure 1012 in the second direction Y is an open end 1013 (e.g., Figure 6As shown), the open end 1013 is connected to the side wall of the partition body 1011 in the second direction Y.

[0049] The groove structure 1012 extends along the second direction Y, so that the connection space 101a and the wiring channel 101b also extend along the second direction Y, providing a wiring path for the connecting lines in the connection unit. The open end of the groove structure 1012 reduces the installation difficulty of the cover structure 104.

[0050] In this embodiment, the first direction X is the length direction of the horizontal cavity 100. In other embodiments, the first direction X in this embodiment is the width direction of the horizontal cavity 100.

[0051] In this embodiment, the second direction Y is perpendicular to the first direction X.

[0052] In this embodiment, the partition structure 101 further includes: a wiring channel outlet 1014 (e.g., Figure 6 As shown), located at the bottom of the wiring channel 101b away from the connection space 101a. The cavity 100 also includes: a cavity through-hole 107 (as shown). Figure 4 As shown), the location is below the wiring channel outlet 1014 and corresponds to the wiring channel outlet 1014, that is, directly below the wiring channel outlet 1014. This facilitates the first connecting line drawn from the bottom of the base 103 in the upper process chamber 102 and the second connecting line drawn from the partition structure 101 to pass through the wiring channel outlet 1014 and the cavity wire hole 107, and then penetrate the side wall of the lower cavity 100 in the height direction, thereby leading the first connecting line and the second connecting line out from the inside of the cavity 100 to the outside of the cavity 100.

[0053] Specifically, the wiring channel outlet 1014 allows the first and second connecting lines to extend from the connection space 101a along the wiring channel 101b to the wiring channel outlet 1014, and then exit to the outside of the cavity 100 through the cavity wiring hole 107 below the wiring channel outlet 1014 for connection to an external power supply or other equipment. The corresponding arrangement of the wiring channel outlet 1014 and the cavity wiring hole 107 makes the exit paths of the first and second connecting lines more regular, avoiding the messy arrangement of the first and second connecting lines inside the cavity 100, thereby reducing the difficulty of installation and maintenance, and thus improving the baking efficiency and quality of the wafer baking chamber.

[0054] In this embodiment, the lower process chamber 102 is located on one side wall in the second direction Y, inside the corresponding side wall of the upper process chamber 102 in the second direction Y. The second direction is perpendicular to the first direction. This makes the material of the cavity 100 below the cavity wire hole 107, providing a structural basis for the cavity wire hole 107. This allows the connecting unit to safely pass through the material of the cavity 100 instead of being directly exposed in the lower process chamber 102, thereby ensuring the smooth lead-out of the first and second connecting wires and ensuring the normal operation of the process chamber. Therefore, it is beneficial to improve the quality of the product, avoid the connecting wires being directly baked by the high temperature inside the process chamber 102, and extend the service life of the connecting wires.

[0055] Specifically, the lower process chamber 102 is located on the side wall of the upper process chamber 102 near the exhaust port 106 in the second direction Y, inside the side wall of the upper process chamber 102 near the exhaust port 106 in the second direction Y.

[0056] It should be noted that, as Figure 5 As shown, the partition body 1011 includes: an upper partition 1011a and a lower partition 1011b located below the upper partition 1011a, and the upper partition 1011a and the lower partition 1011b are fixedly connected.

[0057] As an example, the upper partition 1011a and the lower partition 1011b are connected by welding. A first heating unit 111 is disposed between the upper partition 1011a and the lower partition 1011b.

[0058] like Figure 6 and Figure 7 As shown, the groove structure 1012 includes: a first groove 10121 located at the top of the partition body 1011, the bottom surface of the first groove 10121 abutting against the cover structure 104; a second groove 10122 located in a portion of the bottom surface of the first groove 10121; and a third groove 10123 located in a portion of the bottom surface of the second groove 10122. The multi-level groove morphology of the first groove 10121, the second groove 10122, and the third groove 10123 ensures that while the cover structure 104 abuts against the bottom surface of the first groove 10121 of the groove structure 1012, there is a connection space 101a and a wiring channel 101b between the cover structure 104 and the groove structure 1012 for accommodating the connection unit.

[0059] It should be noted that the connecting space 101a and the wiring channel 101b are the spaces enclosed by the second groove 10122, the third groove 10123 and a portion of the first groove 10121 together with the cover plate structure 104.

[0060] Specifically, the third groove 10123 and the area of ​​the second groove 10122 directly above the third groove 10123 constitute the connecting space 101a, and the remaining area of ​​the second groove 10122, together with the cover plate structure 104, constitutes the wiring channel 101b. The connecting space 101a and the wiring channel 101b are used to set the first connecting line and the second connecting line.

[0061] like Figure 7 As shown, the first groove 10121 includes a main groove area 10121a and a side groove area 10121b located on one side of the main groove area 10121a, the side groove area 10121b and the main groove area 10121a being connected; the second groove 10122 includes a lead wire transition area 10122a and a wiring area 10122b located on one side of the lead wire transition area 10122a, the lead wire transition area 10122a being located at the bottom of the main groove area 10121a, and the wiring area 10122b being located at the bottom of the side groove area 10121b; the third groove 10123 is located at the bottom of the lead wire transition area 10122a. The third groove 10123 and the lead wire transition area 10122a are used to form a connection space 101a, while the wiring area 10122b can form part of the wiring channel 101b.

[0062] The groove structure 1012 forms a multi-layered stepped groove, which can not only fix the cover plate structure 104, but also arrange the connecting lines in the connecting unit in an orderly manner, thereby avoiding the problem of messy and disordered wiring, improving the performance and reliability of the wafer baking chamber, and improving the space utilization rate inside the wafer baking chamber.

[0063] A cover plate structure 104 is disposed on the groove structure 1012, and the cover plate structure 104 and the groove structure 1012 at least enclose a connection space 101a and a wiring channel 101b communicating with the connection space 101a. A first connecting line leading out from the bottom of the base 103 and a second connecting line leading out from the partition structure enter the connection space 101a. The wiring channel 101b is used to guide the first connecting line and the second connecting line from the connection space 101a to the outside of the cavity 100. The cover plate structure 104 is disposed on the groove structure 1012, so that gas or external impurities are not easily allowed to enter the connection space 101a and the wiring channel 101b during wafer baking.

[0064] In this embodiment, the cover plate structure 104 (such as...) Figure 9 (As shown) includes: a plate 1041 and a through hole 1042 located on the plate 1041, and the through hole 1042 is located in the third groove 10123 (as shown). Figure 7 Directly above (as shown).

[0065] The plate 1041 is the main part of the cover plate structure 104, used to cover the groove structure 1012, forming the top of the connection space 101a and the wiring channel 101b. The through hole 1042 is located on the plate 1041 and directly above the third groove 10123, so that the first connecting line in the base 103 can smoothly pass through the through hole 1042 into the connection space 101a.

[0066] like Figure 9 and Figure 10 As shown, the plate body 1041 includes: a first part 1041a, located at the top of the connecting space 101a, wherein the first part 1041a is provided with the through hole 1042; and a second part 1041b, located on one side of the first part 1041a and connected to the first part 1041a, wherein the second part 1041b is located at the top of the wiring channel 101b. The cover plate structure 104 further includes: a strip groove 1043 (e.g., Figure 10 As shown in the figure, the second part 1041b is provided facing the wiring channel 101b, and the strip groove 1043 is connected to the connection space 101a and the wiring channel 101b.

[0067] The through hole 1042 on the first part 1041a is used for the first connecting line in the base 103 to pass through. The strip groove 1043 on the second part 1041b is provided facing the wiring channel 101b, which means that the wiring channel 101b of the first connecting line and the second connecting line is further enlarged, making the arrangement of the connecting lines more orderly. In addition, the strip groove 1043 is connected to the connecting space 101a and the wiring channel 101b, increasing the placement space for the first connecting line and the second connecting line.

[0068] It should be noted that in this embodiment, the top of the cover structure 104 is flush with the top of the partition body 1011, providing a relatively flat bottom environment for the upper process chamber 102, which is conducive to airflow.

[0069] The cover plate structure 104 further includes: a sealing groove (not shown in the figure), located on the side of the cover plate structure 104 facing the groove structure 1012, the sealing groove being located around the through hole 1042 and the strip groove 1043; and a sealing ring (not shown in the figure), disposed in the sealing groove.

[0070] In this embodiment, the cover plate structure 104 further includes a sealing groove and a sealing ring. The sealing groove is located on the side of the cover plate structure 104 facing the groove structure 1012 and is located around the through hole 1042 and the strip groove 1043. The sealing ring is disposed in the sealing groove. This improves the sealing performance between the cover plate structure 104 and the groove structure 1012, preventing gas during the wafer baking process from entering the wiring channel 101b and the connection space 101a through the gap between the cover plate structure 104 and the groove structure 1012, thereby improving the service life of the first and second connecting lines.

[0071] The base 103 is located in the process chamber 102, and the bottom of the base 103 in the upper process chamber 102 of the adjacent process chamber 102 is connected to the connection space 101a. The base 103 is used to support the wafer.

[0072] The bottom of the base 103 is connected to the connection space 101a, so that the first connecting line corresponding to the base 103 can be easily introduced into the connection space 101a and led out of the cavity 100 through the wiring channel 101b, thus avoiding the problem of messy and disorderly wiring.

[0073] like Figure 2 and Figure 3 As shown, the base 103 is disposed on the cover plate structure 104. The base 103 includes: a wafer carrier disk 1031; and a support portion 1032 located at the bottom of the wafer carrier disk 1031. The support portion 1032 has a line channel 1033 communicating with the through hole 1042.

[0074] The wafer carrier disk 1031 is a carrier structure for the wafer during the processing. The support part 1032 is located at the bottom of the wafer carrier disk 1031. Because the base 103 is set on the cover plate structure 104, the corresponding support part 1032 is set on the cover plate structure 104. The wire channel 1033 and the through hole 1042 in the support part 1032 are connected, so that the first connecting wire can be led out from the wire channel 1033 and pass through the through hole 1042 into the connecting space 101a.

[0075] The wafer baking chamber further includes: a second heating unit 113 (such as...). Figure 5 As shown in the diagram, the second heating unit 113 is disposed inside the base 103 for heating the base 103, and is connected to the first connecting line. When operating in the wafer baking chamber, the second heating unit 113 is connected to an external power supply through the first connecting line to heat the base 103.

[0076] In this embodiment, the second heating unit 113 is disposed in the wafer carrier disk 1031, and the first connecting line (not shown in the figure) is led out from the wafer carrier disk 1031 and passes through the wire channel 1033 in the support portion 1032 (e.g., Figure 5 As shown), and through holes 1042 on cover plate structure 104 (as shown). Figure 5 After (as shown), enter the connection space 101a (as shown). Figure 5 As shown in the figure.

[0077] It should be noted that the wafer baking chamber further includes: an air inlet 105 (e.g., Figure 3 As shown), it communicates with the process chamber 102 and is located on one side of the process chamber 102 in the second direction Y; the exhaust port 106 (as shown) Figure 3 As shown), it is connected to the process chamber 102 and is located on the other side of the process chamber 102 in the second direction Y.

[0078] The air inlet 105 and the air outlet 106 are used to introduce process gas into the process chamber 102 and exhaust waste gas, respectively, to realize gas circulation and renewal within the process chamber 102. The air inlet 105 and the air outlet 106 are located on both sides of the process chamber 102 in the second direction Y, forming an airflow path, which is beneficial to the uniform distribution of process gas and the rapid discharge of waste gas.

[0079] In this embodiment, there are multiple air inlets 105, which are respectively disposed on two side walls opposite to each other in the first direction X. The use of multiple air inlets 105 in the process chamber 102 allows for a more uniform distribution of gas within the process chamber 102, increasing the contact area between the gas and the wafer, thereby improving baking efficiency.

[0080] It should be noted that the groove structure 1012 (e.g.) Figure 6 (As shown) It is set near the air extraction port 106 in the second direction Y.

[0081] Setting the groove structure 1012 close to the exhaust port 106 is beneficial for directing any trace pollutants or gases that may be generated in the connection space 101a and wiring channel 101b directly to the exhaust port 106, thereby reducing their diffusion in the process chamber 102.

[0082] It should be noted that at least one of the first heating unit 111 and the second heating unit 113 includes a connection end 110, which is disposed in the connection space 101a; the wafer baking chamber further includes a temperature sensor 112, which is disposed in the connection space 101a and spaced apart from the connection end 110.

[0083] In this embodiment, the first heating unit 111 includes a connection end 110 ( Figure 6(Only one is shown in the diagram), and all of them are set in the connection space 101a to facilitate the connection of the first heating unit 111 and the second connecting line.

[0084] In this embodiment, the first heating unit 111 includes a heating wire. The heating wire is disposed between the upper partition portion 1011a and the lower partition portion 1011b of the partition body 1011. The heating wire has good conductivity and heat resistance, enabling rapid and uniform heating. By controlling the current or voltage of the heating wire, the power of the first heating unit 111 can be adjusted, thereby achieving precise temperature control.

[0085] In this embodiment, each of the second heating units 113 includes a heating wire. The heating wire is disposed inside the wafer carrier disk 1031 and has good conductivity and heat resistance, enabling rapid and uniform heating. By controlling the current or voltage of the heating wire, the power of the second heating unit 113 can be adjusted, thereby achieving precise temperature control.

[0086] In this embodiment, the temperature sensor 112 can be in the form of a thermocouple, a thermistor, or similar. The temperature sensor 112 is connected to an external control system via wires. The temperature sensor 112 is positioned in the connection space 101a and can monitor the temperature within the connection space 101a (e.g., near the first heating unit 111 and the second heating unit 113) in real time, feeding the temperature signal back to the control system. Based on the temperature signal, the control system adjusts the power of the first heating unit 111 and the second heating unit 113 to achieve closed-loop temperature control of the process chamber 102, thereby ensuring the temperature stability of the process chamber 102 and improving the wafer baking effect and quality.

[0087] In this embodiment, the cavity 100 includes two process chambers 102, namely an upper chamber 102a (e.g., ...). Figure 3 (as shown) and lower chamber 102b (as shown) Figure 4 (As shown). The wafer baking chamber includes: an upper gate valve 108, disposed at the wafer transfer port of the upper chamber 102a, for opening or closing the wafer transfer port; and a lower gate valve 109, disposed at the wafer transfer port of the lower chamber 102b, for opening or closing the wafer transfer port.

[0088] The upper chamber 102a and the lower chamber 102b are respectively equipped with the upper gate valve 108 and the lower gate valve 109. The independent gate valve design enables the upper chamber 102a and the lower chamber 102b to achieve a time-differential alternating wafer transfer working mode. Therefore, it can ensure the continuity and stability of the production process, which greatly improves the production efficiency of semiconductor equipment, helps to reduce production costs and improve equipment utilization.

[0089] This invention also provides a semiconductor device, including the wafer baking chamber.

[0090] The semiconductor equipment provided in this embodiment includes the wafer baking chamber. Because the wafer baking chamber 100 has multiple stacked process chambers 102, the semiconductor equipment can achieve higher wafer processing throughput within a limited floor area, effectively improving the utilization rate of production space.

[0091] Furthermore, the internal wiring management of this semiconductor device has been optimized. The connection space 101a and wiring channel 101b formed by the partition structure 101, cover structure 104 and groove structure 1012 in the wafer baking chamber provide a regular and centralized arrangement path for the first connecting line connected to the second heating unit 113 of the base 103 and the second connecting line connected to the first heating unit 111 of the partition structure 101. This avoids interference or safety hazards that may be caused by messy internal wiring of the semiconductor device, and improves the reliability and maintainability of the device.

[0092] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0093] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A wafer baking chamber, characterized in that, include: Cavity, including internal space; One or more partition structures are disposed in a cavity to divide the internal space of the cavity into multiple process chambers stacked in a vertical direction. The partition structure includes: a partition body; and multiple groove structures spaced apart on the top of the partition body along a first direction. A cover plate structure is disposed on the groove structure, and the cover plate structure and the groove structure at least enclose a connecting space and a wiring channel communicating with the connecting space; A base, located in the process chamber, is used to support the wafer, and the bottom of the base in the upper process chamber of the adjacent process chamber is in communication with the connecting space; A connection unit, disposed in the connection space and wiring channel, includes a first connection line and a second connection line, the first connection line being led out from the bottom of the base and the second connection line being led out from the partition structure.

2. The wafer baking chamber as described in claim 1, characterized in that, The partition structure also includes: The cabling channel exit is located at the bottom of the cabling channel, away from the connection space; The cavity further includes a cavity wire hole, located below the wiring channel outlet and corresponding to the wiring channel outlet, the cavity wire hole penetrating through the side wall of the cavity below in the height direction.

3. The wafer baking chamber as described in claim 1 or 2, characterized in that, The lower process chamber has one side wall in the second direction, which is located inside the corresponding side wall of the upper process chamber in the second direction, and the second direction is perpendicular to the first direction.

4. The wafer baking chamber as described in claim 1, characterized in that, The groove structure includes: The first groove is located on the top of the partition body, and the bottom surface of the first groove abuts against the cover plate structure; The second groove is located in a portion of the bottom surface of the first groove; The third groove is located in a portion of the bottom surface of the second groove.

5. The wafer baking chamber as described in claim 4, characterized in that, The first groove includes a main groove area and a side groove area located on one side of the main groove area, and the side groove area and the main groove area are connected. The second groove includes a lead transition area and a wiring area located on one side of the lead transition area, wherein the lead transition area is located at the bottom of the main groove area and the wiring area is located at the bottom of the side groove area; The third groove is located at the bottom of the lead transition area.

6. The wafer baking chamber as described in claim 4, characterized in that, The cover plate structure includes: a plate body and a through hole located on the plate body, and the through hole is located directly above the third groove.

7. The wafer baking chamber as described in claim 6, characterized in that, The base is disposed on the cover plate structure, and the base includes: Wafer carrier disk; A support portion, located at the bottom of the wafer carrier disk, has a line channel communicating with the through hole.

8. The wafer baking chamber as described in claim 6, characterized in that, The plate body includes: The first part is located at the top of the connecting space, and the first part is provided with the through hole; The second part is located on one side of the first part and connected to the first part, and the second part is located at the top of the wiring channel; The cover plate structure further includes a strip groove, which is disposed on the second part facing the wiring channel, and the strip groove is connected to the connection space and the wiring channel.

9. The wafer baking chamber as described in claim 8, characterized in that, The cover plate structure also includes: A sealing groove is located on the side of the cover plate structure facing the groove structure, and the sealing groove is located around the through hole and the strip groove; A sealing ring is disposed in the sealing groove.

10. The wafer baking chamber as described in claim 1, characterized in that, The wafer baking chamber also includes: A first heating unit is disposed inside the partition body for heating the partition structure, and the first heating unit is connected to the second connecting line; A second heating unit is disposed inside the base for heating the base, and the second heating unit is connected to the first connecting line.

11. The wafer baking chamber as described in claim 10, characterized in that, At least one of the first heating unit and the second heating unit includes a connecting end, which is disposed in the connecting space; A temperature sensor is disposed in the connection space and spaced apart from the connection end.

12. The wafer baking chamber as described in claim 10, characterized in that, Both the first heating unit and the second heating unit include a heating wire.

13. The wafer baking chamber as described in claim 1, characterized in that, The wafer baking chamber further includes an air inlet, which communicates with the process chamber and is located on one side of the process chamber in a second direction, the second direction being perpendicular to the first direction; An exhaust port is connected to the process chamber and is located on the other side of the process chamber in the second direction; The groove structure is positioned close to the air extraction port in the second direction.

14. The wafer baking chamber as described in claim 13, characterized in that, The groove structure extends along the second direction, and one end of the groove structure in the second direction is an open end, which is connected to the side wall of the partition body in the second direction.

15. A semiconductor device, characterized in that, include: The wafer baking chamber as described in any one of claims 1 to 14.

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