Semiconductor device, circuit board assembly, electric control box and electric appliance

Abstract

The utility model discloses a kind of semiconductor device, circuit board assembly, electric control box and electrical equipment, semiconductor device has horizontal direction and longitudinal direction, horizontal direction and longitudinal direction are perpendicular to each other, semiconductor device includes: plastic package body;Substrate, substrate is set in plastic package body, substrate includes first inverter power pad portion, second inverter power pad portion and PFC (power factor correction) power pad portion that are arranged at interval in horizontal direction;Drive side pin frame, drive side pin frame includes first inverter drive pin frame, second inverter drive pin frame and PFC drive pin frame arranged at interval in horizontal direction, first inverter drive pin frame, second inverter drive pin frame and PFC drive pin frame are respectively provided with first inverter drive chip, second inverter drive chip and PFC drive chip.Wherein, at least two of first inverter drive chip, second inverter drive chip and PFC drive chip are integrated chip, reduce the number of parts, reduce semiconductor device production difficulty.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device, circuit board assembly, electrical control box, and electrical equipment. Background Technology

[0002] Electronic control boards for equipment such as air conditioners and washing machines can be equipped with semiconductor devices such as intelligent power modules. For example, an air conditioner electronic control board may include independently packaged devices such as rectifier bridges, PFC (Power Factor Correction), compressor IPM (Intelligent Power Module), and fan IPM. Each part has a large number of driver chips. These discrete devices occupy a large area on the electronic control board and require multiple insertions during production, making assembly difficult. Utility Model Content

[0003] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a semiconductor device in which at least two of the first inverter driver chip, the second inverter driver chip, and the PFC driver chip are integrated into a single chip, reducing the number of components and lowering the manufacturing difficulty of the semiconductor device.

[0004] Another object of the present invention is to provide a circuit board assembly.

[0005] Another object of the present invention is to provide an electrical control box.

[0006] Another object of the present invention is to provide an electrical device.

[0007] According to an embodiment of the present invention, a semiconductor device has a horizontal direction and a vertical direction, the horizontal direction and the vertical direction being perpendicular to each other. The semiconductor device includes: a molding compound; a substrate, the substrate being at least partially disposed within the molding compound, the substrate including a first inverter power pad portion, a second inverter power pad portion, and a PFC (Power Factor Correction) power pad portion spaced apart horizontally, the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion respectively having a first inverter power chip, a second inverter power chip, and a PFC power chip disposed thereon; and a driver-side pin frame, the driver-side pin frame being at least partially disposed within the molding compound and spaced apart on one side of the vertical direction of the substrate, the driver-side pin frame extending at least partially from the molding compound and including a first inverter driver pin frame, a second inverter driver pin frame, and a PFC driver pin frame spaced apart horizontally. The system comprises a dynamic pin frame, wherein the first inverter drive pin frame and the first inverter power pad portion are at least partially vertically aligned, the second inverter drive pin frame and the second inverter power pad portion are at least partially vertically aligned, and the PFC power pad portion is at least partially vertically aligned with the PFC drive pin frame; a first inverter drive chip, a second inverter drive chip, and a PFC drive chip are respectively disposed on the first inverter drive pin frame, the second inverter drive pin frame, and the PFC drive pin frame, the first inverter drive chip being electrically connected to the first inverter power chip, the second inverter drive chip being electrically connected to the second inverter power chip, and the PFC drive chip being electrically connected to the PFC power chip; wherein at least two of the first inverter drive chip, the second inverter drive chip, and the PFC drive chip constitute an integrated chip.

[0008] According to the semiconductor device of the present invention, at least two of the first inverter driver chip, the second inverter driver chip, and the PFC driver chip are integrated into one chip, reducing the number of components and lowering the difficulty of semiconductor device manufacturing.

[0009] According to some embodiments of the present invention, the first inverter driver chip, the second inverter driver chip, and the PFC driver chip are integrated into a single chip.

[0010] According to some embodiments of the present invention, the first inverter driver chip and the PFC driver chip are integrated into one chip; or, the second inverter driver chip and the PFC driver chip are integrated into one chip; or, the first inverter driver chip and the second inverter driver chip are integrated into one chip.

[0011] According to some embodiments of the present invention, the substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion. A rectifier chip is disposed on the rectifier bridge pad portion. The drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially corresponding to the rectifier bridge pad portion in the longitudinal direction. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion.

[0012] According to some embodiments of the present invention, the lateral direction includes a first direction and a second direction, wherein the first direction and the second direction are arranged in opposite directions; wherein, the first inverter power pad, the second inverter power pad, the PFC power pad, and the rectifier bridge pad are arranged sequentially in the first direction; or, the rectifier bridge pad, the first inverter power pad, the second inverter power pad, and the PFC power pad are arranged sequentially in the first direction; or, the first inverter power pad, the second inverter power pad, the rectifier bridge pad, and the PFC power pad are arranged sequentially in the first direction; or, the first inverter power pad, the rectifier bridge pad, the second inverter power pad, and the PFC power pad are arranged sequentially in the first direction.

[0013] According to some embodiments of the present invention, the first inverter power pad portion has a dimension L1 in the lateral direction, the second inverter power pad portion has a dimension L2 in the lateral direction, and the sum of the dimensions of the rectifier bridge pad portion and the PFC power pad portion in the lateral direction is L3; wherein, L1, L2 and L3 satisfy the relationship: L2+L3≥2*L1.

[0014] According to some embodiments of the present invention, the first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion and the PFC power pad portion is L3; wherein, L1, L2 and L3 satisfy the relationship: 1.5*L3≤L1+L2≤2*L3.

[0015] According to some embodiments of the present invention, the first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion and the PFC power pad portion is L3; wherein, L1, L2 and L3 satisfy the relationship: L3 > L1, or L3 > L2.

[0016] According to some embodiments of the present invention, the rectifier bridge pad portion has a lateral dimension of L4, and the PFC power pad portion has a lateral dimension of L5; wherein, L4 and L5 satisfy the relationship: L4 > L5.

[0017] According to some embodiments of the present invention, the first inverter power pad portion has a dimension of L1 in the lateral direction, the second inverter power pad portion has a dimension of L2 in the lateral direction, and the substrate has a dimension of L6 in the lateral direction.

[0018] Among them, L1, L2 and L6 satisfy the relationship: 0.58≤(L1+L2) / L6≤0.65.

[0019] The circuit board assembly according to a second aspect of the present invention includes the semiconductor device described above.

[0020] The electrical control box according to a third aspect of the present invention includes the circuit board assembly described above.

[0021] The electrical device according to a fourth aspect of the present invention includes: the electrical control box described above.

[0022] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0024] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0025] Figure 2 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 ;

[0026] Figure 3 This is a schematic diagram of the substrate structure according to an embodiment of the present utility model;

[0027] Figure 4 This is a schematic diagram showing the various driver chips arranged on the frame according to an embodiment of the present utility model;

[0028] Figure 5 This is a schematic diagram of the integrated chip arranged on the frame according to an embodiment of the present utility model. Figure 1 ;

[0029] Figure 6 This is a schematic diagram of the integrated chip arranged on the frame according to an embodiment of the present utility model. Figure 2 ;

[0030] Figure 7 This is a schematic diagram of the integrated chip arranged on the frame according to an embodiment of the present utility model. Figure 3 ;

[0031] Figure 8 This is a schematic diagram of the integrated chip arranged on the frame according to an embodiment of the present utility model. Figure 4 .

[0032] Figure label:

[0033] 100. Semiconductor devices;

[0034] 1. Plastic encapsulation;

[0035] 2. Substrate; 201. First inverter power pad; 202. Second inverter power pad; 203. PFC power pad; 204. Rectifier bridge pad;

[0036] 3. Driver-side pin frame;

[0037] 301, First inverter drive pin frame; 3011, First inverter drive chip;

[0038] 302. Second inverter drive pin frame; 3021. Second inverter drive chip;

[0039] 303, PFC driver pin frame; 3031, PFC driver chip;

[0040] 304, Rectifier bridge driver pin frame;

[0041] 305. Integrated chip. Detailed Implementation

[0042] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0043] The following is for reference. Figures 1-8 A semiconductor device 100 according to an embodiment of the present invention is described.

[0044] Reference Figure 1 and Figure 2 As shown, the semiconductor device 100 of this utility model embodiment has a horizontal and a vertical direction, which are perpendicular to each other. The semiconductor device 100 includes: a molding compound 1, a substrate 2, and a drive-side pin frame 3.

[0045] In this design, the substrate 2 is at least partially disposed within the molding compound 1, and the drive-side pin frame 3 is at least partially disposed within the molding compound 1. This protects the structural stability of multiple devices in the semiconductor device 100, thereby ensuring the functional reliability of the semiconductor device 100. The substrate 2 can be completely encapsulated by the molding compound 11, or it can be partially encapsulated by the molding compound 1 and partially exposed on the surface of the molding compound 1. The drive-side pin frame 3 is at least partially disposed within the molding compound 1, and partially extends out of the molding compound 1 to connect to external components. The molding compound 1 protects the stability of the substrate 2 and the drive-side pin frame 3 within the semiconductor device 100 and provides electrical insulation from the outside, thereby ensuring the structural reliability of the semiconductor device 100.

[0046] Furthermore, the substrate 2 includes a first inverter power pad portion 201, a second inverter power pad portion 202, and a PFC (power factor correction) power pad portion arranged laterally at intervals. This ensures that the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203 are arranged relatively independently on the substrate 2. The first inverter power pad portion 201 is provided with a first inverter power chip, the second inverter power pad portion 202 is provided with a second inverter power chip, and the PFC power pad portion 203 is provided with a PFC power chip.

[0047] In this embodiment of the utility model, the power chip includes: a first inverter power chip, a second inverter power chip, and a PFC power chip.

[0048] An inverter circuit can be composed of multiple power chips; for example, a three-phase inverter bridge circuit can be composed of six power chips. The three-phase inverter bridge circuit includes three upper-arm inverter power chips and three lower-arm inverter power chips. The power chips can be composed of insulated-gate bipolar transistors (IGBTs) and freewheeling diodes (FRDs); alternatively, the power chips can be metal-oxide-semiconductor field-effect transistors (MOS); or, the power chips can be RC-IGBTs (reverse-conducting IGBTs that integrate the IGBT and freewheeling diode onto a single chip).

[0049] A PFC power chip includes a PFC power switch chip and a PFC diode. The PFC power switch and PFC diode are components of the PFC circuit, which adjusts the power factor of DC power and outputs the adjusted DC power. The PFC power switch chip can be composed of an insulated-gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT (a reverse-conducting IGBT that integrates the IGBT and freewheeling diode onto a single chip).

[0050] like Figure 1and Figure 2 As shown, the drive-side pin frame 3 is spaced apart on one side of the longitudinal direction of the substrate 2, so that the drive-side pin frame 3 can be arranged adjacent to the substrate 2 to facilitate the electrical connection between the drive-side pin frame 3 and the substrate 2.

[0051] The drive-side pin frame 3 includes a first inverter drive pin frame 301, a second inverter drive pin frame 302, and a PFC drive pin frame 303, which are spaced apart laterally. The first inverter drive pin frame 301 corresponds at least partially to the first inverter power pad portion 201 in the vertical direction, which facilitates the electrical connection between the first inverter drive pin frame 301 and the first inverter power chip on the first inverter power pad portion 201.

[0052] The second inverter drive pin frame 302 and the second inverter power pad portion 202 are at least partially corresponding in the longitudinal direction, which facilitates the electrical connection between the second inverter drive pin frame 302 and the second inverter power chip on the second inverter power pad portion 202. The PFC power pad portion 203 is at least partially corresponding in the longitudinal direction to the PFC drive pin frame 303, which facilitates the electrical connection between the PFC drive pin frame 303 and the PFC power chip on the PFC power pad portion 203.

[0053] The driver chips include: a first inverter driver chip 3011, a second inverter driver chip 3021, and a PFC driver chip 3031.

[0054] Furthermore, a first inverter driver chip 3011, a second inverter driver chip 3021, and a PFC driver chip 3031 are respectively disposed on the first inverter driver pin frame 301, the second inverter driver pin frame 302, and the PFC driver pin frame 303. The first inverter driver chip 3011 is electrically connected to the first inverter power chip, enabling the first inverter driver chip 3011 to drive the first inverter power chip to operate normally. The second inverter driver chip 3021 is electrically connected to the second inverter power chip, enabling the second inverter driver chip 3021 to drive the second inverter power chip to operate normally. The PFC driver chip 3031 is electrically connected to the PFC power chip, enabling the PFC driver chip 3031 to drive the PFC power chip to operate normally.

[0055] In this embodiment of the present invention, the drive-side pin frame 3 can be completely spaced apart from the substrate 2 in the second direction, thereby reducing the impact of heat transferred from the substrate 2 on the drive chip (including the first inverter drive chip 3011, the second inverter drive chip 3021 and the PFC drive chip 3031); the drive-side pin frame 3 can also be partially protruding in the second direction to form a connecting rod and connect with the substrate 2, thereby improving the stability of the substrate 2. At the same time, most of the drive-side pin frame 3 is spaced apart from the substrate 2 in the second direction, thereby balancing the improvement of the stability of the substrate 2 and the reduction of the impact of heat transferred from the substrate 2 on the drive chip.

[0056] In this design, at least two of the first inverter driver chip 3011, the second inverter driver chip 3021, and the PFC driver chip 3031 are integrated into a single chip 305. Multiple designs are possible.

[0057] Design 1:

[0058] like Figure 5 As shown, the first inverter driver chip 3011, the second inverter driver chip 3021, and the PFC driver chip 3031 are integrated into a single chip, reducing the number of chips on the semiconductor device 100, lowering the design complexity of the semiconductor device 100, and reducing the difficulty of device manufacturing. With this configuration, the positions of the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203 on the substrate 2 can be arbitrarily adjusted without restriction, improving the design flexibility of the semiconductor device 100.

[0059] Design 2:

[0060] according to Figure 6 As shown, the first inverter driver chip 3011 and the second inverter driver chip 3021 are combined into an integrated chip 305, while the PFC driver chip 3031 is set separately. The integrated chip 305 and the PFC driver chip 3031 are arranged laterally on the substrate 2. Originally, there were three driver chips. By combining the first inverter driver chip 3011 and the second inverter driver chip 3021 into an integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby reducing the design difficulty of the semiconductor device 100 and the device manufacturing difficulty. With this arrangement, the first inverter power pad portion 201 and the second inverter power pad portion 202 on the substrate 2 are arranged adjacent to each other. The PFC power pad portion 203 can be located on the side of the first inverter power pad portion 201 away from the second inverter power pad portion 202 or on the side of the second inverter power pad portion 202 away from the first inverter power pad portion 201, thereby improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0061] Design 3:

[0062] like Figure 7 As shown, the second inverter driver chip 3021 and the PFC driver chip 3031 are combined into a single integrated chip 305, while the first inverter driver chip 3011 is disposed separately. The integrated chip 305 and the first inverter driver chip 3011 are arranged laterally on the substrate 2. Originally, there were three driver chips. By combining the second inverter driver chip 3021 and the PFC driver chip 3031 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby lowering the design complexity and manufacturing complexity of the semiconductor device 100. With this arrangement, the second inverter power pad portion 202 and the PFC power pad portion 203 on the substrate 2 are arranged adjacent to each other. The first inverter power pad portion 201 can be located on the side of the second inverter power pad portion 202 away from the PFC power pad portion 203, or the PFC power pad portion 203 can be located on the side of the second inverter power pad portion 202 away from the PFC power pad portion 203, thus improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0063] Design 4:

[0064] like Figure 8 As shown, the first inverter driver chip 3011 and the PFC driver chip 3031 are combined into a single integrated chip 305, while the second inverter driver chip 3021 is disposed separately. The integrated chip 305 and the second inverter driver chip 3021 are arranged laterally on the substrate 2. Originally, there were three driver chips. By combining the first inverter driver chip 3011 and the PFC driver chip 3031 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thus lowering the design complexity and manufacturing difficulty of the semiconductor device 100. With this arrangement, the first inverter power pad portion 201 and the PFC power pad portion 203 on the substrate 2 are arranged adjacent to each other. The second inverter power pad portion 202 can be located on the side of the first inverter power pad portion 201 away from the PFC power pad portion 203 or on the side of the PFC power pad portion 203 away from the first inverter power pad portion 201, improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0065] This setup simplifies the design of the driver chip on the frame, reduces the design difficulty of the semiconductor device 100, and reduces the number of chips on the semiconductor device 100, thereby reducing the difficulty of device manufacturing.

[0066] Combination Figures 1-8 As shown, the substrate 2 also includes a rectifier bridge pad portion 204, which is laterally spaced from the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203. A rectifier chip is disposed on the rectifier bridge pad portion 204. This arrangement ensures that the rectifier bridge pad portion 204, the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203 are independently disposed on the semiconductor device 100. This reduces electromagnetic interference among the rectifier bridge pad portion 204, the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203, thereby improving the anti-interference capability of the semiconductor device 100.

[0067] In some embodiments, multiple rectifier chips can form a rectifier bridge. For example, the rectifier chips can be rectifier diodes, which are combined by four spaced rectifier diodes. The rectifier bridge composed of four rectifier diodes converts the input AC power into DC power and outputs it.

[0068] The pads on the substrate 2 include: a first inverter power pad 201, a second inverter power pad 202, a PFC power pad 203, and a rectifier bridge pad 204.

[0069] In some embodiments of this utility model, the substrate 2 may include pads and an insulating heat dissipation layer disposed below the pads. The insulating heat dissipation layer is mainly formed by sequentially stacking an insulating resin sheet and a copper layer, or by sequentially stacking an insulating resin sheet and an aluminum layer. The main material of the pads is copper or aluminum. In this case, most of the substrate 2 is wrapped by the encapsulator 1, and the outer surface of the copper layer or the outer surface of the aluminum layer in the insulating heat dissipation layer of the substrate 2 is exposed from the outer surface of the encapsulator 1. Alternatively, substrate 2 may include pads, an insulating layer, and a heat dissipation layer stacked sequentially. The pads are primarily made of copper or aluminum, the insulating layer is primarily made of AlN, Al2O3, Si3N4, or a combination of these materials, and the heat dissipation layer is primarily made of copper or aluminum. In this case, substrate 2 is mostly encapsulated by the molding compound 1, and the outer surface of the heat dissipation layer is exposed from the outer surface of the molding compound 1. Alternatively, substrate 2 may include pads and an insulating layer disposed below the pads. The insulating layer is primarily made of AlN, Al2O3, or Si3N4 ceramic insulating layer. In this case, substrate 2 is mostly encapsulated by the molding compound 1, and the outer surface of the insulating layer is exposed from the outer surface of the molding compound 1. Alternatively, substrate 2 may be formed solely of pads. In this case, substrate 2 is disposed within the molding compound 1, and the molding compound 1 completely encapsulates substrate 2. The specific structural form of substrate 2 can be adjusted according to the specific requirements and application environment of the semiconductor device 100.

[0070] The driver-side pin frame 3 also includes a rectifier bridge driver pin frame 304, which corresponds at least partially to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge driver pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. This ensures the structural integrity of the semiconductor device 100 and guarantees the normal function of the rectifier module.

[0071] In this embodiment of the invention, the frame can be a PCB. The PCB has pads near the power side that are electrically connected to the driver chips. Each power chip is electrically connected to the pads via wires. The driver-side pin frame 3 has a substrate that is conventional for printed circuit boards (PCBs), such as FR1 to FR5, among which FR4 and FR5 (both are glass fiber reinforced epoxy resins) are commonly used. The first inverter driver pin frame 301, the second inverter driver pin frame 302, and the PFC driver pin frame 303 are designed adjacent to each other on the PCB, and their order can be arbitrarily adjusted. The rectifier bridge driver pin frame 304 is located on one side of the end.

[0072] In this way, the rectifier bridge, PFC, second inverter intelligent module and first inverter intelligent module can be integrated on the semiconductor device 100. Compared with setting multiple independent components, this can reduce the size of the semiconductor device 100, and there is no need for multiple insertions during production. This makes the structure of the semiconductor device 100 simpler and more compact, and makes the production of the semiconductor device 100 simpler.

[0073] In some embodiments of the present invention, one of the first inverter intelligent module and the second inverter intelligent module is a fan intelligent module and the other is a compressor intelligent module.

[0074] In other embodiments of the present invention, both the first inverter intelligent module and the second inverter intelligent module are motor intelligent modules. No specific limitations are imposed here.

[0075] The rectifier chip can be disposed between the first inverter driver chip 3011, the second inverter driver chip 3021 and the PFC driver chip 3031, or the rectifier chip can be disposed at the end of the substrate 2.

[0076] For example, if the first inverter driver chip 3011, the second inverter driver chip 3021 and the PFC driver chip 3031 are integrated into a single integrated chip 305, then the rectifier chip can be disposed on one side or the other side of the horizontal direction of the integrated chip 305.

[0077] For example, the first inverter driver chip 3011 and the second inverter driver chip 3021 are integrated into a single integrated chip 305. The rectifier chip can be disposed between the integrated chip 305 and the PFC driver chip 3031, or on the side of the PFC driver chip 3031 away from the integrated chip 305, or on the side of the integrated chip 305 away from the PFC driver chip 3031.

[0078] For example, the first inverter driver chip 3011 and the PFC driver chip 3031 are integrated into a single chip 305. The rectifier chip can be disposed between the integrated chip 305 and the second inverter driver chip 3021, or on the side of the second inverter driver chip 3021 away from the integrated chip 305, or on the side of the integrated chip 305 away from the second inverter driver chip 3021.

[0079] For example, the second inverter driver chip 3021 and the PFC driver chip 3031 are integrated into a single chip 305. The rectifier chip can be disposed between the integrated chip 305 and the first inverter driver chip 3011, or on the side of the first inverter driver chip 3011 away from the integrated chip 305, or on the side of the integrated chip 305 away from the first inverter driver chip 3011.

[0080] According to some embodiments of the present invention, the lateral direction includes a first direction and a second direction, which are arranged in opposite directions.

[0081] In some embodiments, the first inverter power pad portion 201, the second inverter power pad portion 202, the PFC power pad portion 203, and the rectifier bridge pad portion 204 are arranged sequentially in a first direction. In this case, three designs are available:

[0082] Design 1:

[0083] like Figure 6As shown, the first inverter driver chip 3011 and the second inverter driver chip 3021 are integrated into a single integrated chip 305, while the PFC driver chip 3031 is disposed separately. The integrated chip 305, the PFC driver chip 3031, and the rectifier chip are arranged sequentially in the first direction. By integrating the first inverter driver chip 3011 and the second inverter driver chip 3021 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby lowering the design complexity and manufacturing complexity of the semiconductor device 100. The PFC driver chip 3031 is located on one side of the second inverter driver chip 3021 in the first direction, and the rectifier chip is also located on one side of the PFC driver chip 3031 in the first direction. With this configuration, the first inverter power pad 201, the second inverter power pad 202, the PFC power pad 203, and the rectifier bridge pad 204 on the substrate 2 are arranged sequentially along the first direction. The first inverter power pad 201 can be located on the side of the second inverter power pad 202 opposite to the PFC power pad 203, improving the design flexibility of the semiconductor device 100. To a certain extent, this increases the distance between the driver chips, reduces the thermal impact between them, results in a more reasonable layout, and improves the integration of the semiconductor device 100.

[0084] Design 2:

[0085] like Figure 7 As shown, the second inverter driver chip 3021 and the PFC driver chip 3031 can be integrated into a single integrated chip 305, while the first inverter driver chip 3011 is disposed separately. The first inverter driver chip 3011, the integrated chip 305, and the rectifier chip are arranged sequentially in the first direction. By integrating the second inverter driver chip 3021 and the PFC driver chip 3031 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby lowering the design complexity and manufacturing complexity of the semiconductor device 100. The first inverter driver chip 3011 is located on one side of the second inverter driver chip 3021 in the second direction, and the rectifier chip is located on one side of the PFC driver chip 3031 in the first direction. With this arrangement, the second inverter power pad portion 202 and the PFC power pad portion 203 on the substrate 2 are arranged adjacent to each other, and the first inverter power pad portion 201 can be located on the side of the second inverter power pad portion 202 away from the PFC power pad portion 203, improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0086] Design 3:

[0087] like Figure 5As shown, the first inverter driver chip 3011, the second inverter driver chip 3021, and the PFC driver chip 3031 can be integrated into a single integrated chip 305. The integrated chip 305 and the rectifier chip are arranged sequentially in the first direction. Furthermore, the first inverter driver chip 3011, the second inverter driver chip 3021, and the PFC driver chip 3031 are arranged sequentially along the first direction, with the rectifier chip located on the side of the PFC driver chip 3031 facing away from the second inverter driver chip 3021. Then, the first inverter power pad portion 201, the second inverter power pad portion 202, the PFC power pad portion 203, and the rectifier bridge pad portion 204 are arranged sequentially in the first direction. This reduces the number of chips on the semiconductor device 100, lowers the design complexity of the semiconductor device 100, and reduces the difficulty of device manufacturing.

[0088] In other embodiments, the rectifier bridge pad 204, the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203 are arranged sequentially in the first direction. In this case, three designs are available:

[0089] Design 1: The first inverter driver chip 3011 and the second inverter driver chip 3021 are integrated into a single integrated chip 305, while the PFC driver chip 3031 is disposed separately. The rectifier chip, integrated chip 305, and PFC driver chip 3031 are arranged sequentially in the first direction. By integrating the first inverter driver chip 3011 and the second inverter driver chip 3021 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby lowering the design complexity and manufacturing difficulty of the semiconductor device 100. The PFC driver chip 3031 is located on one side of the integrated chip 305 in the first direction, and the rectifier chip is located on one side of the integrated chip 305 in the second direction. With this arrangement, the rectifier bridge pad 204, the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203 on the substrate 2 are arranged sequentially along the first direction, improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0090] Design 2: The second inverter driver chip 3021 and the PFC driver chip 3031 can be integrated into a single integrated chip 305, while the first inverter driver chip 3011 is set separately. The first inverter driver chip 3011, the integrated chip 305, and the rectifier chip are arranged sequentially in the first direction. By integrating the second inverter driver chip 3021 and the PFC driver chip 3031 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thus lowering the design complexity and manufacturing difficulty of the semiconductor device 100. The first inverter driver chip 3011 is located on one side of the integrated chip 305 in the second direction, and the rectifier chip is located on one side of the first inverter driver chip 3011 in the second direction. With this arrangement, the second inverter power pad portion 202 and the PFC power pad portion 203 on the substrate 2 are arranged adjacent to each other. The first inverter power pad portion 201 can be located on the side of the second inverter power pad portion 202 away from the PFC power pad portion 203, improving the design flexibility of the semiconductor device 100. To a certain extent, increasing the distance between each driver chip reduces the thermal impact between them, resulting in a more reasonable layout and improved integration of the semiconductor device 100.

[0091] Design 3: The first inverter driver chip 3011, the second inverter driver chip 3021, and the PFC driver chip 3031 can be integrated into a single integrated chip 305. The integrated chip 305 and the rectifier chip are arranged sequentially in the first direction. The rectifier chip is located on one side of the integrated chip 305 in the second direction. The first inverter power pad 201, the second inverter power pad 202, the PFC power pad 203, and the rectifier bridge pad 204 are then arranged sequentially in the first direction. This reduces the number of chips on the semiconductor device 100, lowers the design complexity of the semiconductor device 100, and reduces the difficulty of device manufacturing.

[0092] Alternatively, the first inverter power pad section 201, the second inverter power pad section 202, the rectifier bridge pad section 204, and the PFC power pad section 203 are arranged sequentially in the first direction. Specifically, the first inverter driver chip 3011 and the second inverter driver chip 3021 are integrated into a single integrated chip 305, while the PFC driver chip 3031 is disposed separately. The integrated chip 305, the rectifier chip, and the PFC driver chip 3031 are arranged sequentially in the first direction. By integrating the first inverter driver chip 3011 and the second inverter driver chip 3021 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby reducing the design difficulty of the semiconductor device 100 and the difficulty of device manufacturing. The rectifier chip is located on one side of the integrated chip 305 in the first direction, and the PFC driver chip 3031 is located on one side of the rectifier chip in the first direction. With this configuration, the first inverter power pad 201, the second inverter power pad 202, the rectifier bridge pad 204, and the PFC power pad 203 on the substrate 2 are arranged sequentially along the first direction, improving the design flexibility of the semiconductor device 100. To a certain extent, this increases the distance between the driving chips, reduces the thermal impact between them, results in a more reasonable layout, and improves the integration of the semiconductor device 100.

[0093] In some embodiments, the first inverter power pad portion 201, the rectifier bridge pad portion 204, the second inverter power pad portion 202, and the PFC power pad portion 203 are arranged sequentially in the first direction. Specifically, the second inverter driver chip 3021 and the PFC driver chip 3031 can be integrated into a single integrated chip 305, while the first inverter driver chip 3011 is disposed separately. The first inverter driver chip 3011, the rectifier chip, and the integrated chip 305 are arranged sequentially in the first direction. By integrating the second inverter driver chip 3021 and the PFC driver chip 3031 into a single integrated chip 305, the number of chips on the semiconductor device 100 is reduced, thereby reducing the design difficulty of the semiconductor device 100 and the manufacturing difficulty of the device. The rectifier chip is located on one side of the integrated chip 305 in the second direction, and the first inverter driver chip 3011 is located on one side of the rectifier chip in the second direction. With this configuration, the second inverter power pad 202 and the PFC power pad 203 on the substrate 2 are arranged adjacent to each other, and the rectifier bridge pad 204 is located on the side of the second inverter power pad 202 away from the PFC power pad 203. The rectifier bridge pad 204 is disposed between the first inverter power pad 201 and the second inverter power pad 202. To a certain extent, this increases the distance between the driver chips, reduces the thermal impact between them, results in a more reasonable layout, and improves the integration of the semiconductor device 100.

[0094] According to some embodiments of this utility model, the first inverter power pad portion 201 has a lateral dimension of L1, the second inverter power pad portion 202 has a lateral dimension of L2, and the rectifier bridge pad portion 204 and the PFC power pad portion 203 have a lateral dimension of L3. L1, L2, and L3 satisfy the relationship: L2 + L3 ≥ 2 * L1. That is, the sum of the lateral dimensions of the second inverter power pad portion 202, the rectifier bridge pad portion 204, and the PFC power pad portion 203 is greater than or equal to twice the lateral dimension of the first inverter power pad portion 201, ensuring a reasonable layout of the four parts and reducing the thermal impact between the power chips.

[0095] According to some embodiments of the present invention, the first inverter power pad portion 201 has a dimension L1 in the lateral direction, the second inverter power pad portion 202 has a dimension L2 in the lateral direction, and the sum of the dimensions of the rectifier bridge pad portion 204 and the PFC power pad portion 203 in the lateral direction is L3; wherein, L1, L2 and L3 satisfy the relationship: 1.5*L3≤L1+L2≤2*L3. Specifically, the sum of the dimensions of the first inverter power pad portion 201 and the second inverter power pad portion 202 in the lateral direction is between 1.5 and 2 times the sum of the dimensions of the rectifier bridge pad portion 204 and the PFC power pad portion 203 in the lateral direction. The PFC and rectifier bridge are high-temperature operating components. If the area of ​​the rectifier bridge pad portion 204 and the PFC power pad portion 203 is too small, it cannot meet the heat dissipation requirements. If the area of ​​the rectifier bridge pad portion 204 and the PFC power pad portion 203 is too large, it will create ineffective heat dissipation areas and waste space, which is not conducive to miniaturization. Therefore, the rectifier bridge pad portion 204 and the PFC power pad portion 203 are selected with appropriate sizes to meet the heat dissipation requirements while ensuring the miniaturization of the semiconductor device 100.

[0096] according to Figure 3 As shown, the first inverter power pad portion 201 has a lateral dimension of L1, the second inverter power pad portion 202 has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion 204 and the PFC power pad portion 203 is L3; wherein L1, L2, and L3 satisfy the relationship: L3 > L1, or L3 > L2. Specifically, the sum of the lateral dimensions of the rectifier bridge pad portion 204 and the PFC power pad portion 203 must be greater than that of the first inverter power pad portion 201 to avoid the first inverter power pad portion 201 occupying too large a size, which would affect the arrangement of the rectifier bridge pad portion 204 and the PFC power pad portion 203, and ensure a reasonable layout on the semiconductor device 100.

[0097] like Figure 3As shown, the rectifier bridge pad section 204 has a lateral dimension of L4, and the PFC power pad section 203 has a lateral dimension of L5; where L4 and L5 satisfy the relationship: L4 > L5. Since the rectifier bridge requires many chips and needs to be compatible with modules of various current specifications, the lateral dimension of the rectifier bridge pad section 204 is larger than that of the PFC power pad section 203 to ensure the normal functioning of the rectifier bridge.

[0098] according to Figure 3 As shown, the first inverter power pad portion 201 has a lateral dimension of L1, the second inverter power pad portion 202 has a lateral dimension of L2, and the substrate 2 has a lateral dimension of L6. L1, L2, and L6 satisfy the relationship: 0.58 ≤ (L1 + L2) / L6 ≤ 0.65. That is, the sum of the lateral dimensions of the first inverter power pad portion 201 and the second inverter power pad portion 202 accounts for 58%-65% of the substrate 2, ensuring a reasonable layout of the four parts: the second inverter power pad portion 202, the rectifier bridge pad portion 204, the PFC power pad portion 203, and the first inverter power pad portion 201, thereby reducing the thermal impact between the power chips.

[0099] The circuit board assembly according to the present invention includes the semiconductor device 100 described above.

[0100] The electrical control box according to the present invention includes the circuit board assembly described above.

[0101] The electrical device according to the present invention includes: the above-described electrical control box.

[0102] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0104] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a lateral direction and a longitudinal direction, the lateral direction and the longitudinal direction being perpendicular to each other, and the semiconductor device includes: Plastic encapsulation; A substrate, at least partially disposed within the molding compound, the substrate comprising a first inverter power pad portion, a second inverter power pad portion, and a PFC (power factor correction) power pad portion disposed laterally at intervals, wherein a first inverter power chip, a second inverter power chip, and a PFC power chip are respectively disposed on the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion; A drive-side pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame extends at least partially from the molding compound and includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart in the lateral direction. The first inverter drive pin frame corresponds at least partially in the longitudinal direction to a first inverter power pad portion. The second inverter drive pin frame and the second inverter power pad portion correspond at least partially in the longitudinal direction. The PFC power pad portion corresponds at least partially in the longitudinal direction to the PFC drive pin frame. A first inverter driver chip, a second inverter driver chip, and a PFC driver chip are respectively disposed on the first inverter driver pin frame, the second inverter driver pin frame, and the PFC driver pin frame. The first inverter driver chip is electrically connected to the first inverter power chip, the second inverter driver chip is electrically connected to the second inverter power chip, and the PFC driver chip is electrically connected to the PFC power chip. Among them, at least two of the first inverter driver chip, the second inverter driver chip and the PFC driver chip are integrated into one chip.

2. The semiconductor device according to claim 1, characterized in that, The first inverter driver chip, the second inverter driver chip, and the PFC driver chip are integrated into a single chip.

3. The semiconductor device according to claim 1, characterized in that, The first inverter driver chip and the PFC driver chip are integrated into a single chip; or, The second inverter driver chip and the PFC driver chip are integrated into a single chip; or, The first inverter driver chip and the second inverter driver chip are integrated into one chip.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion and the PFC power pad portion, and a rectifier chip is disposed on the rectifier bridge pad portion; The drive-side pin frame also includes a rectifier bridge drive pin frame, which corresponds at least partially in the longitudinal direction to the rectifier bridge pad portion. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion.

5. The semiconductor device according to claim 4, characterized in that, The lateral direction includes a first direction and a second direction, wherein the first direction and the second direction are arranged in opposite directions; wherein... The first inverter power pad, the second inverter power pad, the PFC power pad, and the rectifier bridge pad are arranged sequentially in a first direction; or, The rectifier bridge pads, the first inverter power pads, the second inverter power pads, and the PFC power pads are arranged sequentially in a first direction; or... The first inverter power pad, the second inverter power pad, the rectifier bridge pad, and the PFC power pad are arranged sequentially in a first direction; or, The first inverter power pad, the rectifier bridge pad, the second inverter power pad, and the PFC power pad are arranged sequentially in a first direction.

6. The semiconductor device according to claim 4, characterized in that, The first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion and the PFC power pad portion is L3. Among them, L1, L2 and L3 satisfy the relationship: L2+L3≥2*L1.

7. The semiconductor device according to claim 4, characterized in that, The first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion and the PFC power pad portion is L3. Among them, L1, L2 and L3 satisfy the relationship: 1.5*L3≤L1+L2≤2*L3.

8. The semiconductor device according to claim 4, characterized in that, The first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the sum of the lateral dimensions of the rectifier bridge pad portion and the PFC power pad portion is L3. Among them, L1, L2 and L3 satisfy the following relationship: L3 > L1, or L3 > L2.

9. The semiconductor device according to claim 4, characterized in that, The rectifier bridge pad portion has a lateral dimension of L4, and the PFC power pad portion has a lateral dimension of L5. Among them, L4 and L5 satisfy the relationship: L4 > L5.

10. The semiconductor device according to claim 1, characterized in that, The first inverter power pad portion has a lateral dimension of L1, the second inverter power pad portion has a lateral dimension of L2, and the substrate has a lateral dimension of L6. Among them, L1, L2 and L6 satisfy the relationship: 0.58≤(L1+L2) / L6≤0.

65.

11. A circuit board assembly, characterized in that, include: The semiconductor device according to any one of claims 1-10.

12. An electrical control box, characterized in that, include: The circuit board assembly of claim 11.

13. An electrical appliance, characterized in that, include: The electrical control box as claimed in claim 12.

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