Clamping circuit of power device and VI source board

Abstract

The application relates to the field of circuit design, in particular to a clamping circuit of a power device and a VI source board. The clamping circuit comprises a positive clamping circuit and / or a negative clamping circuit; the positive clamping circuit comprises a first differential amplifier circuit, a positive compensation network and a first biasing circuit; the positive compensation network is connected between the inverting input end and the output end of the first differential amplifier circuit; the first differential amplifier circuit is configured to output the comparison result of a measured output value and a positive clamping set value to the first biasing circuit; the negative clamping circuit comprises a second differential amplifier circuit, a negative compensation network and a second biasing circuit; the negative compensation network is connected between the inverting input end and the output end of the second differential amplifier circuit; and the second differential amplifier circuit is configured to output the comparison result of a measured output value and a negative clamping set value to the second biasing circuit. The clamping circuit arranged outside the power device improves stability and clamping precision.

Description

Technical Field

[0001] This application relates to the field of circuit design, and in particular to a clamping circuit and VI source board for a power supply device. Background Technology

[0002] Chip testing is a crucial step in chip manufacturing. By comparing the actual output with the expected output, the chip's functionality and performance are evaluated and determined. Chip testing typically involves applying an excitation and then detecting the output signal. A VI source board can implement both excitation and detection functions, allowing for the application and detection of an adjustable voltage / current to the chip under test.

[0003] The VI source board integrates power supply devices, which in turn integrate clamping circuitry. This clamping circuitry adjusts the output voltage / current of the power supply device by comparing the voltage at the MEASOUT pin with a clamping voltage threshold set by the internal DAC. However, the internal clamping circuitry is susceptible to instability and oscillations due to temperature drift and process variations. Utility Model Content

[0004] Therefore, it is necessary to provide a clamping circuit and VI source board for a power supply device to address the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application propose a clamping circuit for a power supply device, comprising: a positive clamping circuit and / or a negative clamping circuit; wherein,

[0006] The positive clamping circuit includes a first differential voltage operational amplifier circuit, a positive compensation network, and a first bias circuit; the positive compensation network is connected between the inverting input terminal and the output terminal of the first differential voltage operational amplifier circuit, and is connected to the measured output value of the power supply device; the first differential voltage operational amplifier circuit is configured to output the comparison result of the measured output value and the positive clamping setting value to the first bias circuit; the first bias circuit is connected to the power supply device.

[0007] The negative clamping circuit includes a second differential voltage operational amplifier circuit, a negative compensation network, and a second bias circuit; the negative compensation network is connected between the inverting input terminal and the output terminal of the second differential voltage operational amplifier circuit and is connected to the measured output value of the power supply device; the second differential voltage operational amplifier circuit is configured to output the comparison result of the measured output value and the negative clamping setting value to the second bias circuit; the second bias circuit is connected to the power supply device.

[0008] In some embodiments, the positive compensation network is configured to adjust the resonant frequency of the positive compensation network according to the loop bandwidth of the power supply device; and / or, the negative compensation network is configured to adjust the resonant frequency of the negative compensation network according to the loop bandwidth of the power supply device.

[0009] In some embodiments, the positive compensation network includes resistors R1 and R3, capacitors C1 and C3, and a switching switch SW1. One end of resistor R1 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the first differential voltage operational amplifier circuit. Resistor R3 and capacitor C3 are connected in series between the inverting input terminal of the first differential voltage operational amplifier circuit and the first moving contact of the switching switch SW1. Capacitor C1 is connected between the inverting input terminal of the first differential voltage operational amplifier circuit and the second moving contact of the switching switch SW1. The stationary contact of the switching switch SW1 is connected to the output terminal of the first differential voltage operational amplifier circuit.

[0010] The negative compensation network includes resistors R2 and R4, capacitors C2 and C4, and a switching switch SW2. One end of resistor R2 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the second differential voltage operational amplifier circuit. Resistor R4 and capacitor C4 are connected in series between the inverting input terminal of the second differential voltage operational amplifier circuit and the first moving contact of the switching switch SW2. Capacitor C2 is connected between the inverting input terminal of the second differential voltage operational amplifier circuit and the second moving contact of the switching switch SW2. The stationary contact of the switching switch SW2 is connected to the output terminal of the second differential voltage operational amplifier circuit.

[0011] In some embodiments, the first differential voltage operational amplifier circuit includes a first differential amplifier U1 and a diode D1. The non-inverting input terminal of the first differential amplifier U1 is connected to the positive clamping setting value, the inverting input terminal is connected to the positive compensation network to access the measured output value, and the output terminal is connected to the first bias circuit. The anode of the diode D1 is connected to the output terminal of the first differential amplifier U1, and the cathode is connected to the inverting input terminal of the first differential amplifier U1.

[0012] The second differential voltage operational amplifier circuit includes a second differential amplifier U2 and a diode D2. The non-inverting input terminal of the second differential amplifier U2 is connected to the positive clamping setting value, the inverting input terminal is connected to the negative compensation network to access the measured output value, and the output terminal is connected to the second bias circuit. The anode of the diode D2 is connected to the output terminal of the second differential amplifier U2, and the cathode is connected to the inverting input terminal of the second differential amplifier U2.

[0013] In some embodiments, the first bias circuit includes a resistor R5 and a clamping diode D5; the second bias circuit includes a resistor R6 and a clamping diode D6.

[0014] One end of resistor R5 is connected to the positive power supply AVDD, and the other end of resistor R5 is connected to the negative terminal of clamping diode D5 and the output terminal of the first differential voltage operational amplifier circuit. The positive terminal of clamping diode D5 is connected to the loop compensation output pin COMP of the power supply device and the negative terminal of clamping diode D6. The positive terminal of clamping diode D6 is connected to one end of resistor R6 and the output terminal of the second differential voltage operational amplifier circuit. The other end of resistor R6 is connected to the negative power supply AVSS.

[0015] In some embodiments, a first voltage regulator circuit and / or a second voltage regulator circuit are also included;

[0016] The first voltage regulator circuit is connected between the output terminal of the first differential voltage operational amplifier circuit and the input terminal of the first bias circuit;

[0017] The second voltage regulator circuit is connected between the output terminal of the second differential voltage operational amplifier circuit and the input terminal of the second bias circuit.

[0018] In some embodiments, the first voltage regulator circuit includes a Zener diode D3, the anode of which is connected to the output terminal of the first differential voltage amplifier circuit, and the cathode is connected to the input terminal of the first bias circuit.

[0019] The second voltage regulator circuit includes a Zener diode D4, the negative terminal of which is connected to the output terminal of the second differential voltage amplifier circuit, and the positive terminal is connected to the input terminal of the second bias circuit.

[0020] In some embodiments, the positive clamping circuit further includes a first voltage regulator circuit; the negative clamping circuit further includes a second voltage regulator circuit.

[0021] The positive clamp detection circuit is connected to the first bias circuit and is configured to detect the bias voltage of the first bias circuit and output a positive clamp alarm signal when positive clamping occurs.

[0022] The negative clamp detection circuit is connected to the second bias circuit and is configured to detect the bias voltage of the second bias circuit and output a negative clamp alarm signal when a negative clamp occurs.

[0023] In some embodiments, the positive clamp detection circuit includes a third differential amplifier U3, resistors R7, R9, and R11, diode D7, and diode D8. The inverting and non-inverting inputs of the third differential amplifier U3 are respectively connected to the input and output of the first bias circuit. One end of resistor R7 is connected to the output of the third differential amplifier U3, and the other end of resistor R7 is connected to the cathode of diode D7. The anode of diode D7 is connected to one end of resistor R9 and the cathode of diode D8. The anode of diode D8 is connected to a common ground. One end of resistor R11 is connected to the logic power supply DVDD. The other ends of resistors R9 and R11 together output a positive clamp alarm signal.

[0024] The negative clamp detection circuit includes a fourth differential amplifier U4, resistors R8, R10, and R12, diodes D9 and D10. The inverting and non-inverting inputs of the fourth differential amplifier U4 are connected to the input and output of the second bias circuit, respectively. One end of resistor R8 is connected to the output of the fourth differential amplifier U4, and the other end of resistor R8 is connected to the cathode of diode D9. The anode of diode D9 is connected to one end of resistor R10 and the cathode of diode D10. The anode of diode D10 is connected to a common ground. One end of resistor R12 is connected to the logic power supply DVDD, and the other ends of resistor R12 and resistor R10 together output a negative clamp alarm signal.

[0025] In some embodiments, the circuit further includes a first signal configuration terminal DAC1 and / or a second signal configuration terminal DAC2, wherein the first signal configuration terminal DAC1 is connected to the first differential voltage operational amplifier circuit and provides a positive clamping setting value; and the second signal configuration terminal DAC2 is connected to the second differential voltage operational amplifier circuit and provides a negative clamping setting value.

[0026] Secondly, embodiments of this application propose a VI source board, including a power supply device and a clamping circuit as described in the first aspect connected to the power supply device.

[0027] The clamping circuit and VI source board of the above power supply devices have the following technical effects:

[0028] 1. The clamping circuit, located outside the power supply device, is not easily affected by temperature drift and process deviation, and has high stability and high clamping accuracy.

[0029] 2. The clamping circuit includes a positive clamping circuit and / or a negative clamping circuit. Therefore, at least one of them can be selected according to the output requirements of the power supply device to meet different clamping requirements. Attached Figure Description

[0030] Figure 1A schematic diagram of the clamping circuit of the power supply device in one embodiment provided in this application;

[0031] Figure 2 A schematic diagram of the clamping circuit of the power supply device in another embodiment provided in this application;

[0032] Figure 3 A schematic diagram of the clamping circuit of the power supply device in another embodiment provided in this application;

[0033] Figure 4 A circuit diagram of the clamping circuit of the power supply device in an example embodiment provided in this application.

[0034] Among them, 100 is the positive clamping circuit; 200 is the negative clamping circuit; 300 is the positive clamping detection circuit; 400 is the negative clamping detection circuit; 110 is the first differential voltage operational amplifier circuit; 120 is the positive compensation network; 130 is the first bias circuit; 140 is the first voltage regulator circuit; 210 is the second differential voltage operational amplifier circuit; 220 is the negative compensation network; 230 is the second bias circuit; and 240 is the second voltage regulator circuit. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0036] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0037] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0038] Figure 1 This is a schematic diagram of the clamping circuit of the power supply device in one embodiment of this application. Figure 1 As shown, the clamping circuit of this power supply device includes a positive clamping circuit 100 and / or a negative clamping circuit 200. That is, the clamping circuit can have three configurations: a single positive clamping circuit 100, a single negative clamping circuit 200, or a combination of both. The appropriate configuration can be selected based on the output requirements of the power supply device to meet different clamping needs. The clamping need can be the clamping current requirement of the power supply device's output current.

[0039] The positive clamping circuit 100 includes a first differential voltage operational amplifier circuit 110, a positive compensation network 120, and a first bias circuit 130. The positive compensation network 120 is connected between the inverting input and output terminals of the first differential voltage operational amplifier circuit 110 and is connected to the measured output value of the power supply device. The first differential voltage operational amplifier circuit 110 is configured to compare the measured output value with the positive clamping setting value and output the comparison result to the first bias circuit 130. The first bias circuit 130 is connected to the power supply device. Specifically, the first differential voltage operational amplifier circuit 110 compares the measured output value of the power supply device with the positive clamping setting value and outputs the comparison result to the first bias circuit 130. The positive compensation network 120 is used for loop compensation of the power supply device to improve its loop stability and clamping accuracy. The bias state of the first bias circuit 130 is determined by the comparison result. The power supply device determines whether to adjust its output based on the bias state of the first bias circuit 130, thereby achieving the purpose of positive clamping.

[0040] The negative clamping circuit 200 includes a second differential voltage operational amplifier circuit 210, a negative compensation network 220, and a second bias circuit 230. The negative compensation network 220 is connected between the inverting input and output of the second differential voltage operational amplifier circuit 210 and is connected to the measured output value of the power supply device. The second differential voltage operational amplifier circuit 210 is configured to compare the measured output value with the negative clamping setting value and output the comparison result to the second bias circuit 230. The second bias circuit 230 is connected to the power supply device. Specifically, the second differential voltage operational amplifier circuit 210 compares the measured output value of the power supply device with the negative clamping setting value and outputs the comparison result to the second bias circuit 230. The negative compensation network 220 is used for loop compensation of the power supply device to improve its loop stability and clamping accuracy. The bias state of the second bias circuit 230 is determined by the comparison result. The power supply device determines whether to adjust its output based on the bias state of the second bias circuit 230, thereby achieving the purpose of negative clamping.

[0041] The clamping circuit has a first signal configuration terminal DAC1 and / or a second signal configuration terminal DAC2. The first signal configuration terminal DAC1 is connected to the first differential voltage operational amplifier circuit 110 and provides a positive clamping setting value; the first signal configuration terminal DAC2 is connected to the second differential voltage operational amplifier circuit 210 and provides a negative clamping setting value.

[0042] In this embodiment, the power supply device can be a DPS (Programmable Device Power Supply) chip, which is an integrated power supply chip; it can also be an analog circuit composed of discrete devices. In this embodiment, the clamping circuit located outside the power supply device is less susceptible to temperature drift and process deviations, and its stability is high. In related technologies, the power supply device integrates a clamping circuit inside and uses a fixed compensation network, which cannot suppress overshoot caused by load and may damage the chip under test.

[0043] In this embodiment, the positive compensation network 120 is configured to adjust its resonant frequency according to the loop bandwidth of the power supply device; the negative compensation network 220 is configured to adjust its resonant frequency according to the loop bandwidth of the power supply device.

[0044] The loop bandwidth of the power supply device is affected by the load. In this embodiment, both the positive compensation network 120 and the negative compensation network 220 adjust their resonant frequencies according to the loop bandwidth to match different loads, thereby suppressing overshoot caused by the load, stabilizing the clamping loop bandwidth, stabilizing the output of the power supply device, and improving clamping accuracy.

[0045] Figure 2 This is a schematic diagram of the clamping circuit of the power supply device in another embodiment provided in this application. In order to improve the output voltage range of the power supply device, in this embodiment, the positive clamping circuit 100 further includes a first voltage regulator circuit 140, and the negative clamping circuit 200 further includes a second voltage regulator circuit 240.

[0046] The first voltage regulator circuit 140 is connected between the output terminal of the first differential voltage operational amplifier circuit 110 and the input terminal of the first bias circuit 130; the second voltage regulator circuit 240 is connected between the output terminal of the second differential voltage operational amplifier circuit 210 and the input terminal of the second bias circuit 230.

[0047] In this embodiment, the positive output voltage range of the power supply device can be increased by the first voltage regulator circuit 140, and the negative output voltage range of the power supply device can be increased by the second voltage regulator circuit 240.

[0048] Figure 3 This is a schematic diagram of the clamping circuit of the power supply device in another embodiment provided in this application. The clamping circuit also includes a positive clamping detection circuit 300 and / or a negative clamping detection circuit 400.

[0049] The positive clamp detection circuit 300 is connected to the first bias circuit 130 and is configured to detect the bias voltage of the first bias circuit 130 and output a positive clamp alarm signal when a positive clamp occurs; the negative clamp detection circuit 400 is connected to the second bias circuit 230 and is configured to detect the bias voltage of the second bias circuit 230 and output a negative clamp alarm signal when a negative clamp occurs.

[0050] In this embodiment, positive clamping detection circuit 300 is used to detect and alarm the occurrence of positive clamping, and / or negative clamping detection circuit 400 is used to detect and alarm the occurrence of negative clamping.

[0051] Figure 4 A circuit diagram of a clamping circuit for a power supply device in an example embodiment provided in this application is shown below. Figure 4A detailed explanation of the specific circuit structure and clamping principle of the clamping circuit.

[0052] The positive compensation network 120 includes resistors R1 and R3, capacitors C1 and C3, and a switch SW1. One end of resistor R1 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the first differential voltage operational amplifier circuit 110. Resistor R3 and capacitor C3 are connected in series between the inverting input terminal of the first differential voltage operational amplifier circuit 110 and the first moving contact of the switch SW1. Capacitor C1 is connected between the inverting input terminal of the first differential voltage operational amplifier circuit 110 and the second moving contact of the switch SW1. The stationary contact of the switch SW1 is connected to the output terminal of the first differential voltage operational amplifier circuit 110.

[0053] The negative compensation network 220 includes resistors R2 and R4, capacitors C2 and C4, and a switch SW2. One end of resistor R2 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the second differential voltage operational amplifier circuit 210. Resistor R4 and capacitor C4 are connected in series between the inverting input terminal of the second differential voltage operational amplifier circuit 210 and the first moving contact of the switch SW2. Capacitor C2 is connected between the inverting input terminal of the second differential voltage operational amplifier circuit 210 and the second moving contact of the switch SW2. The stationary contact of the switch SW2 is connected to the output terminal of the second differential voltage operational amplifier circuit 210.

[0054] In this example embodiment, the resonant frequencies of the positive and negative compensation networks 220 are adjusted by controlling the switching switches SW1 and SW2 respectively, based on the loop bandwidth of the power supply device.

[0055] Using 20K as the dividing point between fast and slow loop bandwidth, when the loop bandwidth is greater than 20K, it is necessary to switch switch SW1 and switch switch SW2 to point b (second moving contact). At this time, the loop bandwidth is determined by resistor R1 and capacitor C1 (resistor R2 and capacitor C2). The resonant frequency of resistor R1 and capacitor C1 (resistor R2 and capacitor C2) is, for example, less than 1 / 5 of 20K, so as to stabilize the loop bandwidth.

[0056] When the loop bandwidth is less than 20K, the switching switches SW1 and SW2 need to be switched to point a (first moving contact). At this time, the loop bandwidth is determined by the resonant frequencies of resistor R1 and capacitor C3 (resistor R2 and capacitor C4) and resistor R3 and capacitor C3 (resistor R4 and capacitor C4). For example, the resonant frequencies of resistor R1 and capacitor C3 (resistor R2 and capacitor C4) should be greater than 5 times the loop bandwidth to stabilize the loop bandwidth.

[0057] The first differential voltage operational amplifier circuit 110 includes a first differential amplifier U1 and a diode D1. The non-inverting input terminal of the first differential amplifier U1 is connected to a positive clamping setting value, the inverting input terminal is connected to a positive compensation network 120 to receive a measured output value, and the output terminal is connected to a first voltage regulator circuit 140. The anode of the diode D1 is connected to the output terminal of the first differential amplifier U1, and the cathode is connected to the inverting input terminal of the first differential amplifier U1.

[0058] The second differential voltage operational amplifier circuit 210 includes a second differential amplifier U2 and a diode D2. The non-inverting input terminal of the second differential amplifier U2 is connected to a positive clamping setting value, the inverting input terminal is connected to a negative compensation network 220 to receive the measured output value, and the output terminal is connected to a second voltage regulator circuit 240. The positive terminal of the diode D2 is connected to the output terminal of the second differential amplifier U2, and the negative terminal is connected to the inverting input terminal of the second differential amplifier U2.

[0059] Because diode D1 is connected between the output and inverting input of the first differential amplifier U1, the output voltage of the first differential amplifier U1 will be pulled up from the positive clamping setting value plus 0.7V to the target voltage. The target voltage refers to the voltage that the first differential amplifier U1 should output when the loop is stable. This shortens the output voltage range of the first differential amplifier U1, thereby accelerating the loop response. Similarly, because diode D2 is connected between the output and inverting input of the second differential amplifier U2, it also increases the output voltage of the corresponding differential amplifier, accelerating the loop response.

[0060] The first voltage regulator circuit 140 includes a Zener diode D3, the anode of which is connected to the output terminal of the first differential voltage amplifier circuit 110, and the cathode of which is connected to the input terminal of the first bias circuit 130. The second voltage regulator circuit 240 includes a Zener diode D4, the cathode of which is connected to the output terminal of the second differential voltage amplifier circuit 210, and the anode of which is connected to the input terminal of the second bias circuit 230.

[0061] Zener diodes D3 and D4 are used to improve the output voltage range of power supply devices.

[0062] The first bias circuit 130 includes a resistor R5 and a clamping diode D5; the second bias circuit 230 includes a resistor R6 and a clamping diode D6. One end of the resistor R5 is connected to the positive power supply AVDD, and the other end of the resistor R5 is connected to the cathode of the clamping diode D5 and the output terminal of the first voltage regulator circuit 140. The anode of the clamping diode D5 is connected to the loop compensation output pin COMP of the power supply device and the cathode of the clamping diode D6. The anode of the clamping diode D6 is connected to one end of the resistor R6 and the output terminal of the second voltage regulator circuit 240, and the other end of the resistor R6 is connected to the negative power supply AVSS.

[0063] Resistors R5 and R6 act as pull-up and pull-down resistors, respectively. The combination of resistor R5 with clamping diode D5 and resistor R6 with clamping diode D6 helps to increase the output voltage range of the power supply device.

[0064] Assuming the sampling resistor inside the power supply device at the 1A level is 0.39Ω, and the gain of the MEASOUT output pin is configured to 20, the positive clamping process of the positive clamping circuit 100 is as follows: Assuming the positive clamping setting is set to 1V and the negative clamping setting is set to -1V, the corresponding clamping points are: The negative clamping site is When the power supply output voltage is 2V and the load resistance is less than 15.6Ω (assuming a load resistance of 10Ω), if the positive clamping circuit 100 does not clamp, the output voltage of the MEASOUT pin will be 1.56V, and the output current will gradually increase from 0A. At a certain moment, the output current will increase to more than 0.1282A, meaning the MEASOUT pin voltage will be greater than 1V. When the MEASOUT pin voltage is greater than the positive clamping setting value of 1V, a voltage difference will be generated across the first differential amplifier U1, causing the output of the first differential amplifier U1 to be negatively biased. At this time, the clamping diode D5 will be positively biased, pulling down the voltage of the loop compensation output pin COMP. The voltage of the loop compensation output pin COMP directly affects the output voltage of the power supply, which will also be pulled down until it stabilizes, i.e., the voltage difference across the first differential amplifier U1 is adjusted to near 0V, stabilizing the output voltage. .

[0065] The negative clamping process of the negative clamping circuit 200 is as follows: When the power supply device output voltage is -2V, the voltage at the MEASOUT output pin will gradually decrease from 0V. At a certain moment, the output current will gradually decrease to less than -0.1282A. At this time, the MEASOUT output pin voltage will be less than the negative clamping setting value of -1V. A voltage difference will be generated across the second differential amplifier U2, and the output of the second differential amplifier U2 will be forward biased. At this time, the clamping diode D6 will be forward biased, pulling up the voltage at the COMP pin. The voltage at the COMP pin directly affects the output voltage of the power supply device, and the output voltage of the power supply device will also be pulled up until it tends to stabilize. The voltage difference across the second differential amplifier U2 is adjusted to be close to 0V, stabilizing the output voltage. .

[0066] When the clamping circuit is not clamping, the voltage at the MEASOUT output pin is between -1V and 1V. For the positive clamping circuit 100, the output of the first differential amplifier U1 will be forward biased, and diode D1 will also be forward biased. The inverting input of the first differential amplifier U1 will be equal to the non-inverting input, and its output will be equal to the positive clamping setting plus the diode voltage, i.e., 1.7V. Assuming there is no Zener diode D3, the voltage at the loop compensation output pin COMP will be 2.4V. If the output voltage of the power supply device is greater than 2.4V, it will be clamped to 2.4V. Therefore, Zener diode D3 needs to be selected according to the output voltage range of the power supply device to improve its output voltage range. The voltage of Zener diode D3 plus 1.4V needs to be greater than the maximum output voltage of the power supply device.

[0067] Similarly, for the negative clamping circuit 200, the Zener diode D4 needs to be selected based on the output voltage range of the power supply device to improve the output voltage range of the power supply device. The voltage of the Zener diode D4 plus 1.4V needs to be greater than the absolute value of the minimum output voltage.

[0068] The positive clamp detection circuit 300 includes a third differential amplifier U3, resistors R7, R9, and R11, diodes D7 and D8. The inverting and non-inverting inputs of the third differential amplifier U3 are connected to the input and output of the first bias circuit 130, respectively. One end of resistor R7 is connected to the output of the third differential amplifier U3, and the other end of resistor R7 is connected to the cathode of diode D7. The anode of diode D7 is connected to one end of resistor R9 and the cathode of diode D8. The anode of diode D8 is connected to the common ground. One end of resistor R11 is connected to the logic power supply DVDD. The other ends of resistors R9 and R11 together output a positive clamp alarm signal.

[0069] The negative clamp detection circuit 400 includes a fourth differential amplifier U4, resistors R8, R10, and R12, diodes D9 and D10. The inverting and non-inverting inputs of the fourth differential amplifier U4 are connected to the input and output of the second bias circuit 230, respectively. One end of resistor R8 is connected to the output of the fourth differential amplifier U4, and the other end of resistor R8 is connected to the cathode of diode D9. The anode of diode D9 is connected to one end of resistor R10 and the cathode of diode D10. The anode of diode D10 is connected to the common ground. One end of resistor R12 is connected to the logic power supply DVDD. The other ends of resistor R12 and resistor R10 together output a negative clamp alarm signal.

[0070] The positive clamping detection circuit 300 and the negative clamping detection circuit 400 detect whether clamping has occurred by judging whether clamping diodes D5 and D6 are forward biased, and the alarm is reliable and accurate.

[0071] When positive clamping occurs, clamping diode D5 will be forward biased. The non-inverting input of the third differential amplifier U3 in the positive clamping detection circuit 300 will be 0.7V higher than the inverting input. At this time, the output of the third differential amplifier U3 will be forward biased, diodes D7 and D8 will be reverse biased, and one end of resistor R9 will be in a high-impedance state. The voltage at the positive clamping alarm signal output will be pulled up to the logic power supply level DVDD by resistor R11, outputting a high-level positive clamping alarm signal for FPGA recognition. When positive clamping does not occur, clamping diode D5 will be reverse biased, the output of the third differential amplifier U3 will be reverse biased, diodes D7 and D8 will be forward biased, and the voltage at the left end of resistor R9 will be -0.7V. By configuring the resistance values ​​of R9 and R11, the positive clamping detection circuit 300 will output a low-level signal of 0V for FPGA recognition.

[0072] Similarly, when negative clamping occurs, clamping diode D6 will be forward biased, the output of the fourth differential amplifier U4 will be forward biased, diodes D9 and D10 will be reverse biased, and one end of resistor R10 will be in a high-impedance state. At this time, the voltage at the negative clamping alarm signal output terminal will be pulled up to the logic power supply level DVDD by resistor R12, outputting a high-level negative clamping alarm signal for FPGA recognition. When negative clamping does not occur, the negative clamping detection circuit 400 outputs a low-level 0V signal for FPGA recognition.

[0073] This application also proposes a VI source board, including a power supply device and a clamping circuit as described in the above embodiments connected to the power supply device.

[0074] It should be noted that the working principle and beneficial effects of the clamping circuit for power supply devices have been described in detail in the above embodiments, so they will not be repeated in this embodiment.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A clamping circuit for a power supply device, characterized in that, include: Positive clamping circuit and / or negative clamping circuit; wherein, The positive clamping circuit includes a first differential voltage operational amplifier circuit, a positive compensation network, and a first bias circuit; the positive compensation network is connected between the inverting input terminal and the output terminal of the first differential voltage operational amplifier circuit, and is connected to the measured output value of the power supply device; the first differential voltage operational amplifier circuit is configured to output the comparison result of the measured output value and the positive clamping setting value to the first bias circuit; the first bias circuit is connected to the power supply device. The negative clamping circuit includes a second differential voltage operational amplifier circuit, a negative compensation network, and a second bias circuit; the negative compensation network is connected between the inverting input terminal and the output terminal of the second differential voltage operational amplifier circuit and is connected to the measured output value of the power supply device; the second differential voltage operational amplifier circuit is configured to output the comparison result of the measured output value and the negative clamping setting value to the second bias circuit; the second bias circuit is connected to the power supply device.

2. The clamping circuit of the power supply device according to claim 1, characterized in that, The positive compensation network is configured to adjust its resonant frequency according to the loop bandwidth of the power supply device; and / or, the negative compensation network is configured to adjust its resonant frequency according to the loop bandwidth of the power supply device.

3. The clamping circuit of the power supply device according to claim 1, characterized in that, The positive compensation network includes resistors R1 and R3, capacitors C1 and C3, and a switching switch SW1. One end of resistor R1 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the first differential voltage operational amplifier circuit. Resistor R3 and capacitor C3 are connected in series between the inverting input terminal of the first differential voltage operational amplifier circuit and the first moving contact of the switching switch SW1. Capacitor C1 is connected between the inverting input terminal of the first differential voltage operational amplifier circuit and the second moving contact of the switching switch SW1. The stationary contact of the switching switch SW1 is connected to the output terminal of the first differential voltage operational amplifier circuit. The negative compensation network includes resistors R2 and R4, capacitors C2 and C4, and a switching switch SW2. One end of resistor R2 is connected to the measured output value of the power supply device, and the other end is connected to the inverting input terminal of the second differential voltage operational amplifier circuit. Resistor R4 and capacitor C4 are connected in series between the inverting input terminal of the second differential voltage operational amplifier circuit and the first moving contact of the switching switch SW2. Capacitor C2 is connected between the inverting input terminal of the second differential voltage operational amplifier circuit and the second moving contact of the switching switch SW2. The stationary contact of the switching switch SW2 is connected to the output terminal of the second differential voltage operational amplifier circuit.

4. The clamping circuit of the power supply device according to claim 1, characterized in that, The first differential voltage operational amplifier circuit includes a first differential amplifier U1 and a diode D1. The non-inverting input terminal of the first differential amplifier U1 is connected to the positive clamping setting value, the inverting input terminal is connected to the positive compensation network to connect to the measured output value, and the output terminal is connected to the first bias circuit. The anode of the diode D1 is connected to the output terminal of the first differential amplifier U1, and the cathode is connected to the inverting input terminal of the first differential amplifier U1. The second differential voltage operational amplifier circuit includes a second differential amplifier U2 and a diode D2. The non-inverting input terminal of the second differential amplifier U2 is connected to the positive clamping setting value, the inverting input terminal is connected to the negative compensation network to access the measured output value, and the output terminal is connected to the second bias circuit. The anode of the diode D2 is connected to the output terminal of the second differential amplifier U2, and the cathode is connected to the inverting input terminal of the second differential amplifier U2.

5. The clamping circuit of the power supply device according to claim 1, characterized in that, The first bias circuit includes a resistor R5 and a clamping diode D5; the second bias circuit includes a resistor R6 and a clamping diode D6. One end of resistor R5 is connected to the positive power supply AVDD, and the other end of resistor R5 is connected to the negative terminal of clamping diode D5 and the output terminal of the first differential voltage operational amplifier circuit. The positive terminal of clamping diode D5 is connected to the loop compensation output pin of the power supply device and the negative terminal of clamping diode D6. The positive terminal of clamping diode D6 is connected to one end of resistor R6 and the output terminal of the second differential voltage operational amplifier circuit. The other end of resistor R6 is connected to the negative power supply AVSS.

6. The clamping circuit of the power supply device according to claim 1, characterized in that, The positive clamping circuit further includes a first voltage regulator circuit; the negative clamping circuit further includes a second voltage regulator circuit. The first voltage regulator circuit is connected between the output terminal of the first differential voltage operational amplifier circuit and the input terminal of the first bias circuit; The second voltage regulator circuit is connected between the output terminal of the second differential voltage operational amplifier circuit and the input terminal of the second bias circuit.

7. The clamping circuit of the power supply device according to claim 6, characterized in that, The first voltage regulator circuit includes a Zener diode D3, the anode of which is connected to the output terminal of the first differential voltage amplifier circuit, and the cathode is connected to the input terminal of the first bias circuit. The second voltage regulator circuit includes a Zener diode D4, the negative terminal of which is connected to the output terminal of the second differential voltage amplifier circuit, and the positive terminal is connected to the input terminal of the second bias circuit.

8. The clamping circuit of the power supply device according to claim 1, characterized in that, It also includes a positive clamping detection circuit and / or a negative clamping detection circuit; The positive clamp detection circuit is connected to the first bias circuit and is configured to detect the bias voltage of the first bias circuit and output a positive clamp alarm signal when positive clamping occurs. The negative clamp detection circuit is connected to the second bias circuit and is configured to detect the bias voltage of the second bias circuit and output a negative clamp alarm signal when a negative clamp occurs.

9. The clamping circuit of the power supply device according to claim 8, characterized in that, The positive clamp detection circuit includes a third differential amplifier U3, resistors R7, R9, and R11, diode D7, and diode D8. The inverting and non-inverting inputs of the third differential amplifier U3 are connected to the input and output of the first bias circuit, respectively. One end of resistor R7 is connected to the output of the third differential amplifier U3, and the other end of resistor R7 is connected to the cathode of diode D7. The anode of diode D7 is connected to one end of resistor R9 and the cathode of diode D8. The anode of diode D8 is connected to a common ground. One end of resistor R11 is connected to a logic power supply. The other ends of resistors R9 and R11 together output a positive clamp alarm signal. The negative clamp detection circuit includes a fourth differential amplifier U4, resistors R8, R10, and R12, diode D9, and diode D10. The inverting and non-inverting inputs of the fourth differential amplifier U4 are connected to the input and output of the second bias circuit, respectively. One end of resistor R8 is connected to the output of the fourth differential amplifier U4, and the other end of resistor R8 is connected to the cathode of diode D9. The anode of diode D9 is connected to one end of resistor R10 and the cathode of diode D10. The anode of diode D10 is connected to a common ground. One end of resistor R12 is connected to a logic power supply, and the other ends of resistor R12 and resistor R10 together output a negative clamp alarm signal.

10. The clamping circuit of the power supply device according to claim 1, characterized in that, It also includes a first signal configuration terminal DAC1 and / or a second signal configuration terminal DAC2. The first signal configuration terminal DAC1 is connected to the first differential voltage operational amplifier circuit and provides a positive clamping setting value; the second signal configuration terminal DAC2 is connected to the second differential voltage operational amplifier circuit and provides a negative clamping setting value.

11. A VI source board, characterized in that, It includes a power supply device and a clamping circuit as described in any one of claims 1-10 connected to the power supply device.

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