A dual 85 test circuit for AC-DC power supply chips

Abstract

This utility model relates to the field of circuit technology and discloses a dual 85 test circuit for an AC-DC power supply chip. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (with a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. This utility model overcomes the shortcomings of THB testing and whole-machine dual 85 testing, achieving the advantage of performing dual 85 testing under simulated actual operating conditions (PWM operation state) while increasing the number of tests to 77 PCS.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a dual 85 test circuit for an AC-DC power supply chip. Background Technology

[0002] Modern electronic devices are widely used in various complex environments, including high-temperature and high-humidity scenarios such as tropical regions, humid industrial environments, and some outdoor applications. To ensure that AC-DC power chips can operate stably and reliably in these harsh environments, corresponding environmental adaptability tests are required. The dual 85 test is an important testing method that simulates high-temperature and high-humidity environments.

[0003] In existing dual 85 testing, chip manufacturers conduct a 1000-hour THB test (77 chips tested) on the chip. This involves supplying power to the chip's VDD at 85℃ / 85% humidity, enabling the logic control circuitry to operate, while simultaneously setting the COMP feedback pin voltage and the CS current sampling pin voltage to 0V. This ensures the PWM signal output for logic control remains low, keeping the internal power MOSFETs off. Then, 80% of the MOSFET's maximum withstand voltage is applied to the SW pin (the MOSFET's drain pin). This method is commonly used by chip companies and can effectively evaluate the reliability of AC-DC chip internal MOSFETs under high temperature, high humidity, and high pressure conditions, as well as the reliability of most logic control circuits under these conditions, using simple external circuitry. However, the chip's operating state differs somewhat from actual operation. The PWM drive circuit is not active, and this part of the circuit is not as rigorous as in actual operation, so the evaluation results are not comprehensive enough.

[0004] This utility model patent discloses a dual 85 test circuit for AC-DC power chips, which is mainly used to verify the performance stability and reliability of the chip when used for a long time in a high temperature and high humidity environment, so as to evaluate the chip's tolerance to harsh environments and discover potential reliability problems in advance, such as moisture absorption of chip packaging materials, corrosion of metal pins, and leakage of internal circuits of the chip. Utility Model Content

[0005] To overcome the above shortcomings, this utility model provides a dual 85 test circuit for AC-DC power chips, which aims to improve the existing test circuits' inability to detect problems such as moisture absorption of chip packaging materials, corrosion of metal pins, and leakage of internal circuits in advance.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a dual 85 test circuit for an AC-DC power chip, a high-voltage DC power supply connected to the SW pin of the AC-DC chip via a current-limiting resistor network; a current detection module consisting of a first resistor connected in series between the CS pin of the AC-DC chip and ground; a power supply module including a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin; a feedback control module including an RC network (a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground; and multiple test circuits integrated in parallel on the same PCB board to form a multi-channel test system.

[0007] Furthermore, the current-limiting resistor network consists of 5 to 6 resistors with a resistance of 510KΩ connected in series, and the voltage of the high-voltage DC power supply is 80% of the maximum withstand voltage of the MOS transistor inside the AC-DC chip.

[0008] Furthermore, the first resistor has a resistance of 100Ω, which is used to limit the detection current of the CS pin to avoid triggering overvoltage or undervoltage protection.

[0009] Furthermore, the decoupling capacitor has a capacitance of 0.1μF, and the DC voltage of the power supply module is 20V and does not exceed 80% of the maximum operating voltage of the VDD pin.

[0010] Furthermore, in the RC network, the resistance of the second resistor is 15KΩ, and the capacitance of the first capacitor is 1nF.

[0011] Furthermore, the multi-channel test system has 77 test circuits connected in parallel, used for batch testing of the high temperature and high humidity reliability of AC-DC chips.

[0012] Furthermore, the test circuit is applied to a dual 85 test environment (85℃ / 85%RH), and the AC-DC chip operates in PWM dynamic switching mode.

[0013] This utility model has the following beneficial effects:

[0014] 1. This utility model fills the gaps in THB testing and whole-machine dual 85 testing, that is, it realizes dual 85 testing under simulated actual working conditions (PWM working state), and can increase the number of tests to 77 PCS.

[0015] 2. In this utility model, a conventional-sized high and low temperature test chamber can test hundreds of test samples. If it is a whole system test, a conventional-sized high and low temperature test chamber can only test 4 to 6 test samples.

[0016] 3. In this utility model, the combination of THB test and whole machine dual 85 test can more comprehensively and effectively evaluate the stability and reliability of the AC-DC chip under test in high temperature and high humidity environment with the investment of acceptable test equipment resources. Attached Figure Description

[0017] Figure 1 This invention provides a test circuit diagram for a dual 85 test circuit for an AC-DC power chip.

[0018] Figure 2 The image shows the finished product of the AC-DC power chip dual 85 test circuit proposed in this utility model. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0020] Reference Figure 1 and Figure 2 This utility model provides an embodiment of an AC-DC power chip dual 85 test circuit. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip via a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. The current-limiting resistor network consists of 5-6 resistors with a resistance of 510KΩ. The circuit is composed of multiple series components, and the voltage of the high-voltage DC power supply is 80% of the maximum withstand voltage of the internal MOSFET of the AC-DC chip. The first resistor has a resistance of 100Ω and is used to limit the detection current of the CS pin to avoid triggering overvoltage or undervoltage protection. The decoupling capacitor has a capacitance of 0.1μF. The DC voltage of the power supply module is 20V and does not exceed 80% of the maximum operating voltage of the VDD pin. In the RC network, the second resistor has a resistance of 15KΩ and the first capacitor has a capacitance of 1nF. The number of test circuits connected in parallel in the multi-channel test system is 77, which are used for batch testing of the high temperature and high humidity reliability of the AC-DC chip. The test circuit is applied to the dual 85 test environment (85℃ / 85%RH), and the AC-DC chip operates in PWM dynamic switching mode.

[0021] Specifically, in this circuit, a 300KΩ resistor is used to limit the current of the SW pin, preventing the MOS transistor from being damaged by instantaneous overcurrent. If the MOS is broken down, the resistor network can block the short-circuit current, thereby protecting the high-voltage power supply and other circuits. At the same time, the current of the MOS transistor flows through a 100Ω resistor to generate a voltage signal (V_CS = I_MOS × 100Ω). If V_CS is too low (the resistor is too small) → triggering undercurrent protection, the chip is turned off. If V_CS is too high (the resistor is too large) → exceeding the withstand voltage of the CS pin (such as 1V), the chip may be damaged. In addition, in this circuit, a 0.1μF capacitor is used to filter out high-frequency noise, ensuring the stable power supply of the logic control circuit, and 20V is 80% of the maximum withstand voltage of VDD (such as 25V), avoiding the risk of overvoltage. At the same time, the output current (I_comp) of the COMP pin flows through a 15KΩ resistor to generate a feedback voltage (V_COMP = I_comp × 15KΩ). If V_COMP < V_COMP_BM (such as 0.5V), the PWM is turned off. If V_COMP > V_COMP_OLP (such as 2V), the PWM is turned off. Finally, the above single-chip test circuit is repeated 77 groups and integrated in parallel on the same PCB board to verify the reliability of 77 AC-DC chips in the dual 85 environment at the same time, so that a single test chamber can complete high-density testing and reduce costs.

[0022] Working principle: In the circuit structure, the SW pin is connected to a high-voltage DC power supply (adjustable from 400V to 2000V) in series through six 300KΩ resistors (R1 - R6). After the resistor network divides the voltage, the actual voltage applied to the SW pin is 80% of the MOS withstand voltage of the high-voltage power supply (for example: if the MOS withstand voltage is 1000V, the test voltage is set to 800V). The CS pin is grounded through a 100Ω resistor to detect the current of the MOS transistor. The VDD pin is connected to a 20V DC power supply, and at the same time, a 0.1μF capacitor is connected in parallel to the ground. The COMP pin is connected to a 15KΩ resistor (R10) and a 1nF capacitor (not marked in the figure) in parallel to the ground. The output current (I_comp) of the COMP pin flows through a 15KΩ resistor to generate a feedback voltage (V_COMP = I_comp × 15KΩ). The above single-chip test circuit is repeated 77 groups and integrated in parallel on the same PCB board.

[0023] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A dual 85 test circuit for an AC-DC power supply chip, characterized in that: A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network; The current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. The power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply that provides DC voltage to the VDD pin; The feedback control module includes an RC network connected in parallel between the COMP pin of the AC-DC chip and ground, and a second resistor connected in series with the first capacitor; Multiple test circuits are connected in parallel and integrated on the same PCB board to form a multi-channel test system.

2. The AC-DC power chip dual 85 test circuit according to claim 1, characterized in that: The current-limiting resistor network consists of 5 to 6 resistors with a resistance of 510KΩ connected in series, and the voltage of the high-voltage DC power supply is 80% of the maximum withstand voltage of the MOS transistor inside the AC-DC chip.

3. The AC-DC power chip dual 85 test circuit according to claim 2, characterized in that: The first resistor has a resistance of 100Ω and is used to limit the detection current of the CS pin to avoid triggering overvoltage or undervoltage protection.

4. The AC-DC power chip dual 85 test circuit according to claim 3, characterized in that: The decoupling capacitor has a capacitance of 0.1μF, and the DC voltage of the power supply module is 20V and does not exceed 80% of the maximum operating voltage of the VDD pin.

5. The AC-DC power chip dual 85 test circuit according to claim 4, characterized in that: In the RC network, the resistance of the second resistor is 15KΩ and the capacitance of the first capacitor is 1nF.

6. The AC-DC power chip dual 85 test circuit according to claim 4, characterized in that: The multi-channel test system has 77 test circuits connected in parallel, used for batch testing of the high temperature and high humidity reliability of AC-DC chips.

7. The AC-DC power chip dual 85 test circuit according to claim 6, characterized in that: The test circuit is applied to a dual 85 test environment, which is 85℃ / 85%RH, and the AC-DC chip operates in PWM dynamic switching mode.

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