A high-reliability power semiconductor module

Abstract

This utility model discloses a high-reliability power semiconductor module, relating to the field of power semiconductor modules. It includes an AMB substrate and several chipsets disposed on the AMB substrate, each chipset including at least one power chip. For any chipset, when it includes only one power chip, the power chip is electrically connected to the AMB substrate via copper foil. When a chipset includes more than one power chip, the power chips are electrically connected to each other and to the AMB substrate via copper foil. This utility model uses copper foil instead of bonding wires for efficient and stable current conduction in the power semiconductor module, improving the performance and reliability of the power semiconductor module.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor modules, and in particular to a high-reliability power semiconductor module. Background Technology

[0002] In existing power semiconductor modules, bonding wires are often used to establish electrical connections between the chip and external circuits for current transmission. However, bonding wires have several limitations. First, bonding wires have relatively high resistance, generating significant Joule heat during high-current transmission. This not only reduces the power conversion efficiency of the power semiconductor module but also affects its stability and reliability due to excessive heat. Second, bonding wires are susceptible to thermal and mechanical stresses during long-term use, leading to wire detachment or breakage, and ultimately module failure. Therefore, finding a more efficient and stable current conduction method to replace bonding wires is of great significance. Utility Model Content

[0003] In response to the aforementioned problems and technical requirements, the applicant has proposed a high-reliability power semiconductor module.

[0004] The technical solution of this utility model is as follows:

[0005] A high-reliability power semiconductor module includes an AMB substrate and a plurality of chipsets disposed on the AMB substrate, wherein the chipsets include at least one power chip.

[0006] For any chipset, when the chipset includes only one power chip, the power chip is electrically connected to the AMB substrate via copper foil; when the chipset includes more than one power chip, the power chips are electrically connected to each other via copper foil and to the AMB substrate via copper foil.

[0007] A further technical solution is that the purity of the copper foil is not less than 99.9%, and the thickness of the copper foil is in the range of 0.1-0.5mm.

[0008] A further technical solution is that the copper foil surface is coated with an insulating protective coating, the thickness of which ranges from 0.01 to 0.05 mm.

[0009] A further technical solution is that the material of the insulating protective coating includes polyimide.

[0010] A further technical solution is that the AMB substrate includes an upper bridge first connection area, an upper bridge second connection area, an upper bridge third connection area, a lower bridge first connection area, a lower bridge second connection area, and a lower bridge third connection area, and the power chip is disposed on the upper bridge first connection area and / or the lower bridge first connection area;

[0011] The power chip includes a MOSFET chip. The gate of each power chip is connected to one end of a gate resistor via a bonding wire. The other end of the gate resistor is correspondingly soldered to the upper bridge second connection area or the lower bridge second connection area. The source of each power chip is correspondingly connected to the upper bridge third connection area or the lower bridge third connection area via a bonding wire.

[0012] A further technical solution is that the AMB substrate further includes an upper bridge gate lead-out region, an upper bridge source lead-out region, a lower bridge gate lead-out region, and a lower bridge source lead-out region, wherein,

[0013] The second connection region of the upper bridge is connected to the gate lead-out region of the upper bridge via a bonding wire, and the third connection region of the upper bridge is connected to the source lead-out region of the upper bridge via a bonding wire;

[0014] The second connection region of the lower bridge is connected to the gate lead-out region of the lower bridge via a bonding wire, and the third connection region of the lower bridge is connected to the source lead-out region of the lower bridge via a bonding wire.

[0015] A further technical solution is that the AMB substrate further includes a first signal connection area, and the power chip disposed on the lower bridge first connection area is electrically connected to the first signal connection area through copper foil; the power chip disposed on the upper bridge first connection area is electrically connected to the lower bridge first connection area through copper foil.

[0016] The further technical solution includes a first signal terminal, a second signal terminal, and a third signal terminal;

[0017] The first signal terminal is connected to the first signal connection area, the second signal terminal is connected to the first connection area of ​​the upper bridge, and the third signal terminal is connected to the first connection area of ​​the lower bridge.

[0018] A further technical solution is that the power semiconductor module further includes an NTC resistor, and the AMB substrate further includes a first temperature measuring area and a second temperature measuring area. One end of the NTC resistor is soldered to the first temperature measuring area, and the other end of the NTC resistor is soldered to the second temperature measuring area.

[0019] A further technical solution is that the copper foil is soldered to the power chip and the AMB substrate using solder, or the copper foil is connected to the power chip and the AMB substrate by crimping.

[0020] The beneficial technical effects of this utility model are:

[0021] (1) Reduced resistance: Copper foil has better conductivity than bonding wire, and its resistance is much lower than that of bonding wire. Under the same current transmission conditions, using copper foil instead of bonding wire can reduce the overall resistance of the module by 30% to 50%, thereby reducing Joule heating and improving the power conversion efficiency of the power semiconductor module.

[0022] (2) Improved reliability: Copper foil has better mechanical strength and resistance to thermal stress. Compared with bonding wires, copper foil will not easily break or fall off due to frequent thermal expansion and contraction. Tests have shown that in temperature cycling tests, the connection reliability of power semiconductor modules using copper foil is more than 50% higher than that of modules using bonding wires.

[0023] (3) Optimized heat dissipation: Since copper foil can reduce resistance and heat generation, and it has good thermal conductivity, it can help the module dissipate heat better. Thermal simulation experiments have shown that after using copper foil for current conduction, the local hot spot temperature of the module can be reduced by 10-20℃, which is beneficial for the stable operation of power semiconductor modules under high power and high frequency conditions. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of one embodiment of the high-reliability power semiconductor module provided by this utility model.

[0025] Figure 2 This is a circuit topology diagram of one embodiment of the high-reliability power semiconductor module provided by this utility model.

[0026] Figure label:

[0027] 1-First signal terminal, 2-Second signal terminal, 3-Third signal terminal, 4-Fourth signal pin, 5-Fifth signal pin, 6-Sixth signal pin, 7-Seventh signal pin, 8-Eighth signal pin, 9-Ninth signal pin, 10-Tenth signal pin, 11-Eleventh signal pin, 12-Twelfth signal pin, 13-Thirteenth signal pin, 14-Fourteenth signal pin, 15-Fifteenth signal pin, 16-Copper foil, 17-NTC resistor;

[0028] 101-First connection region of the upper bridge, 102-Second connection region of the upper bridge, 103-Third connection region of the upper bridge, 104-Gate lead-out region of the upper bridge, 105-Source lead-out region of the upper bridge, 106-First signal connection region, 107-First temperature measurement region, 108-Second temperature measurement region, 109-Second signal connection region, 110-Third signal connection region, 111-Fourth signal connection region, 112-Fifth signal connection region;

[0029] 201 - Lower bridge first connection region, 202 - Upper bridge second connection region, 203 - Lower bridge third connection region, 204 - Lower bridge gate lead-out region, 205 - Lower bridge source lead-out region. Detailed Implementation

[0030] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0031] This utility model provides a high-reliability power semiconductor module, including an AMB (Active Metal Brazing) substrate and a plurality of chipsets disposed on the AMB substrate, wherein the chipsets include at least one power chip;

[0032] For any chipset, when the chipset includes only one power chip, the power chip is electrically connected to the AMB substrate through copper foil 16; when the chipset includes more than one power chip, the power chips are electrically connected to each other through copper foil 16 and electrically connected to the AMB substrate through copper foil 16.

[0033] Specifically, the copper foil 16 must be made of high-purity copper, with a purity of not less than 99.9% to ensure good conductivity. The thickness of the copper foil 16 is set between 0.1-0.5 mm. To prevent oxidation and improve its electrical insulation performance, in this embodiment, an insulating protective coating with a thickness of 0.01-0.05 mm is coated on the surface of the copper foil 16. This insulating protective coating is made of a high-temperature resistant and highly insulating material, such as polyimide. In specific implementation, the shape of the copper foil 16 needs to be customized according to the chip layout and current transmission path requirements in the power semiconductor module.

[0034] In this embodiment, a total of 4 chipsets are set, and each chipset contains three power chips. In this embodiment, the power chips are MOSFET chips. Figure 1 As shown, power chips M1-M3 constitute the first chipset, power chips M4-M6 constitute the second chipset, power chips M7-M9 constitute the third chipset, and power chips M10-M12 constitute the fourth chipset.

[0035] The metal layer of the AMB substrate is patterned and divided into multiple different conductive regions, such as... Figure 1 As shown, it includes an upper bridge first connection area 101, an upper bridge second connection area 102, an upper bridge third connection area 103, a lower bridge first connection area 201, a lower bridge second connection area 202, and a lower bridge third connection area 203, and the power chip is disposed on the upper bridge first connection area 101 and / or the lower bridge first connection area 201;

[0036] The gate of each power chip is connected to one end of a gate resistor via a bonding wire, and the other end of the gate resistor is correspondingly soldered to the upper bridge second connection region 102 or the lower bridge second connection region 202; the source of each power chip is correspondingly connected to the upper bridge third connection region 103 or the lower bridge third connection region 203 via a bonding wire.

[0037] Specifically, when the power chip is a MOSFET chip, a drain is typically provided on the back side of the power chip. In the chipset, the power chip is disposed on the upper bridge first connection region 101 and / or the lower bridge first connection region 201, meaning the drain of the power chip is soldered to the upper bridge first connection region 101 and / or the lower bridge first connection region 201. The power chip is soldered to the upper bridge first connection region 101, and one end of the gate resistor connected to the power chip is correspondingly soldered to the upper bridge second connection region 102. The source of the power chip is connected to the upper bridge third connection region 103 via a bonding wire. Similarly, the power chip is soldered to the lower bridge first connection region 201, and one end of the gate resistor connected to the power chip is correspondingly soldered to the lower bridge second connection region 202. The source of the power chip is connected to the lower bridge third connection region 203 via a bonding wire.

[0038] like Figure 1 As shown, in this embodiment, chipsets are disposed in both the upper bridge first connection area 101 and the lower bridge first connection area 201. The first and second chipsets are disposed in the upper bridge first connection area 101, and the third and fourth chipsets are disposed in the lower bridge first connection area 201. The gates of power chips M1-M12 are sequentially connected to one end of resistors R1-R12 via bonding wires. The sources of power chips M1-M6 are connected to the upper bridge third connection area 103 via bonding wires, and the sources of power chips M7-M12 are connected to the lower bridge third connection area 203 via bonding wires. The other ends of resistors R1-R6 are soldered to the upper bridge second connection area 102, and the other ends of resistors R7-R12 are soldered to the lower bridge second connection area 202.

[0039] The conductive regions of the AMB substrate further include an upper bridge gate lead-out region 104, an upper bridge source lead-out region 105, a lower bridge gate lead-out region 204, and a lower bridge source lead-out region 205, wherein,

[0040] The upper bridge second connection region 102 is connected to the upper bridge gate lead-out region 104 via a bonding wire, and the upper bridge third connection region 103 is connected to the upper bridge source lead-out region 105 via a bonding wire.

[0041] The second connection region 202 of the lower bridge is connected to the gate lead-out region 204 of the lower bridge via a bonding wire, and the third connection region 203 of the lower bridge is connected to the source lead-out region 205 of the lower bridge via a bonding wire.

[0042] The conductive area of ​​the AMB substrate also includes a first signal connection area 106. The power chip disposed on the lower bridge first connection area 201 is electrically connected to the first signal connection area 106 through copper foil 16; the power chip disposed on the upper bridge first connection area 101 is electrically connected to the lower bridge first connection area 201 through copper foil 16.

[0043] Specifically, such as Figure 1As shown, in the first chipset, the sources of power chips M1-M3 are interconnected through a first copper foil, and the first copper foil is connected to the first connection point of the lower bridge first connection area 201; in the second chipset, the sources of power chips M4-M6 are interconnected through a second copper foil, and the second copper foil is connected to the second connection point of the lower bridge first connection area 201; in the third chipset, the sources of power chips M7-M9 are interconnected through a third copper foil, and the third copper foil is connected to the first connection point of the first signal connection area 106; in the fourth chipset, the sources of power chips M10-M12 are interconnected through a fourth copper foil, and the fourth copper foil is connected to the second connection point of the first signal connection area 106.

[0044] The power semiconductor module further includes a first signal terminal 1, a second signal terminal 2, and a third signal terminal 3. The first signal terminal 1 is connected to the first signal connection area 106, the second signal terminal 2 is connected to the upper bridge first connection area 101, and the third signal terminal 3 is connected to the lower bridge first connection area 201.

[0045] Furthermore, the power semiconductor module also includes an NTC (Negative Temperature Coefficient) resistor 17, and the AMB substrate also includes a first temperature measuring area 107 and a second temperature measuring area 108. One end of the NTC resistor 17 is soldered to the first temperature measuring area 107, and the other end of the NTC resistor is soldered to the second temperature measuring area 108. The temperature of the power semiconductor module is detected by detecting the resistance value of the NTC resistor 17.

[0046] The conductive areas of the AMB substrate further include a second signal connection area 109, a third signal connection area 110, a fourth signal connection area 111, and a fifth signal connection area 112; the upper bridge first connection area 101 is connected to the fourth signal pin 4, the fifth signal connection area 112 is connected to the fifth signal pin 5, the upper bridge source lead-out area 105 is connected to the sixth signal pin 6, the upper bridge gate lead-out area 104 is connected to the seventh signal pin 7, the fourth signal connection area 111 is connected to the eighth signal pin 8, the third signal connection area 110 is connected to the ninth signal pin 9, the second signal connection area 109 is connected to the tenth signal pin 10, the lower bridge source lead-out area 205 is connected to the eleventh signal pin 11, the lower bridge gate lead-out area 204 is connected to the twelfth signal pin 12, the second temperature sensing area 108 is connected to the thirteenth signal pin 13, the first temperature sensing area 107 is connected to the fourteenth signal pin 14, and the lower bridge first connection area 201 is connected to the fifteenth signal pin 15.

[0047] This utility model also provides a specific process flow for using copper foil 16 instead of bonding wire for current conduction, including:

[0048] The required copper foil 16 is fabricated using high-precision stamping or etching processes based on a pre-designed shape. For stamping, a dedicated die is used to ensure the dimensional accuracy of the copper foil 16 is within ±0.05mm. For etching, an environmentally friendly etching solution is used, and etching time and temperature are controlled to ensure a smooth, burr-free copper foil surface.

[0049] After the required copper foil 16 is prepared, the copper foil 16 is connected to the connection points of the power chip electrode and the AMB substrate. The connection can be made by welding or pressing.

[0050] When using the soldering method, the surfaces of the power chip electrodes and external connection points are first cleaned and pre-treated to remove oil and oxide layers. Then, an appropriate amount of solder is evenly applied to the corresponding connection areas and the connection ends of the copper foil 16. High-precision soldering equipment, such as a laser soldering machine, is used to perform the soldering under suitable parameters. The soldering temperature is controlled between 200 and 250°C, and the soldering time is controlled between 0.5 and 2 seconds to ensure that the solder fully melts and forms a reliable connection. Preferably, the solder used is a specially formulated low-temperature, high-conductivity solder, such as tin-silver solder with a silver content of 3% to 5%, to ensure soldering quality and low contact resistance.

[0051] When using the crimping method, a corresponding crimping mold needs to be designed. The crimping mold is used to tightly press the connection end of the copper foil 16 to the connection point of the power chip electrode and the AMB substrate. The crimping pressure is controlled between 50 and 100 N to ensure that the contact resistance of the crimped part is low enough.

[0052] After connecting the copper foil 16 to the connection points of the power chip electrodes and the AMB substrate, an insulating protective coating is applied. Using precision coating equipment, such as an automatic sprayer, the insulating protective coating material is evenly applied to the surface of the copper foil 16. After coating, the power semiconductor module is placed in a constant temperature drying oven for curing at 150–200°C for 1–3 hours to ensure optimal performance of the insulating protective coating.

[0053] In summary, this invention uses copper foil instead of bonding wires in power semiconductor modules for efficient and stable current conduction, thereby improving the performance and reliability of power semiconductor modules.

[0054] In the description of this specification, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. A feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. The description referring to the term "an embodiment," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating this disclosure and are not intended to limit the scope of this disclosure. Other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of this utility model should be considered to be included within the protection scope of this utility model.

Claims

1. A high-reliability power semiconductor module, characterized by, It includes an AMB substrate and several chipsets disposed on the AMB substrate, wherein the chipsets include at least one power chip; For any chipset, when the chipset includes only one power chip, the power chip is electrically connected to the AMB substrate via copper foil; when the chipset includes more than one power chip, the power chips are electrically connected to each other via copper foil and to the AMB substrate via copper foil.

2. The high-reliability power semiconductor module according to claim 1, characterized in that The thickness of the copper foil ranges from 0.1 to 0.5 mm.

3. The high-reliability power semiconductor module according to claim 1, characterized by The copper foil surface is coated with an insulating protective coating, the thickness of which ranges from 0.01 to 0.05 mm.

4. The high-reliability power semiconductor module according to claim 3, characterized in that The material of the insulating protective coating includes polyimide.

5. The high-reliability power semiconductor module of claim 1, wherein, The AMB substrate includes an upper bridge first connection area, an upper bridge second connection area, an upper bridge third connection area, a lower bridge first connection area, a lower bridge second connection area, and a lower bridge third connection area, and the power chip is disposed on the upper bridge first connection area and / or the lower bridge first connection area; The power chip includes a MOSFET chip. The gate of each power chip is connected to one end of a gate resistor via a bonding wire. The other end of the gate resistor is correspondingly soldered to the upper bridge second connection area or the lower bridge second connection area. The source of each power chip is correspondingly connected to the upper bridge third connection area or the lower bridge third connection area via a bonding wire.

6. The high-reliability power semiconductor module according to claim 5, characterized in that The AMB substrate further includes an upper bridge gate lead-out region, an upper bridge source lead-out region, a lower bridge gate lead-out region, and a lower bridge source lead-out region, wherein, The second connection region of the upper bridge is connected to the gate lead-out region of the upper bridge via a bonding wire, and the third connection region of the upper bridge is connected to the source lead-out region of the upper bridge via a bonding wire; The second connection region of the lower bridge is connected to the gate lead-out region of the lower bridge via a bonding wire, and the third connection region of the lower bridge is connected to the source lead-out region of the lower bridge via a bonding wire.

7. The high-reliability power semiconductor module according to claim 5, characterized by The AMB substrate further includes a first signal connection area, and a power chip disposed on the lower bridge first connection area is electrically connected to the first signal connection area through copper foil; a power chip disposed on the upper bridge first connection area is electrically connected to the lower bridge first connection area through copper foil.

8. The high-reliability power semiconductor module according to claim 7, characterized in that It also includes a first signal terminal, a second signal terminal, and a third signal terminal; The first signal terminal is connected to the first signal connection area, the second signal terminal is connected to the first connection area of ​​the upper bridge, and the third signal terminal is connected to the first connection area of ​​the lower bridge.

9. The high-reliability power semiconductor module according to claim 7, characterized by The power semiconductor module also includes an NTC resistor, and the AMB substrate also includes a first temperature measuring area and a second temperature measuring area. One end of the NTC resistor is soldered to the first temperature measuring area, and the other end of the NTC resistor is soldered to the second temperature measuring area.

10. The high-reliability power semiconductor module of claim 1, wherein, The copper foil is soldered to the power chip and AMB substrate using solder, or the copper foil is connected to the power chip and AMB substrate by crimping.

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