A robot system based on FPGA

Abstract

This utility model relates to the field of robotics technology and provides an FPGA-based robot system, including an FPGA main control chip, a voice recognition module, an image recognition module, a motor control module, and an environmental detection module. The input and output terminals of the voice recognition module are connected to the FPGA main control chip. The image recognition module includes a camera and an image display, with the camera output terminal connected to the FPGA main control chip. The motor control module includes a robotic arm servo unit and a vehicle drive motor unit, with the FPGA main control chip simultaneously connected to both the robotic arm servo unit and the vehicle drive motor unit. The environmental detection module includes an ambient light monitoring unit, an ambient temperature monitoring unit, and an ambient humidity monitoring unit, with the output terminal connected to the FPGA main control chip. The FPGA has greater parallelism advantages at higher frequencies, offering high flexibility and customizability.

Description

Technical Field

[0001] This utility model relates to the field of robotics technology, specifically to an FPGA-based robot system. Background Technology

[0002] As a type of intelligent robot, companion robots can perform functions such as indoor patrol and monitoring, indoor environment monitoring, robotic arm-assisted grasping, fall detection, timed medication reminders, voice control of IoT platforms, identity recognition, and elderly companionship.

[0003] Companion robot control systems are typically equipped with CPUs and GPUs. The computation of CPUs and GPUs generally relies on increasing the number of computing units. The working principle of computation is that the data generated by one computing unit is immediately processed by the next computing unit in the pipeline. This eliminates the "fetch-compute-store" link in the data flow channel, which facilitates the computational operations of data producers and consumers, thereby improving performance. Conversely, due to multiple limitations such as fixed architecture, fixed number of cores, fixed instruction set, and rigid memory architecture, CPUs and GPUs can only perform computations at the expense of performance, thereby reducing the overall operating speed of the system. At the same time, the fixed CPU and GPU modules make it difficult to expand subsequent modules when robot functions need to be updated. Utility Model Content

[0004] The purpose of this invention is to provide an FPGA-based robot system that can solve the technical problem of poor reconfigurability in existing companion robot systems.

[0005] To achieve the above objectives, an FPGA-based robot system includes an FPGA main control chip, a speech recognition module, an image recognition module, a motor control module, and an environmental detection module.

[0006] The input and output terminals of the voice recognition module are connected to the FPGA main control chip;

[0007] The image recognition module includes a camera and an image display, with the camera output connected to the FPGA main control chip;

[0008] The motor control module includes a robotic arm servo unit and a car drive motor unit, and the FPGA main control chip is connected to both the robotic arm servo unit and the car drive motor unit.

[0009] The environmental monitoring module includes an ambient light monitoring unit, an ambient temperature monitoring unit, and an ambient humidity monitoring unit. The output of the environmental monitoring module is connected to the FPGA main control chip.

[0010] Further configuration: The FPGA main control chip includes a clock module, a digital recognition top layer, an LCD top layer, a DDR3 controller, an image resolution setting module, and an OV564O driver.

[0011] Further configured, the clock module output is simultaneously connected to the OV564O driver, the LCD top layer, the image resolution setting module, and the DDR3 controller. The LCD top layer output is connected to the digital recognition top layer, and the DDR3 controller output is connected to the image resolution setting module.

[0012] A further configuration is that the top-level output terminal of the digital recognition is connected to an LCD display, and the top-level output terminal of the digital recognition is connected to a digital tube display via a digital tube driver.

[0013] Further configuration involves the DDR3 controller communicating with DDR3 peripherals.

[0014] Further configuration involves the 0V564O driver communicating with the camera.

[0015] Further configuration involves connecting the camera output to the image display input.

[0016] Further configuration involves connecting the vehicle's drive motor unit to the automatic obstacle avoidance module.

[0017] Further configured, the output terminals of the ambient temperature monitoring unit and the ambient humidity monitoring unit are connected to an ambient temperature and humidity display.

[0018] Further configuration involves connecting the output of the ambient light monitoring unit to a illuminator.

[0019] The beneficial effects of one or more of the above technical solutions:

[0020] (1) Replace the original CPU and GPU with FPGA. FPGA adjusts the frequency through parallel and direct execution algorithms. FPGA performs calculations at a lower frequency and a lower switching rate. However, compared with the equivalent computing performance of CPU and GPU, FPGA has a greater advantage in parallelism at a higher frequency, so that customers can achieve higher energy efficiency.

[0021] (2) FPGA chips can be programmed to implement various digital circuits, and have high flexibility and customizability, and can adapt to various personalized customization needs. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute a limitation thereof.

[0023] Figure 1This is a schematic diagram of the structure of this utility model;

[0024] Figure 2 A schematic diagram showing the connection between the FPGA main control chip and the image recognition module of this utility model.

[0025] In the diagram, 1. FPGA main control chip; 11. Clock module; 12. Digital recognition top layer; 13. LCD top layer; 14. DDR3 controller; 15. Image resolution setting module; 16. OV564O driver; 17. DDR3 peripherals.

[0026] 2. Speech recognition module;

[0027] 3. Image recognition module; 31. Camera; 32. LCD display; 33. Digital tube display; 34. Digital tube driver;

[0028] 4. Motor control module; 41. Robotic arm servo unit; 42. Car drive motor unit; 43. Automatic obstacle avoidance module;

[0029] 5. Environmental monitoring module; 51. Ambient light monitoring unit; 52. Ambient temperature monitoring unit; 53. Ambient humidity monitoring unit; 54. Lighting device; 55. Ambient temperature and humidity display. Detailed Implementation

[0030] The specific implementation of this embodiment will now be described with reference to the accompanying drawings.

[0031] An FPGA-based robot system includes an FPGA main control chip 1, which is connected to a voice recognition module 2, an image recognition module 3, a motor control module 4, and an environmental detection module 5 through a top-level control circuit.

[0032] See attached document Figure 1 The FPGA main control chip 1 includes a clock module 11, a digital recognition top layer 12, an LCD top layer 13, a DDR3 controller 14, an image resolution setting module 15, and an OV564O driver 16.

[0033] The clock module 11 output is simultaneously connected to the OV564O driver 16, the LCD top layer 13, the image resolution setting module 15, and the DDR3 controller 14. The LCD top layer 13 output is connected to the digital recognition top layer 12, and the DDR3 controller 14 output is connected to the image resolution setting module 15.

[0034] The output terminal of the digital recognition top layer 12 is connected to the LCD display 32. The output terminal of the digital recognition top layer 12 is connected to the digital tube display 33 through the digital tube driver 34. The DDR3 controller 14 is connected to the DDR3 peripheral 17. The OV564O driver 16 is connected to the camera 31.

[0035] The input and output terminals of the voice recognition module 2 are connected to the FPGA main control chip 1. The user triggers the voice recognition module 2 with a wake word, and the voice recognition module 2 responds to realize the lighting control of the illuminator 54.

[0036] The image recognition module 3 includes a camera 31 and an image display 32. The output of the camera 31 is connected to the FPGA main control chip 1, and the output of the camera 31 is connected to the input of the image display 32.

[0037] The image data processing process is existing technology. After the camera 31 captures the image, the data is written to the DDR3 controller 14 by the OV564O driver 16. The LCD top layer 13 reads the data from the DDR3 controller 14 and performs image processing through the digital recognition top layer 12. The image is then displayed by the digital tube driven by the digital tube or by the LCD display after passing through the digital recognition top layer 12.

[0038] See attached document Figure 2 The top-level digital recognition module 12 includes rgb2ycbcr: rgb2ycbcr is the RGB to YCbcr conversion module, binarizatiowei is the image binarization module, digital_recognition is the image feature value matching module, and projection is the image edge detection module.

[0039] Specifically, the rgb2ycbcr module first converts RGB to YCbCr, then performs binarization processing through binarizatiowei to obtain a binary image. The binary image is then subjected to horizontal and vertical projection, i.e., image segmentation, to obtain the horizontal and vertical boundaries of each digit. The digit boundary information is then sent to the feature recognition module for feature matching, thereby recognizing the digits in the image. The top-level digit recognition module 12 is an existing module, and its image processing can be achieved through existing methods.

[0040] The motor control module 4 includes a robotic arm servo unit 41 and a trolley drive motor unit 42. The FPGA main control chip 1 is connected to both the robotic arm servo unit 41 and the trolley drive motor unit 42.

[0041] The trolley drive motor unit 42 is connected to the automatic obstacle avoidance module 43. The automatic obstacle avoidance module 43 includes four ranging sensors set on the front of the trolley. The four ranging sensors are existing infrared sensors. The ranging sensors are connected to the FPGA main control chip 1. The FPGA main control chip 1 controls the movement of the trolley drive motor according to the feedback distance transmitted by the sensors.

[0042] The environmental detection module 5 includes an ambient light monitoring unit 51, an ambient temperature monitoring unit 52, and an ambient humidity monitoring unit 53. The ambient light monitoring unit 51 uses an existing TEMT6000 ambient light sensor, the ambient temperature monitoring unit 52 uses an existing KTY84 temperature sensor, and the ambient humidity monitoring unit 53 uses an existing Sensirion SHT4x humidity sensor. The output of the environmental detection module 5 is connected to the FPGA main control chip 1. After receiving the data from the environmental detection module 5, the FPGA main control chip 1 displays it through the ambient temperature and humidity display 55. The ambient temperature monitoring unit 52 and the ambient humidity monitoring unit 53 detect the temperature and humidity of the air in the environment. The temperature sensor and the humidity sensor are located on one side of the vehicle.

[0043] The outputs of the ambient temperature monitoring unit 52 and the ambient humidity monitoring unit 53 are connected to the ambient temperature and humidity display 55. The output of the ambient light monitoring unit 51 is connected to the illuminator 54. When the ambient temperature monitoring unit 52 detects that the current ambient light is too low, the FPGA main control chip 1 turns on the robot's built-in illuminator 54, which is located on the top of the vehicle.

[0044] The temperature and humidity monitoring modules are mainly controlled by voice signals and change with the voice signals, while the ambient light monitoring module is affected by the current ambient light intensity and can also be controlled by external voice signals.

[0045] Although the specific embodiments of the present utility model have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present utility model. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solution of the present utility model are still within the scope of protection of the present utility model.

Claims

1. An FPGA-based robotic system, characterized by, It includes an FPGA main control chip, and the FPGA main control chip connects to a voice recognition module, an image recognition module, a motor control module, and an environmental detection module; The input and output terminals of the voice recognition module are connected to the FPGA main control chip; The image recognition module includes a camera and an image display, with the camera output connected to the FPGA main control chip; The motor control module includes a robotic arm servo unit and a car drive motor unit, and the FPGA main control chip is connected to both the robotic arm servo unit and the car drive motor unit. The environmental monitoring module includes an ambient light monitoring unit, an ambient temperature monitoring unit, and an ambient humidity monitoring unit. The output of the environmental monitoring module is connected to the FPGA main control chip.

2. The FPGA-based robot system of claim 1, wherein, The FPGA main control chip includes a clock module, a digital recognition top layer, an LCD top layer, a DDR3 controller, an image resolution setting module, and an OV564O driver.

3. The FPGA-based robot system of claim 1, wherein, The clock module output is simultaneously connected to the OV564O driver, the top layer of the LCD, the image resolution setting module, and the DDR3 controller. The output of the top layer of the LCD is connected to the digital recognition top layer, and the output of the DDR3 controller is connected to the image resolution setting module.

4. The FPGA-based robot system of claim 2, wherein, The digital recognition top-level output terminal is connected to an LCD display, and the digital recognition top-level output terminal is connected to a digital tube display via a digital tube driver.

5. The FPGA-based robot system of claim 1, wherein, The DDR3 controller communicates with DDR3 peripherals.

6. The FPGA-based robot system of claim 1, wherein, The 0V564O driver communicates with the camera.

7. The FPGA-based robot system of claim 1, wherein, The camera output is connected to the image display input.

8. The FPGA-based robot system of claim 1, wherein, The vehicle's drive motor unit is connected to the automatic obstacle avoidance module.

9. The FPGA-based robot system of claim 1, wherein, The output terminals of the ambient temperature monitoring unit and the ambient humidity monitoring unit are connected to the ambient temperature and humidity display.

10. The FPGA-based robot system of claim 1, wherein, The output of the ambient light monitoring unit is connected to a illuminator.

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