Array substrate, display panel and display device

Abstract

This disclosure provides an array substrate, a display panel, and a display device, relating to the field of display technology, for improving the lifespan of a display device. The array substrate includes a substrate and a plurality of thin-film transistors (TFTs) located on one side of the substrate. The plurality of TFTs includes a first TFT and a second TFT. The first TFT includes a first electrode region, a first channel region, and a second electrode region located in a first active layer. The second TFT includes a third electrode region, a second channel region, and a fourth electrode region located in a second active layer. The first electrode region, the first channel region, and the second electrode region are arranged along a first direction, and the third electrode region, the second channel region, and the fourth electrode region are arranged along a second direction. The first and second directions are parallel to the substrate and intersect or are parallel to it. The dimension of the first channel region in the first direction is larger than the dimension of the second channel region in the second direction. The above-described array substrate is used in a display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in mobile phones, tablets, laptops, and automotive displays. The display panel of an LCD device contains multiple thin-film transistors (TFTs), and the electrical performance requirements for TFTs with different functions vary. Utility Model Content

[0003] The purpose of this disclosure is to provide an array substrate, a display panel, and a display device for optimizing the electrical performance of thin-film transistors and improving the lifespan of the display device.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, an array substrate is provided, comprising: a substrate and a plurality of thin-film transistors arranged in an array on one side of the substrate; the plurality of thin-film transistors include: a first thin-film transistor and a second thin-film transistor; the array substrate further includes: a first active layer and a second active layer, the first thin-film transistor including: a first electrode region, a first channel region and a second electrode region located in the first active layer and connected in sequence, the second thin-film transistor including: a third electrode region, a second channel region and a fourth electrode region located in the second active layer and connected in sequence; the first electrode region, the first channel region and the second electrode region are arranged along a first direction, the third electrode region, the second channel region and the fourth electrode region are arranged along a second direction, the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect or are parallel; wherein, the size of the first channel region in the first direction is larger than the size of the second channel region in the second direction.

[0006] In the aforementioned array substrate, by setting the size of the first channel region in the first direction to be larger than the size of the second channel region in the second direction, the threshold voltage of the first thin-film transistor can be adjusted to be greater than the threshold voltage of the second thin-film transistor. This allows the first and second thin-film transistors to be used in different circuits in the array substrate. For example, the first thin-film transistor can be used in a pixel driving circuit, and the second thin-film transistor can be used in a gate driving circuit. This allows for targeted optimization of the electrical performance of the thin-film transistors and improvement of product lifespan.

[0007] In some embodiments, the size of the first channel region in the first direction ranges from 5 μm to 8 μm; and / or, the size of the second channel region in the second direction ranges from 5 μm to 7 μm.

[0008] In some embodiments, the dimension of the first channel region in the fourth direction is smaller than the dimension of the second channel region in the fifth direction; the fourth direction and the fifth direction are parallel to the substrate, and the fourth direction is perpendicular to the first direction, and the fifth direction is perpendicular to the second direction.

[0009] In some embodiments, the array substrate further includes: a light-shielding layer located on the side of the thin-film transistor near the substrate, the light-shielding layer including: a first light-shielding pattern and a second light-shielding pattern; in a normal projection facing the substrate, the first light-shielding pattern covers the first electrode region, the first channel region and the second electrode region, the second light-shielding pattern covers the second channel region, and the second light-shielding pattern does not overlap with the third electrode region and the fourth electrode region.

[0010] In some embodiments, the threshold voltage of the first thin-film transistor is greater than the threshold voltage of the second thin-film transistor.

[0011] In some embodiments, the array substrate further includes: a first gate layer and a second gate layer located on one side of the substrate, the first gate layer including a first gate pattern of the first thin-film transistor, and the second gate layer including a second gate pattern of the second thin-film transistor; in an orthographic projection facing the substrate, the first gate pattern overlaps with the first channel region, and the second gate pattern overlaps with the second channel region; the first gate layer is located on the side of the first channel region closer to the substrate; and / or, the second gate layer is located on the side of the second channel region away from the substrate.

[0012] In some embodiments, the array substrate further includes: a first dielectric layer and a gate insulating layer; the first dielectric layer is located between the first active layer and the first gate layer; the gate insulating layer is located between the second active layer and the second gate layer; wherein the thickness of the portion of the first dielectric layer located between the first gate pattern and the first channel region is greater than the thickness of the portion of the gate insulating layer located between the second gate pattern and the second channel region.

[0013] In some embodiments, the thickness of the portion of the first dielectric layer located between the first gate pattern and the first channel region differs from the thickness of the portion of the gate insulating layer located between the second gate pattern and the second channel region by a range of 2000 angstroms to 4000 angstroms.

[0014] In some embodiments, a plurality of second thin-film transistor arrays are arranged, a plurality of second channel regions are sequentially connected along the second direction, and a plurality of second channel regions are sequentially spaced along the fifth direction.

[0015] In some embodiments, the first active layer and the second active layer are disposed on the same layer.

[0016] In some embodiments, the plurality of thin-film transistors further includes: a third thin-film transistor; the array substrate further includes: a third active layer, the third thin-film transistor including: a fifth electrode region, a third channel region, and a sixth electrode region located in the third active layer and connected in sequence, the fifth electrode region, the third channel region, and the sixth electrode region being arranged along a third direction, the third direction being parallel to the substrate, and the third direction intersecting or being parallel to the second direction; wherein, the dimension of the third channel region in the third direction is less than or equal to the dimension of the second channel region in the second direction.

[0017] In some embodiments, the size of the third channel region in the third direction ranges from 4 μm to 7 μm.

[0018] In some embodiments, the dimension of the third channel region in the sixth direction is approximately equal to the dimension of the second channel region in the fifth direction; the sixth direction is parallel to the substrate and perpendicular to the third direction.

[0019] In some embodiments, the array substrate further includes: a light-shielding layer located on the side of the third thin-film transistor near the substrate, the light-shielding layer including: a third light-shielding pattern; in an orthographic projection facing the substrate, the third channel region covers the third light-shielding pattern, and a portion of the boundary of the third channel region extending along a sixth direction is spaced from a portion of the boundary of the third light-shielding pattern extending along the sixth direction.

[0020] In some embodiments, in an orthographic projection facing the substrate, the distance between the portion of the boundary of the third channel region extending along the sixth direction and the portion of the boundary of the third light-shielding pattern extending along the sixth direction ranges from 1 μm to 3 μm.

[0021] In some embodiments, the threshold voltage of the third thin-film transistor is less than the threshold voltage of the second thin-film transistor.

[0022] In some embodiments, the array substrate further includes a third gate layer located on one side of the substrate, the third gate layer including a third gate pattern; in an orthographic projection facing the substrate, the third gate pattern overlaps with the third channel region; the third gate layer is located on the side of the third channel region away from the substrate.

[0023] In some embodiments, a plurality of the third thin-film transistor arrays are arranged, a plurality of the third channel regions are sequentially connected along the third direction, and a plurality of the third channel regions are sequentially spaced along the sixth direction.

[0024] In some embodiments, the first active layer, the second active layer, and the third active layer are disposed on the same layer; and / or

[0025] Alternatively, the second gate layer and the third gate layer may be disposed on the same layer.

[0026] In some embodiments, the array substrate further includes: a pixel driving circuit, a gate driving circuit, and a multiplexer; the array substrate satisfies at least one of the following: the pixel driving circuit includes the first thin-film transistor; the gate driving circuit includes the second thin-film transistor; the multiplexer includes the third thin-film transistor.

[0027] On the other hand, a display panel is provided, the display panel comprising: an array substrate, an opposing substrate, and a liquid crystal layer as described in any of the above embodiments, wherein the opposing substrate is disposed opposite to and spaced apart from the array substrate, and the liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0028] In another aspect, a display panel is provided, the display panel comprising: an array substrate as described in any of the above embodiments and a plurality of light-emitting devices, the plurality of light-emitting devices being disposed on the array substrate, and the array substrate being used to drive the plurality of light-emitting devices to emit light.

[0029] In another aspect, a display device is provided, the display device comprising: a display panel as described in any of the above embodiments and a driver chip, the driver chip being used to drive the display panel to display.

[0030] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0033] Figure 1 This is a structural diagram of a display device provided according to some embodiments of the present disclosure;

[0034] Figure 2 This is a structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0035] Figure 3 This is a structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0036] Figure 4 According to Figure 3 The provided cross-sectional view of the array substrate along section line AA;

[0037] Figure 5 This is a structural diagram of another array substrate provided according to some embodiments of the present disclosure;

[0038] Figure 6 According to Figure 5 Enlarged view of point D on the provided array substrate;

[0039] Figure 7 According to Figure 6 The provided cross-sectional view of the array substrate along section line BB;

[0040] Figure 8 A graph showing the basic characteristics of a thin-film transistor provided according to some embodiments of this disclosure;

[0041] Figure 9 This is a structural diagram of another array substrate provided according to some embodiments of the present disclosure;

[0042] Figure 10 According to Figure 9 Enlarged view of point E on the provided array substrate;

[0043] Figure 11 According to Figure 10 A cross-sectional view of the provided array substrate along section line CC;

[0044] Figure 12 This is a structural diagram of another display panel provided according to some embodiments of the present disclosure. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0051] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0052] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] Some embodiments of this disclosure provide a display device 2000, which can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones (e.g., cell phones), wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The following is an illustration using the display device 2000 as an example of a mobile phone.

[0055] For example, the display device 2000 can be an electroluminescent display device or a photoluminescent display device. When the display device 2000 is an electroluminescent display device, it can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). When the display device 2000 is a photoluminescent display device, it can be a quantum dot photoluminescent display device. The following uses an OLED display device as an example to illustrate some embodiments of this disclosure; however, the implementation of this disclosure includes, but is not limited to, these embodiments, and any other display device can be considered as long as the same technical concept is applied.

[0056] Please continue reading. Figure 1 The aforementioned display device 2000 includes a display panel 1000.

[0057] like Figure 2 As shown, the display panel 1000 includes an array substrate 100, which includes a plurality of thin-film transistors 10 arranged in an array. The display panel 1000 also includes a plurality of light-emitting devices 200, and the array substrate 100 is used to drive the plurality of light-emitting devices 200 to emit light.

[0058] For example, such as Figure 2As shown, the array substrate 100 also includes multiple scan signal lines GL and multiple data signal lines DL, which are connected to multiple thin-film transistors 10. The smallest area defined by the intersection of the multiple scan signal lines GL and multiple data signal lines DL is a sub-pixel area S, and a sub-pixel P is provided in the sub-pixel area S. The sub-pixel P is the smallest unit for display by the display panel 1000.

[0059] like Figure 2 As shown, in the display panel 1000, the requirements for electrical characteristics of thin-film transistors 10 with different functions vary significantly.

[0060] For example, the display panel 1000 includes a pixel driving circuit, a gate driving circuit, and a multiplexer, wherein the thin-film transistors 10 in the pixel driving circuit, the gate driving circuit, and the multiplexer have different requirements for electrical characteristics.

[0061] For example, in the pixel driving circuit, the thin-film transistor 10, acting as a switch, requires a high threshold voltage and excellent negative bias temperature illumination stress (NBTIS) characteristics to ensure the stability of the pixel signal. The threshold voltage of the thin-film transistor 10 in the gate driving circuit needs to be higher than that of the thin-film transistor 10 in the multiplexer to ensure a longer lifespan for the display panel 1000. The threshold voltage of the thin-film transistor 10 in the multiplexer is generally lower, and it needs to have good positive bias temperature stress (PBTS) characteristics to improve signal transmission speed. Here, the threshold voltage is the gate voltage that enables the formation of a channel.

[0062] In some embodiments, since the thin film transistors 10 of the display panel 1000 are formed using the same structure and process parameters, it is difficult to simultaneously meet the different electrical performance requirements of multiple thin film transistors 10, resulting in a reduced lifespan of the display panel 1000 or an increased process complexity.

[0063] Based on this, such as Figure 2 , Figure 3 , Figure 5 and Figure 6 As shown, an embodiment of this disclosure provides an array substrate 100, which includes a substrate 101 and a plurality of thin-film transistors 10 arranged in an array on one side of the substrate 101. The array substrate 100 further includes a first active layer 12a and a second active layer 12b.

[0064] For example, substrate 101 may be a glass substrate, a quartz substrate or a plastic substrate.

[0065] For example, the materials of the first active layer 12a and the second active layer 12b are independently selected from amorphous silicon (a-Si), metal oxide, or low-temperature polycrystalline silicon (LTPS). In other embodiments, the materials of the first active layer 12a and the second active layer 12b are the same, and the first active layer 12a and the second active layer 12b are disposed in the same layer. Distributed in the same layer means that the same film deposition process is used to form a film layer for forming a specific pattern, and then the layer structure is formed in one patterning process using the same mask. That is, one patterning process corresponds to one mask. Depending on the specific pattern, one patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0066] The array substrate 100 further includes: a plurality of thin-film transistors 10 arranged in an array; the plurality of thin-film transistors 10 include: a first thin-film transistor 11 and a second thin-film transistor 12, the first thin-film transistor 11 including a first electrode region 121, a first channel region 122 and a second electrode region 123 located in the first active layer 12a, and the second thin-film transistor 12 including a third electrode region 124, a second channel region 125 and a fourth electrode region 126 located in the second active layer 12b.

[0067] The first electrode region 121, the first channel region 122, and the second electrode region 123 are arranged along the first direction X1, and the third electrode region 124, the second channel region 125, and the fourth electrode region 126 are arranged along the second direction X2. The first direction X1 and the second direction X2 are parallel to the substrate 101, and the first direction X1 and the second direction X2 intersect or are parallel.

[0068] For example, the first direction X1 and the second direction X2 intersect, or the first direction X1 and the second direction X2 are perpendicular.

[0069] It should be noted that the arrangement direction of the two electrode regions and the channel region of the thin-film transistor 10 can be represented as direction X, which includes: a first direction X1, a second direction X2, and a third direction X3 (e.g., ...). Figure 10 (As shown).

[0070] The dimension d1 of the first channel region 122 in the first direction X1 is greater than the dimension d2 of the second channel region 125 in the second direction X2, that is, d1>d2.

[0071] The dimension d1 of the first channel region 122 in the first direction X1 is the length of the first channel region 122, and the dimension d2 of the second channel region 125 in the second direction X2 is the length of the second channel region 125.

[0072] For example, such as Figure 3 and Figure 6 As shown, the array substrate 100 further includes a first gate layer 14a and a second gate layer 14b. The first gate layer 14a includes a first scan signal line GL1, and the second gate layer 14b includes a second scan signal line GL1. In a projection onto the substrate 101, the region where the first active layer 12a overlaps with the first scan signal line GL1 is the first channel region 122, and the region where the second active layer 12b overlaps with the second scan signal line GL2 is the second channel region 125. The length of the first channel region 122 can be understood as the width of the first scan signal line GL1, and the length of the second channel region 125 can be understood as the width of the second scan signal line GL2.

[0073] The length of the channel region of the thin-film transistor 10 affects its threshold voltage. For example, the longer the channel region of the thin-film transistor 10, the higher its threshold voltage can be; however, the relationship is not entirely linear. When the channel region becomes shorter, a narrow-channel effect occurs. The narrow-channel effect means that when the channel is very small, the electric field between the source and drain of the thin-film transistor 10 penetrates into the channel region, weakening the gate's control over the underlying potential, and causing Vth to become more negative or decrease in value.

[0074] Meanwhile, due to the phenomenon of photogenerated carriers, the carriers are more easily excited after the channel length is shortened, which leads to a deterioration in stability under negative bias temperature illumination stress.

[0075] Therefore, by setting the size d1 of the first channel region 122 in the first direction X1 to be greater than the size d2 of the second channel region 125 in the second direction X2, the threshold voltage of the first thin-film transistor 11 can be adjusted to be greater than the threshold voltage of the second thin-film transistor 12. This allows the first thin-film transistor 11 and the second thin-film transistor 12 to be used in different circuits in the array substrate 100. For example, the first thin-film transistor 11 can be used in a pixel driving circuit, and the second thin-film transistor 12 can be used in a gate driving circuit. This is to specifically optimize the electrical performance of the thin-film transistor 10 and improve the product's lifespan.

[0076] In other embodiments, such as Figure 3 and Figure 6 As shown, the dimension d1 of the first channel region 122 in the first direction X1 can be equal to the dimension d2 of the second channel region 125 in the second direction X2, that is, d1 = d2.

[0077] By setting the size d1 of the first channel region 122 in the first direction X1 to be equal to the size d2 of the second channel region 125 in the second direction X2, the threshold voltage of the first thin film transistor 11 can also be made greater than the threshold voltage of the second thin film transistor 12 by setting other structural parameters of the first thin film transistor 11 and the second thin film transistor 12.

[0078] For example, other structural parameters include: the size of the light-shielding pattern relative to the channel region, and the thickness of the insulating layer between the active layer and the gate layer that overlap in the vertical substrate direction. The effects of the size of the light-shielding pattern relative to the channel region and the thickness of the insulating layer between the active layer and the gate layer that overlap in the vertical substrate direction on the threshold voltage of the thin-film transistor 10 will be discussed later and will not be elaborated here.

[0079] In some embodiments, such as Figure 3 As shown, the first thin-film transistor 11 is used in the pixel driving circuit, and the size d1 of the first channel region 122 in the first direction X1 ranges from 5μm to 8μm.

[0080] For example, the size d1 of the first channel region 122 in the first direction X1 is 5μm, 5.3μm, 5.5μm, 5.8μm, 6μm, 6.3μm, 6.6μm, 6.8μm, 7μm, 7.3μm, 7.5μm, 7.8μm or 8μm, etc., and there is no limitation here.

[0081] By setting the size d1 of the first channel region 122 in the first direction X1 to be in the range of 5μm to 8μm, the first thin film transistor 11 has a high threshold voltage, and the first thin film transistor 11 can be used in the pixel driving circuit to ensure the stability of the pixel signal.

[0082] In some embodiments, such as Figure 6 As shown, the size d2 of the second channel region 125 in the second direction X2 ranges from 5μm to 7μm.

[0083] For example, the size d2 of the second channel region 125 in the second direction X2 is 5μm, 5.2μm, 5.4μm, 5.6μm, 5.8μm, 6μm, 6.2μm, 6.4μm, 6.6μm, 6.8μm, 6.9μm or 7μm, etc., and there is no limitation here.

[0084] By setting the size d2 of the second channel region 125 in the second direction X2 to be 5μm to 7μm, the second thin film transistor 12 has better balanced driving capability and reliability, so that the second thin film transistor 12 can be used in the gate driving circuit.

[0085] The following is an exemplary description of the film stacking structure in the region where the first thin-film transistor 11 of the array substrate 100 is located.

[0086] In some embodiments, such as Figure 3 and Figure 4 As shown, Figure 3 This is a structural diagram of an array substrate 100 provided according to some embodiments of the present disclosure. Figure 4 According to Figure 3 The provided array substrate 100 is a cross-sectional view along section line AA. The array substrate 100 may include: a light-shielding layer 103, a gate insulating layer 106, a first gate layer 14a, a first dielectric layer 107, a first active layer 12a, an interlayer dielectric layer 108, and a source / drain metal layer 105 disposed on one side of the substrate 101.

[0087] For example, the first gate layer 14a includes a first gate pattern 141, which is electrically connected to the first scan signal line GL1.

[0088] For example, the first thin-film transistor 11 includes a gate, a source, and a drain. The first gate pattern 141 is the gate of the first thin-film transistor 11. The source and drain of the first thin-film transistor 11 are located in the source-drain metal layer 105, and the source and drain are connected to the first active layer 12a through vias penetrating the interlayer dielectric layer 108. For example, the source is connected to the first electrode region 121 of the first thin-film transistor 11 through a via penetrating the interlayer dielectric layer 108, and the drain is connected to the second electrode region 123 of the first thin-film transistor 11 through another via penetrating the interlayer dielectric layer 108.

[0089] When a certain voltage is applied to the gate of the first thin-film transistor 11, the first channel region 122 is turned on, so that a path is formed between the source and drain of the first thin-film transistor 11, thereby turning on the first thin-film transistor 11.

[0090] In this embodiment, the first gate layer 14a is located on the side of the first channel region 122 near the substrate 101.

[0091] In other words, the first thin-film transistor 11 adopts a back channel etch (BCE) structure for the thin-film transistor 10, which can further improve the threshold voltage of the first thin-film transistor 11.

[0092] The following is an exemplary description of the film stacking structure in the region where the second thin-film transistor 12 of the array substrate 100 is located.

[0093] In some embodiments, such as Figure 6 and Figure 7 As shown, Figure 7 According to Figure 6The provided cross-sectional view of the array substrate 100 along the cross-section line BB shows that the array substrate 100 may include: a light-shielding layer 103, a first dielectric layer 107, a second active layer 12b, a gate insulating layer 106, a second gate layer 14b, an interlayer dielectric layer 108, and a source / drain metal layer 105 disposed on one side of the substrate 101.

[0094] For example, the second gate layer 14b includes a second gate pattern 142, which is electrically connected to the second scan signal line GL2.

[0095] It should be noted that in the film stacking structure of the region where the first thin film transistor 11 is located and in the film stacking structure of the region where the second thin film transistor 12 is located on the array substrate 100, the light-shielding layer 103 can be located in the same layer or in different layers, the first dielectric layer 107 can be located in the same layer or in different layers, the gate insulating layer 106 can be located in the same layer or in different layers, the interlayer dielectric layer 108 can be located in the same layer or in different layers, and the source / drain metal layer 105 can be located in the same layer or in different layers. There are no restrictions here.

[0096] For example, the second thin-film transistor 12 includes a gate, a source, and a drain. The second gate pattern 142 is the gate of the second thin-film transistor 12. The source and drain of the second thin-film transistor 12 are located in the source-drain metal layer 105. The source and drain are connected to the second active layer 12b through vias penetrating the interlayer dielectric layer 108 and the gate insulating layer 106. For example, the source is connected to the third electrode region 124 through a via penetrating the interlayer dielectric layer 108 and the gate insulating layer 106, and the drain is connected to the fourth electrode region 126 through another via penetrating the interlayer dielectric layer 108 and the gate insulating layer 106.

[0097] When a certain voltage is applied to the gate of the second thin-film transistor 12, the channel region 122 of the second thin-film transistor 12 is turned on, so that a path is formed between the source and drain of the second thin-film transistor 12, thereby turning on the second thin-film transistor 12.

[0098] In this embodiment, such as Figure 7 As shown, the second gate layer 14b is located on the side of the second channel region 125 away from the substrate 101.

[0099] In other words, the second thin-film transistor 12 adopts a top-gate structure, which can optimize the carrier mobility of the second thin-film transistor 12 through high-precision gate control and improve the resistance to bias stress of the second thin-film transistor 12.

[0100] In some embodiments, such as Figure 3 and Figure 6As shown, the dimension d11 of the first channel region 122 in the fourth direction Y1 is smaller than the dimension d12 of the second channel region 125 in the fifth direction Y2, that is, d11 < d12. Here, the fourth direction Y1 is parallel to the substrate 101, and the fourth direction Y1 is perpendicular to the first direction X1; the fifth direction Y2 is parallel to the substrate 101, and the fifth direction Y2 is perpendicular to the second direction X2.

[0101] It should be noted that the direction perpendicular to the arrangement directions of the two pole regions and the channel region of the thin film transistor 10 can be referred to as the direction Y, and the direction Y includes: the fourth direction Y1, the fifth direction Y2, and the sixth direction Y3 (as Figure 10 shown).

[0102] The dimension d11 of the first channel region 122 in the fourth direction Y1 can be understood as the width of the first thin film transistor 11, and the dimension d12 of the second channel region 125 in the fifth direction Y2 can be understood as the width of the second thin film transistor 12.

[0103] Since the threshold voltage of the first thin film transistor 11 is relatively large, the first thin film transistor 11 can be used in the pixel driving circuit to ensure the stability of the pixel signal. By setting the dimension d11 of the first channel region 122 in the fourth direction Y1 to be smaller than the dimension d12 of the second channel region 125 in the fifth direction Y2, the dimension d11 of the first channel region 122 in the fourth direction Y1 is relatively small, which can reduce the size of the first thin film transistor 11 and improve the pixel density of the display panel 1000.

[0104] In some embodiments, as Figures 3-7 shown, the light shielding layer 103 includes: a first light shielding pattern 131 and a second light shielding pattern 132. In the orthographic projection facing the substrate 101, the first light shielding pattern 131 covers the first pole region 121, the first channel region 122, and the second pole region 123, the second light shielding pattern 132 covers the second channel region 125, and the second light shielding pattern 132 has no overlap with the third pole region 124 and the fourth pole region 126.

[0105] Exemplarily, the light shielding layer 103 can be connected to a fixed potential to shield the influence of peripheral stray charges on the thin film transistor 10.

[0106] Exemplarily, in the orthographic projection facing the substrate 101, there is a spacing d3 between the part of the boundary L31 of the first channel region 122 extending along the fourth direction Y1 and the part of the boundary L11 of the first light shielding pattern 131 extending along the fourth direction Y1.

[0107] For example, in the orthographic projection facing the substrate 101, the first light-shielding pattern 131 not only covers the first pole region 121, the first channel region 122 and the second pole region 123, but also has a gap between the portion of the boundary L11 of the first light-shielding pattern 131 extending along the first direction X1 and the portion of the boundary L2 of the first pole region 121, the channel region 122 and the second pole region 123 extending along the first direction X1.

[0108] By covering the first electrode region 121, the first channel region 122, and the second electrode region 123 with the first light-shielding pattern 131, the threshold voltage of the first thin-film transistor 11 can be increased, the leakage current caused by light can be reduced, the stability of the first thin-film transistor 11 can be enhanced, and the NBTIS characteristics of the first thin-film transistor 11 can be optimized.

[0109] For example, in an orthographic projection facing the substrate 101, the portion of the boundary L12 of the second light-shielding pattern 132 extending along the fifth direction Y2 coincides with the portion of the boundary L32 of the second channel region 125 extending along the fifth direction Y2.

[0110] By setting the second light-shielding pattern 132 in the orthographic projection facing the substrate 101, covering the second channel region 125, and without overlapping with the third pole region 124 and the fourth pole region 126, the increase of parasitic capacitance can be effectively avoided, and the consistency of the transmitted signal of the second thin film transistor 12 can be maintained.

[0111] In other words, the size of the light-shielding pattern affects the threshold voltage of the thin-film transistor 10. Specifically, the threshold voltage of the thin-film transistor 10 can be adjusted by setting different spacing d3 between the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the thin-film transistor 10 channel region boundary L3 extending in the Y direction. The following experimental data is provided. For example, the light-shielding pattern includes: a first light-shielding pattern 131, a second light-shielding pattern 132 (e.g., ...). Figure 7 (as shown) and the third light-shielding pattern 133 (as shown) Figure 11 (As shown).

[0112] Figure 8 This is a basic characteristic graph of the thin-film transistor 10 provided according to some embodiments of the present disclosure. The horizontal axis represents the gate-source voltage of the thin-film transistor 10, denoted as Vgs, in V; the vertical axis represents the logarithmic coordinate of the source-drain current of the thin-film transistor 10, denoted as Ids, in A. The distance d3 between the boundary L1 of the light-shielding pattern and the boundary L3 of the channel region of the thin-film transistor 10 represented by Examples 1, 2, 3, and 4 is different.

[0113] In Example 1, the distance d3 between the portion of the boundary L1 of the light-shielding pattern extending in the Y direction and the portion of the boundary L3 of the channel region of the thin-film transistor 10 extending in the Y direction is 2 μm.

[0114] In Example 2, the distance d3 between the portion of the boundary L1 of the light-shielding pattern extending in the Y direction and the portion of the boundary L3 of the channel region of the thin-film transistor 10 extending in the Y direction is 1 μm.

[0115] In Example 3, the distance d3 between the portion of the boundary L1 of the light-shielding pattern extending in the Y direction and the portion of the boundary L3 of the channel region of the thin-film transistor 10 extending in the Y direction is 0 μm.

[0116] In Example 4, the distance d3 between the portion of the boundary L1 of the light-shielding pattern extending in the Y direction and the portion of the boundary L3 of the channel region of the thin-film transistor 10 extending in the Y direction is -1 μm.

[0117] It should be noted that when the distance d3 between the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the channel region boundary L3 of the thin-film transistor 10 extending in the Y direction is positive, it indicates that the light-shielding pattern covers the channel region of the thin-film transistor 10 in the orthogonal projection facing the substrate 101. When the distance d3 between the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the channel region boundary L3 of the thin-film transistor 10 extending in the Y direction is 0, it indicates that the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the channel region boundary L3 of the thin-film transistor 10 extending in the Y direction coincide in the orthogonal projection facing the substrate 101. When the distance d3 between the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the channel region boundary L3 of the thin-film transistor 10 extending in the Y direction is negative, it indicates that the channel region of the thin-film transistor 10 covers the light-shielding pattern in the orthogonal projection facing the substrate 101.

[0118] Combination Figure 4 , Figure 7 and Figure 11 ,Depend on Figure 8 As can be seen, the threshold voltage of the thin-film transistor 10 provided in Example 1 is approximately -1V, the threshold voltage of the thin-film transistor 10 provided in Example 2 is approximately -3V, the threshold voltage of the thin-film transistor 10 provided in Example 3 is approximately -7V, and the threshold voltage of the thin-film transistor 10 provided in Example 4 is approximately -17V. The thin-film transistor 10 provided in Example 1 has the highest threshold voltage.

[0119] That is, through Figure 8 It can be seen that the larger the distance d3 between the portion of the light-shielding pattern boundary L1 extending in the Y direction and the portion of the channel region boundary L3 of the thin-film transistor 10 extending in the Y direction, the larger the threshold voltage of the thin-film transistor 10.

[0120] Therefore, by setting the first light-shielding pattern 131 to cover the first pole region 121, the first channel region 122 and the second pole region 123, and the second light-shielding pattern 132 to cover the second channel region 125, and the second light-shielding pattern 132 does not overlap with the third pole region 124 and the fourth pole region 126, the threshold voltage of the first thin film transistor 11 is greater than the threshold voltage of the second thin film transistor 12.

[0121] In some embodiments, such as Figure 4 and Figure 7 As shown, the array substrate 100 includes: a first dielectric layer 107 and a gate insulating layer 106; in the first thin film transistor 11, the first dielectric layer 107 is located between the first active layer 12a and the first gate layer 14a; in the second thin film transistor 12, the gate insulating layer 106 is located between the second active layer 12b and the second gate layer 14b; wherein, the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122 is greater than the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125, i.e., d4>d5.

[0122] When the insulating layer between the active layer and the gate layer is thicker, the gate's control over the channel region of the thin-film transistor 10 can be reduced, thereby increasing the threshold voltage of the thin-film transistor 10. Therefore, by setting the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122 to be greater than the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125, the threshold voltage of the first thin-film transistor 11 can be further increased to ensure the stability of the pixel signal.

[0123] At the same time, the threshold voltage of the second thin film transistor 12 is made lower than the threshold voltage of the first thin film transistor 11 to balance the driving capability of the second thin film transistor 12.

[0124] In some embodiments, such as Figure 4 and Figure 7 As shown, the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122, and the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125, have a difference range of 2000 angstroms to 4000 angstroms.

[0125] For example, the difference between the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122 and the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125 is 2000 angstroms, 2100 angstroms, 2300 angstroms, 2500 angstroms, 2700 angstroms, 2800 angstroms, 3000 angstroms, 3100 angstroms, 3300 angstroms, 3500 angstroms, 3600 angstroms, 3800 angstroms, 3900 angstroms, or 4000 angstroms, etc., is not limited here.

[0126] For example, the thickness d6 of the first dielectric layer 107 ranges from 4000 angstroms to 5000 angstroms. For instance, the thickness d6 of the first dielectric layer 107 can be 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, 4500 angstroms, 4600 angstroms, 4700 angstroms, 4800 angstroms, 4900 angstroms, or 5000 angstroms, etc., and is not limited here. The thickness d6 of the first dielectric layer 107 minus the thickness of the first gate layer 14a equals the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122.

[0127] For example, the thickness d7 of the gate insulating layer 106 ranges from 1000 angstroms to 2000 angstroms. For instance, the thickness d7 of the gate insulating layer 106 can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms, or 2000 angstroms, etc., and is not limited here. The thickness d7 of the gate insulating layer 106 minus the thickness of the second active layer 12b equals the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125.

[0128] The threshold voltage of the first thin-film transistor 11 is increased by setting the difference between the thickness d4 of the portion of the first dielectric layer 107 located between the first gate pattern 141 and the first channel region 122 and the thickness d5 of the portion of the gate insulating layer 106 located between the second gate pattern 142 and the second channel region 125 to be in the range of 2000 angstroms to 4000 angstroms, and the threshold voltage of the second thin-film transistor 12 is made to be less than the threshold voltage of the first thin-film transistor 11.

[0129] By setting the length of the channel region of the thin-film transistor 10, the size difference of the light-shielding pattern relative to the channel region, and the thickness of the insulating layer between the active layer and the gate layer, the threshold voltage of the first thin-film transistor 11 is made greater than the threshold voltage of the second thin-film transistor 12. This allows the first thin-film transistor 11 and the second thin-film transistor 12 to be disposed in the same array substrate 100, thereby enabling the thin-film transistors 10 of the pixel driving circuit and the gate driving circuit in the array substrate 100 to have different electrical characteristics and improving the product lifespan.

[0130] In some embodiments, such as Figure 5 As shown, a plurality of second-type thin-film crystal 12-tube arrays are arranged, and a plurality of second channel regions 125 are connected sequentially along the second direction X2, and a plurality of second channel regions 125 are arranged sequentially at intervals along the fifth direction Y2.

[0131] In other words, multiple second-type thin-film crystals 12 are combined to form an interconnected transistor. The multiple second channel regions 125 of the transistor form the channel region of the transistor. The channel region has multiple branches extending in the longitudinal and transverse directions. This can reduce the heat dissipation of the second channel region 125 and effectively prevent the second thin-film transistor 12 from burning out due to excessive heat dissipation in the second channel region 125.

[0132] In some embodiments, such as Figure 6 , Figure 9 , Figure 10 and Figure 11 As shown, Figure 9 This is a structural diagram of another array substrate 100 provided according to some embodiments of the present disclosure. Figure 10 According to Figure 9 Enlarged view of point E on the provided array substrate. Figure 11 According to Figure 10 The provided array substrate 100 is shown in a cross-sectional view along section line CC. The plurality of thin film transistors 10 further include: a third thin film transistor 13. The array substrate 100 also includes: a third active layer 12c. The third thin film transistor 13 includes a fifth electrode region 127, a third channel region 128, and a sixth electrode region 129 located in the third active layer 12c and connected in sequence. The fifth electrode region 127, the third channel region 128, and the sixth electrode region 129 are arranged along a third direction X3. The third direction X3 is parallel to the substrate 101, and the third direction X3 intersects or is parallel to the second direction X2. The dimension d8 of the third channel region 128 in the third direction X3 is less than or equal to the dimension d2 of the second channel region 125 in the second direction X2, i.e., d8 ≤ d2.

[0133] For example, the dimension d8 of the third channel region 128 in the third direction X3 is the length of the third channel region 128, that is, the length of the third channel region 128 is less than or equal to the length of the second channel region 125.

[0134] The array includes a third thin-film transistor 13, and the third channel region 128 is configured such that its dimension d8 in the third direction X3 is less than or equal to the dimension d2 of the second channel region 125 in the second direction X2. Combined with the subsequent configuration of the third light-shielding pattern 133, the threshold voltage of the third thin-film transistor 13 is less than the threshold voltage of the second thin-film transistor 12. This allows the third thin-film transistor 13, the first thin-film transistor 11, and the second thin-film transistor 12 to be used in different circuits in the array substrate 100, thereby optimizing the electrical performance of the thin-film transistor 10 and improving the product's lifespan.

[0135] In some embodiments, at least two of the first active layer 12a, the second active layer 12b, and the third active layer 12c are made of metal oxide materials and / or metal nitride materials. The metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0136] Metallic nitride materials include, but are not limited to, zinc nitride, indium nitride, gallium nitride, tin nitride, cadmium nitride, aluminum nitride, germanium nitride, titanium nitride, silicon nitride, or combinations thereof.

[0137] The materials of the first active layer 12a, the second active layer 12b, and the third active layer 12c can be amorphous, partially crystalline, single-crystal, or polycrystalline, and the structure can also be a single-layer or multi-layer structure.

[0138] In some embodiments, such as Figure 10 and Figure 11 As shown, the size d8 of the third channel region 128 in the third direction X3 ranges from 4μm to 7μm.

[0139] For example, the size d8 of the third channel region 128 in the third direction X3 is 4μm, 4.2μm, 4.4μm, 4.6μm, 4.8μm, 5μm, 5.2μm, 5.4μm, 5.6μm, 5.8μm, 6μm, 6.2μm, 6.4μm, 6.6μm, 6.8μm, 6.9μm or 7μm, etc., and there is no limitation here.

[0140] By setting the size d8 of the third channel region 128 in the third direction X3 to be in the range of 4μm to 7μm, and ensuring that the size d8 of the third channel region 128 in the third direction X3 is less than or equal to the size d2 of the second channel region 125 in the second direction X2, the threshold voltage of the second thin-film transistor 12 is made greater than the threshold voltage of the third thin-film transistor 13. The application of a positive bias voltage causes electrons to accumulate in the channel region. Under thermal excitation, these electrons are captured by defect states at the interface or gate insulating layer 106. The smaller the length of the channel region, the smaller the potential barrier at the interface, and the less likely electrons are to be captured by defects. Therefore, the PBTS characteristics of the third thin-film transistor 13 can be improved.

[0141] In some embodiments, such as Figure 6 and Figure 10 As shown, the dimension d13 of the third channel region 128 in the sixth direction Y3 is approximately equal to the dimension d12 of the second channel region 125 in the fifth direction Y2; the sixth direction Y3 is parallel to the substrate 101 and perpendicular to the third direction X2.

[0142] The dimension d13 of the third channel region 128 in the sixth direction Y3 can be understood as the width of the third channel region 128. That is, the width of the third channel region 128 can be approximately equal to the width of the second thin-film transistor 12. Similarly, the dimension d11 of the first channel region 122 in the fourth direction Y1 is also smaller than the dimension d13 of the third channel region 128 in the sixth direction Y3, making the dimension d11 of the first channel region 122 relatively small. This reduces the size of the first thin-film transistor 11 and increases the pixel density of the display panel 1000.

[0143] The following is an exemplary description of the film stacking structure in the region where the third thin-film transistor 13 of the array substrate 100 is located.

[0144] In some embodiments, such as Figure 10 and Figure 11 As shown, the array substrate 100 may include: a light-shielding layer 103, a first dielectric layer 107, a third active layer 12c, a gate insulating layer 106, a third gate layer 14c, an interlayer dielectric layer 108, and a source / drain metal layer 105 disposed on one side of the substrate 101.

[0145] For example, the third gate layer 14c includes a third gate pattern 143 that overlaps with the third channel region 128 in a projection onto the substrate 101. The array substrate 100 also includes a third scan signal line GL3 located in the third gate layer 14c, and the third gate pattern 143 is electrically connected to the third scan signal line GL3.

[0146] For example, the third thin-film transistor 13 includes a gate, a source, and a drain. The third gate pattern 143 is the gate of the third thin-film transistor 13. The source and drain of the third thin-film transistor 13 are located in the source-drain metal layer 105. The source and drain are connected to the third active layer 12c through vias penetrating the interlayer dielectric layer 108 and the gate insulating layer 106. For example, the source is connected to the fifth electrode region 127 through a via penetrating the interlayer dielectric layer 108 and the gate insulating layer 106, and the drain is connected to the sixth electrode region 129 through another via penetrating the interlayer dielectric layer 108 and the gate insulating layer 106.

[0147] When a certain voltage is applied to the gate of the third thin-film transistor 13, the third channel region 128 is turned on, so that a path is formed between the source and drain of the third thin-film transistor 13, thereby turning on the third thin-film transistor 13.

[0148] In this embodiment, such as Figure 10 and Figure 11 As shown, the third gate layer 14c is located on the side of the third channel region 128 away from the substrate 101.

[0149] In other words, the third thin-film transistor 13 adopts a top-gate structure, which can optimize the carrier mobility of the third thin-film transistor 13 through high-precision gate control and improve the resistance to bias stress of the third thin-film transistor 13.

[0150] In some embodiments, such as Figure 10 and Figure 11 As shown, the light-shielding layer 103 includes: a third light-shielding pattern 133; in the orthographic projection facing the substrate 101, the third channel region 128 covers the third light-shielding pattern 133, and the portion of the boundary L33 of the third channel region 128 extending along the sixth direction Y3 has a distance d3 from the portion of the boundary L13 of the third light-shielding pattern 133 extending along the sixth direction Y3.

[0151] In other words, the third light-shielding pattern 133 is smaller in size than the third channel area 128.

[0152] As described above regarding the influence of the size of the light-shielding pattern on the threshold voltage of the thin-film transistor 10, by setting the third channel region 128 to cover the third light-shielding pattern 133 in the orthogonal projection facing the substrate 101, and by having a spacing d3 between the portion of the boundary L33 of the third channel region 128 extending along the sixth direction Y3 and the portion of the boundary L13 of the third light-shielding pattern 133 extending along the sixth direction Y3, the coupling effect between the third light-shielding pattern 133 and the third active layer 12c can be reduced, thereby improving the response speed of the third thin-film transistor 13. For example, this third thin-film transistor 13 is suitable for a multiplexer.

[0153] In some embodiments, such as Figure 10 and Figure 11 As shown, the distance d3 between the portion of the boundary L33 of the third channel region 128 extending along the sixth direction Y3 and the portion of the boundary L13 of the third shading pattern 133 extending along the sixth direction Y3 ranges from 1μm to 3μm.

[0154] For example, the distance d3 between the portion of the boundary L33 of the third channel region 128 extending along the sixth direction Y3 and the portion of the boundary L13 of the third light-shielding pattern 133 extending along the sixth direction Y3 is 1μm, 1.1μm, 1.2μm, 1.3μm, and 1.

[0155] 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2.0μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm,

[0156] 2.5μm, 2.6μm, 2.7μm, 2.8μm, 2.9μm or 3μm, etc., are not limited here.

[0157] By setting the distance d3 between the portion of the boundary L33 of the third channel region 128 extending along the sixth direction Y3 and the portion of the boundary L13 of the third light-shielding pattern 133 extending along the sixth direction Y3 to be in the range of 1μm to 3μm, the coupling effect between the third light-shielding pattern 133 and the third active layer 12c can be reduced while ensuring the light-shielding effect of the third light-shielding pattern 133, thereby improving the response speed of the third thin film transistor 13.

[0158] In some embodiments, such as Figure 7 , Figure 10 and Figure 11 As shown, the threshold voltage of the third thin-film transistor 13 is less than the threshold voltage of the second thin-film transistor 12.

[0159] By adjusting the length of the third channel region 128 and the size of the third light-shielding pattern 133 of the third thin-film transistor 13, the threshold voltage of the third thin-film transistor 13 is made lower than that of the second thin-film transistor 12. This makes the electrical performance of the third thin-film transistor 13 more suitable for multiplexers. This allows the thin-film transistors 10 of the pixel driving circuit, gate driving circuit, and multiplexer in the array substrate 100 to have different electrical characteristics, thereby improving product lifespan.

[0160] In some embodiments, such as Figure 9 As shown, multiple third thin-film transistors 13 are arranged in an array, and multiple third channel regions 128 are connected sequentially along the third direction X3, and multiple third channel regions 128 are arranged at intervals along the sixth direction Y3.

[0161] In other words, multiple third thin-film transistors 13 are combined to form an interconnected transistor. The multiple third channel regions 128 of the transistor form the channel region of the transistor. The channel region has multiple branches extending in the longitudinal and transverse directions. This can reduce the heat dissipation of the third channel region 128 and effectively prevent the third thin-film transistor 13 from burning out due to excessive heat dissipation in the third channel region 128.

[0162] In some embodiments, such as Figure 3 , Figure 6 and Figure 10 As shown, the first active layer 12a, the second active layer 12b, and the third active layer 12c are disposed on the same layer; and / or, the second gate layer 14b and the third gate layer 14c are disposed on the same layer.

[0163] In some embodiments, the material of the gate layer may include a metallic conductive material, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the first conductive layer may also be a metallic stacked structure. Exemplarily, the first conductive layer may include a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum-niobium-titanium (MoNb / Ti) stacked structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum-niobium-copper (MoNb / Cu) stacked structure, a molybdenum-nickel-titanium-copper (MTD / Cu) stacked structure, or a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb) stacked structure. The following are some of the following stacked structures: (Cu / MTD) stacked structure, (MTD / Cu / MTD) stacked structure, (MoTi / Cu) stacked structure, (MoTi / Cu / MTD) stacked structure, (MoTi / Cu / MTD) stacked structure, (MoTi / Cu / MoTi) stacked structure, (MoTi / Cu / MoTi) stacked structure, (MoNb-Copper-MoNb) stacked structure, and (AlNb-MoNd) stacked structure, or combinations thereof.

[0164] The thickness of the second gate 32 can be

[0165] For example, the first active layer 12a, the second active layer 12b and the third active layer 12c are film layers formed using the same film deposition process to form a specific pattern, thereby simplifying the fabrication process of the array substrate 100.

[0166] For example, the second gate layer 14b and the third gate layer 14c are formed using the same film deposition process to form a specific pattern, thereby simplifying the fabrication process of the array substrate 100.

[0167] like Figure 12As shown, some embodiments of this disclosure also provide another display panel 1000, which includes an array substrate 100 as described in any of the above embodiments. The display panel 1000 further includes an opposing substrate 300 and a liquid crystal layer 400. The opposing substrate is opposite to and spaced apart from the array substrate 100, and the liquid crystal layer 400 is disposed between the array substrate 100 and the opposing substrate 300.

[0168] For example, liquid crystal material is disposed in liquid crystal layer 400. The opposing substrate 300 is, for example, a color filter substrate. The array substrate 100 realizes the display operation of display panel 1000 by controlling the degree of rotation of liquid crystal material.

[0169] The display panel 1000 includes the array substrate 100 provided in any of the above embodiments. Therefore, the display panel 1000 provided in this disclosure has all the beneficial effects of the array substrate 100 provided in any of the above embodiments, which will not be elaborated here.

[0170] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized by, include: A substrate and a plurality of thin-film transistors arranged in an array on one side of the substrate; The plurality of thin-film transistors includes: a first thin-film transistor and a second thin-film transistor; The array substrate further includes: a first active layer and a second active layer; the first thin film transistor includes: a first electrode region, a first channel region and a second electrode region located in the first active layer and connected in sequence; the second thin film transistor includes: a third electrode region, a second channel region and a fourth electrode region located in the second active layer and connected in sequence. The first electrode region, the first channel region, and the second electrode region are arranged along a first direction, and the third electrode region, the second channel region, and the fourth electrode region are arranged along a second direction. The first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect or are parallel. Wherein, the size of the first channel region in the first direction is greater than the size of the second channel region in the second direction.

2. The array substrate according to claim 1, characterized in that, The size of the first channel region in the first direction ranges from 5 μm to 8 μm; and / or, The size of the second channel region in the second direction ranges from 5 μm to 7 μm.

3. The array substrate according to claim 1 or 2, wherein, The dimension of the first channel region in the fourth direction is smaller than the dimension of the second channel region in the fifth direction; the fourth direction and the fifth direction are parallel to the substrate, and the fourth direction is perpendicular to the first direction, and the fifth direction is perpendicular to the second direction.

4. The array substrate of claim 1, wherein, Also includes: A light-shielding layer located on the side of the thin-film transistor near the substrate, the light-shielding layer comprising: a first light-shielding pattern and a second light-shielding pattern; In a projection onto the substrate, the first light-shielding pattern covers the first pole region, the first channel region, and the second pole region, the second light-shielding pattern covers the second channel region, and the second light-shielding pattern does not overlap with the third pole region and the fourth pole region.

5. The array substrate of claim 1, wherein, The threshold voltage of the first thin-film transistor is greater than the threshold voltage of the second thin-film transistor.

6. The array substrate of claim 1, wherein, Also includes: A first gate layer and a second gate layer are located on one side of the substrate. The first gate layer includes a first gate pattern of the first thin-film transistor, and the second gate layer includes a second gate pattern of the second thin-film transistor. In a normal projection facing the substrate, the first gate pattern overlaps with the first channel region, and the second gate pattern overlaps with the second channel region. The first gate layer is located on the side of the first channel region closer to the substrate; and / or, the second gate layer is located on the side of the second channel region away from the substrate.

7. The array substrate of claim 6, wherein, Also includes: A first dielectric layer and a gate insulating layer; the first dielectric layer is located between the first active layer and the first gate layer; the gate insulating layer is located between the second active layer and the second gate layer; The thickness of the portion of the first dielectric layer located between the first gate pattern and the first channel region is greater than the thickness of the portion of the gate insulating layer located between the second gate pattern and the second channel region.

8. The array substrate of claim 7, wherein, The difference between the thickness of the portion of the first dielectric layer located between the first gate pattern and the first channel region and the thickness of the portion of the gate insulating layer located between the second gate pattern and the second channel region ranges from 2000 angstroms to 4000 angstroms.

9. The array substrate of claim 1, wherein, A plurality of second thin-film transistor arrays are arranged, and along the second direction, a plurality of second channel regions are sequentially connected, and along the fifth direction, a plurality of second channel regions are sequentially spaced apart.

10. The array substrate of claim 1, wherein, The first active layer and the second active layer are configured on the same layer.

11. The array substrate of claim 6, wherein, The plurality of thin-film transistors further includes: a third thin-film transistor; The array substrate further includes a third active layer, and the third thin film transistor includes a fifth electrode region, a third channel region, and a sixth electrode region located in the third active layer and connected in sequence. The fifth electrode region, the third channel region, and the sixth electrode region are arranged along a third direction, which is parallel to the substrate, and the third direction intersects or is parallel to the second direction. Wherein, the dimension of the third channel region in the third direction is less than or equal to the dimension of the second channel region in the second direction.

12. The array substrate of claim 11, wherein, The third channel region has a size range of 4μm to 7μm in the third direction.

13. The array substrate according to claim 11 or 12, characterized in that, The dimension of the third channel region in the sixth direction is approximately equal to the dimension of the second channel region in the fifth direction; the sixth direction is parallel to the substrate and perpendicular to the third direction.

14. The array substrate of claim 11, wherein, Also includes: A light-shielding layer located on the side of the third thin-film transistor near the substrate, the light-shielding layer comprising: a third light-shielding pattern; In a projection onto the substrate, the third channel region covers the third light-shielding pattern, and the portion of the boundary of the third channel region extending along the sixth direction is spaced from the portion of the boundary of the third light-shielding pattern extending along the sixth direction.

15. The array substrate of claim 14, wherein, In a normal projection facing the substrate, the distance between the portion of the boundary of the third channel region extending along the sixth direction and the portion of the boundary of the third light-shielding pattern extending along the sixth direction ranges from 1 μm to 3 μm.

16. The array substrate of claim 11, wherein, The threshold voltage of the third thin-film transistor is lower than the threshold voltage of the second thin-film transistor.

17. The array substrate of claim 11, wherein, Also includes: A third gate layer located on one side of the substrate, the third gate layer comprising: a third gate pattern; in a normal projection facing the substrate, the third gate pattern overlaps with the third channel region; The third gate layer is located on the side of the third channel region away from the substrate.

18. The array substrate of claim 11, wherein, Multiple third thin-film transistor arrays are arranged, and multiple third channel regions are sequentially connected along the third direction, and multiple third channel regions are sequentially spaced along the sixth direction.

19. The array substrate of claim 17, wherein, The first active layer, the second active layer, and the third active layer are disposed on the same layer; and / or, the second gate layer and the third gate layer are disposed on the same layer.

20. The array substrate of claim 11, wherein, Also includes: Pixel driving circuit, gate driving circuit and multiplexer; The array substrate satisfies at least one of the following: The pixel driving circuit includes the first thin-film transistor; The gate driving circuit includes the second thin-film transistor; The multiplexer includes the third thin-film transistor.

21. A display panel, comprising: include: The array substrate as described in any one of claims 1 to 20; Opposing substrates are arranged opposite to and spaced apart from the array substrates; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

22. A display panel, comprising: include: The array substrate as described in any one of claims 1 to 20; Multiple light-emitting devices are disposed on the array substrate, and the array substrate is used to drive the multiple light-emitting devices to emit light.

23. A display device comprising: include: The display panel as described in claim 21 or 22; A driver chip is used to drive the display panel to display.

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