Signal generating device, quantum computing measurement and control system and quantum computer
By optimizing the frequency multiplier circuit and phase-locked loop circuit, a high-frequency reference clock signal with low phase noise characteristics is generated, which solves the problem of phase noise degradation during the frequency multiplication process, improves signal quality, and reduces the complexity of the phase-locked loop circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2025-06-30
- Publication Date
- 2026-07-03
AI Technical Summary
The existing high-frequency reference clock signal suffers from phase noise degradation during the frequency doubling process, making it difficult to meet the stringent requirements of the quantum measurement and control integrated machine. Furthermore, the low frequency of the phase detector in the traditional PLL circuit leads to near-end phase noise degradation, affecting signal quality.
By combining a frequency multiplier circuit, a phase-locked loop circuit, and a mixer, and through low-pass filtering and dynamic adjustment of the voltage-controlled oscillator, a high-frequency reference clock signal with low phase noise characteristics is generated. This avoids the problem of high frequency dividers in traditional phase-locked loop circuits and optimizes signal quality.
It improves the phase noise performance at both the near and far ends of the signal, enhances signal quality, and ensures that the phase noise level of the target frequency signal output by the voltage-controlled oscillator meets the requirements of quantum computers, while reducing the difficulty of installing and maintaining the phase-locked loop circuit.
Smart Images
Figure CN224457288U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of quantum computer technology, and in particular to a signal generating device, a quantum computing measurement and control system, and a quantum computer. Background Technology
[0002] A quantum computer is a high-performance computing device based on the principles of quantum mechanics. It consists of core components such as quantum chips and a quantum measurement and control integrated machine, used to perform high-speed mathematical and logical operations and process quantum information. In the quantum measurement and control integrated machine, the radio frequency transmission and acquisition functions rely on a high-frequency reference clock signal, typically in the range of 3-8 GHz.
[0003] Currently, such high-frequency reference clock signals are typically obtained by frequency multiplication and phase noise optimization of low-frequency clock signals. However, the frequency multiplication process causes phase noise to deteriorate at a rate of 20logN (where N is the number of frequency multiplications), making it difficult for the phase noise level of the high-frequency clock signal output by the frequency multiplication circuit to meet the stringent requirements of quantum measurement and control integrated machines. Therefore, phase noise optimization processing is necessary for the frequency-multiplied signal.
[0004] Existing phase noise optimization methods are mainly implemented through phase-locked loop (PLL) circuits. A typical PLL circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). Although this PLL circuit can effectively optimize the far-end phase noise of the frequency-multiplied clock signal, the phase detector's detection frequency is relatively low. Therefore, a high-ratio divider is usually required in the feedback link from the VCO output signal to the phase detector. This further deteriorates the near-end phase noise performance of the final signal, affecting the final signal quality and limiting its application in quantum computers.
[0005] Therefore, there is an urgent need to provide a signal generating device that can generate a high-frequency reference clock signal with low phase noise characteristics in order to improve signal quality.
[0006] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0007] The purpose of this invention is to provide a signal generating device, a quantum computing measurement and control system, and a quantum computer that can generate a high-frequency reference clock signal with low phase noise characteristics to improve signal quality and thus meet the requirements of quantum computers for low-phase-noise high-frequency reference clock signals.
[0008] To achieve the above objectives, this utility model provides the following technical solution:
[0009] The first aspect of this utility model provides a signal generating device, comprising:
[0010] A frequency multiplier circuit is used to process the received first clock signal to generate a second clock signal with a higher frequency.
[0011] A phase-locked loop circuit includes a mixer, a first filter, and a voltage-controlled oscillator. The two input terminals of the mixer are electrically connected to the output terminals of the frequency multiplier circuit and the voltage-controlled oscillator, respectively, to generate a difference frequency signal based on the frequency difference between a received second clock signal and a frequency signal. The input terminal of the first filter is electrically connected to the output terminal of the mixer to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal. The input terminal of the voltage-controlled oscillator is electrically connected to the output terminal of the first filter to output the frequency signal and adjust the frequency of the frequency signal according to the first voltage-controlled signal until it is locked to a target frequency.
[0012] The signal generating device described above, further, the frequency multiplier circuit includes a signal processing unit, the signal processing unit including a frequency multiplier element and a first amplifier connected in series;
[0013] The input terminal of the frequency multiplier is used to receive a first clock signal, the output terminal of the frequency multiplier is electrically connected to the input terminal of the first amplifier, and one input terminal of the mixer is electrically connected to the output terminal of the first amplifier.
[0014] In addition to the signal generating device described above, the signal processing unit further includes a second filter, and one input terminal of the mixer is electrically connected to the output terminal of the first amplifier through the second filter.
[0015] In the signal generating device described above, there are multiple signal processing units connected in series; the output terminal of the second filter of the preceding signal processing unit is electrically connected to the input terminal of the frequency multiplier element of the following signal processing unit.
[0016] The frequency multiplier elements operate in different frequency bands; the second filters operate in different frequency bands; and the output frequency bandwidth of the voltage-controlled oscillator is less than the passband width of the second filter in the last stage signal processing unit.
[0017] As described above, the signal generating device further includes a phase-locked loop circuit that also includes a power divider unit. The input terminal of the power divider unit is electrically connected to the output terminal of the voltage-controlled oscillator, and one of the multiple output terminals of the power divider unit is electrically connected to one input terminal of the mixer, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.
[0018] As described above, the signal generating device further includes a second amplifier and a power divider in the power dividing unit;
[0019] The input terminal of the second amplifier is electrically connected to the output terminal of the voltage-controlled oscillator to amplify the frequency signal;
[0020] The input terminal of the power divider is electrically connected to the output terminal of the second amplifier, and one of the multiple output terminals of the power divider is electrically connected to one input terminal of the mixer, so as to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
[0021] As described above, the signal generating device further includes a phase-locked loop circuit that also includes an attenuator electrically connected between the power divider and the mixer, used to reduce the power of the divided frequency signal to a preset range.
[0022] The signal generating device described above further includes a PCB board, wherein the frequency multiplier circuit and the phase-locked loop circuit are respectively integrated on opposite sides of the PCB board.
[0023] The second aspect of this utility model provides a quantum computing measurement and control system, including a quantum measurement and control link and the aforementioned signal generating device. The quantum measurement and control link is electrically connected to the phase-locked loop circuit to use a frequency signal of the target frequency as a reference clock signal.
[0024] The third aspect of this utility model provides a quantum computer, including the above-mentioned quantum computing measurement and control system.
[0025] The beneficial effects of this utility model are as follows:
[0026] The signal generating device of this application optimizes the traditional phase-locked loop circuit to avoid deteriorating the near-end phase noise index of the final signal, thereby generating a signal with low phase noise characteristics and improving signal quality. Specifically, the first filter in the phase-locked loop circuit of this application combines its low-pass filtering function with the dynamic frequency adjustment function of the voltage-controlled oscillator to improve the far-end and near-end phase noise of the frequency-multiplied clock signal. In addition, this circuit uses a mixer, which effectively avoids the problem of needing to set a high frequency divider due to the low frequency of the phase detector in the traditional phase-locked loop circuit, thereby significantly reducing the near-end phase noise introduced in the feedback link and effectively improving the near-end phase noise performance.
[0027] In summary, the signal generation device of this application improves the near-end and far-end phase noise performance of the final output signal, enabling the phase noise level of the target frequency signal stably output by the voltage-controlled oscillator to meet the requirements of the quantum computing measurement and control system for a high-frequency reference clock signal, and thus it can be used as a high-frequency reference clock signal.
[0028] The quantum computing measurement and control system and quantum computer provided by this utility model include the above-mentioned signal generating device, and therefore have the same beneficial effects, which will not be described again here. Attached Figure Description
[0029] Figure 1 This is a structural block diagram of the signal generating device provided in an embodiment of the present utility model;
[0030] Figure 2 A schematic diagram of the frequency multiplier circuit provided in the embodiment of this utility model. Figure 1 ;
[0031] Figure 3 A schematic diagram of the frequency multiplier circuit provided in the embodiment of this utility model. Figure 2 ;
[0032] Figure 4 A schematic diagram of a phase-locked loop circuit provided in an embodiment of this utility model;
[0033] Figure 5 A schematic diagram of the power distribution unit provided in an embodiment of this utility model;
[0034] In the attached figures, the following are the reference numerals: 10, mixer; 20, first filter; 30, voltage-controlled oscillator; 40, power divider; 41, second amplifier; 42, power divider; 50, attenuator; 60, expansion circuit; 70, frequency multiplier; 80, first amplifier; 90, second filter. Detailed Implementation
[0035] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0036] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0038] Figure 1 This is a structural block diagram of the signal generating device provided in an embodiment of the present invention; as shown below. Figure 1 As shown: This application discloses a signal generating device, including:
[0039] The frequency multiplier circuit is used to process the received first clock signal to generate a second clock signal with a higher frequency.
[0040] A phase-locked loop circuit includes a mixer 10, a first filter 20, and a voltage-controlled oscillator 30. The two input terminals of the mixer 10 are electrically connected to the output terminal of the frequency multiplier circuit and the output terminal of the voltage-controlled oscillator 30, respectively, to generate a difference frequency signal based on the frequency difference between the received second clock signal and the frequency signal. The input terminal of the first filter 20 is electrically connected to the output terminal of the mixer 10 to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal. The input terminal of the voltage-controlled oscillator 30 is electrically connected to the output terminal of the first filter 20 to output a frequency signal and adjust the frequency of the frequency signal according to the first voltage-controlled signal until it is locked to the target frequency.
[0041] The signal generating device in this embodiment operates as follows: A frequency multiplier circuit processes the received first clock signal (e.g., a 100MHz clock signal) to generate a second clock signal with a higher frequency (e.g., a 6.4GHz clock signal); the mixer 10 in the phase-locked loop circuit precisely compares the frequency signal output by the voltage-controlled oscillator 30 with the frequency-multiplied second clock signal to generate a difference frequency signal representing the frequency difference between the two. A first filter 20 performs low-pass filtering on the difference frequency signal to generate a first voltage-controlled signal. The voltage-controlled oscillator 30 adjusts the frequency of its output frequency signal according to the first voltage-controlled signal until the frequency of the frequency signal is locked to the target frequency.
[0042] The signal generating device in this embodiment optimizes the traditional phase-locked loop circuit to avoid deteriorating the near-end phase noise index of the final signal, thereby generating a signal with low phase noise characteristics and improving signal quality. Specifically, the first filter 20 in the phase-locked loop circuit of this application combines its low-pass filtering function with the dynamic frequency adjustment function of the voltage-controlled oscillator 30 to work together to improve the far-end and near-end phase noise of the frequency-multiplied clock signal. In addition, the circuit uses a mixer 10, which effectively avoids the problem of needing to set a high frequency divider due to the low frequency of the phase detector in the traditional phase-locked loop circuit, thereby significantly reducing the near-end phase noise introduced in the feedback link and effectively improving the near-end phase noise performance.
[0043] In summary, the signal generation device of this embodiment improves the near-end and far-end phase noise performance of the final output signal, ensuring that the phase noise level of the target frequency signal stably output by the voltage-controlled oscillator 30 meets the requirements of the quantum computing measurement and control system for a high-frequency reference clock signal, and can be used as a high-frequency reference clock signal. Simultaneously, the phase-locked loop circuit of this embodiment uses fewer components and has a more streamlined circuit structure, significantly reducing the difficulty of installation, maintenance, and debugging, effectively improving the reliability and maintainability of the phase-locked loop circuit.
[0044] In this embodiment, the target frequency is the frequency of the second clock signal after processing by the frequency multiplier circuit.
[0045] In this embodiment, the first filter 20 is a loop filter, which can be active or passive. In some embodiments of this embodiment, the first filter 20 is active. Compared to a passive filter, the active first filter 20 can provide higher gain and wider loop bandwidth, thereby achieving faster lock-in time and better dynamic response. Furthermore, the active first filter 20 helps reduce phase noise and improve frequency stability. To further reduce phase noise, the phase-locked loop circuit also includes an LDO (low dropout linear regulator) to power the first filter 20. Using an LDO regulator to power the first filter 20 provides a stable, low-noise power supply, thereby helping to reduce the phase noise of the phase-locked loop circuit.
[0046] In this embodiment, the type of voltage-controlled oscillator 30 is not specifically limited. In order to further reduce phase noise, in some implementations of this embodiment, the voltage-controlled oscillator 30 adopts a sapphire dielectric oscillator.
[0047] In this embodiment, the frequency multiplier circuit is not specifically limited, and the following are some examples:
[0048] Example 1: A frequency multiplier circuit can be composed of one or more frequency multipliers connected in series, or it can be composed of one or more comb spectrum generators connected in series, or it can be composed of a frequency multiplier and a comb spectrum generator connected in series.
[0049] Example 2: Figure 2 A schematic diagram of the frequency multiplier circuit provided in the embodiment of this utility model. Figure 1 ;like Figure 2 As shown: The frequency multiplier circuit includes a signal processing unit, which includes a frequency multiplier element 70 and a first amplifier 80 connected in series; the input terminal of the frequency multiplier element 70 is used to receive a first clock signal, the output terminal of the frequency multiplier element 70 is electrically connected to the input terminal of the first amplifier 80, and one input terminal of the mixer 10 is electrically connected to the output terminal of the first amplifier 80.
[0050] In the frequency multiplier circuit of this example, the frequency multiplier element 70 is used to increase the frequency of the first clock signal to achieve frequency multiplication; then the first amplifier 80 amplifies the signal output by the frequency multiplier element 70 to enhance the signal power, so as to compensate for the attenuation that may occur during the frequency multiplication process and ensure the integrity of the signal.
[0051] In this example, the specific type of frequency multiplier 70 is not limited. Depending on the actual needs, a comb spectrum generator or a frequency multiplier can be selected. Among them, the comb spectrum generator has low cost and the number of frequency multiplications is flexible and adjustable, but circuit debugging is required according to the needs; the frequency multiplier has a simple circuit, does not require debugging, and the number of frequency multiplications is fixed and cannot be changed.
[0052] In this example, the second filter 90 can be a bandpass filter.
[0053] Example 3: Figure 3 A schematic diagram of the frequency multiplier circuit provided in the embodiment of this utility model. Figure 2 ;like Figure 3 As shown: Based on Example 2, the signal processing unit further includes a second filter 90, and one input terminal of the mixer 10 is electrically connected to the output terminal of the first amplifier 80 through the second filter 90.
[0054] In this example, the second filter 90 is designed to filter the signal amplified by the first amplifier 80 in order to suppress high-frequency spurious signals and reduce phase noise, thereby improving the purity and phase stability of the signal.
[0055] In this example, the number of signal processing units in the frequency multiplier circuit is not specifically limited; it can be one, two, or more, depending on actual needs. In some specific implementations, there are multiple signal processing units connected in series. The output terminal of the second filter 90 of the previous stage signal processing unit is electrically connected to the input terminal of the frequency multiplier element 70 of the next stage signal processing unit. The operating frequency bands of each frequency multiplier element 70 are different, and the operating frequency bands of each second filter 90 are different.
[0056] By setting up multiple signal processing units, the signal can be frequency multiplied, amplified, and filtered in stages. Specifically, each frequency multiplier 70 operates in a different frequency band, meaning that the design of each frequency multiplier 70 can focus on a specific frequency range to improve performance and accuracy. For example, when there are two frequency multipliers 70, the first frequency multiplier 70 can extract the multiplication factor of the fundamental frequency from the input signal, and then the second frequency multiplier 70 performs further frequency multiplication to achieve a higher multiplication factor. This hierarchical processing can reduce error accumulation and improve the overall frequency multiplication accuracy and performance. Similarly, the different operating frequency bands of the second filters 90 can achieve more precise frequency selectivity, filtering out noise or interference within a specific frequency band while preserving signal quality within the target frequency range.
[0057] Furthermore, in some specific embodiments, the output frequency bandwidth of the voltage-controlled oscillator 30 is smaller than the passband width of the second filter 90 in the last stage signal processing unit. This setting allows for precise control of the frequency output of the voltage-controlled oscillator 30, enabling it to lock with the center frequency of the second filter 90. In addition, it can significantly reduce the performance requirements of the second filter 90, thereby reducing costs.
[0058] Figure 4 This is a schematic diagram of a phase-locked loop circuit provided in an embodiment of the present invention; in some embodiments of this invention, such as Figure 4 As shown: In Figure 1 Based on the phase-locked loop circuit, the phase-locked loop circuit also includes a power divider unit 40. The input terminal of the power divider unit 40 is electrically connected to the output terminal of the voltage-controlled oscillator 30, and one of the multiple output terminals of the power divider unit 40 is electrically connected to one input terminal of the mixer 10, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.
[0059] In this embodiment, the frequency signal output from the voltage-controlled oscillator 30 is divided into multiple paths by the power divider unit 40, allowing the signal to be used at multiple output terminals. This not only allows the same frequency signal to be used for different circuit requirements but also helps reduce interference between different circuit parts, improving the overall stability and signal quality of the circuit. In this embodiment, the design of the power divider unit 40 allows it to have at least two output terminals, but the number is not specifically limited and can be two, three, or more. The power-divided frequency signals are allocated to different uses: one signal is used as a feedback signal and output to the mixer 10 to maintain the stable operation of the phase-locked loop circuit; the remaining signals can be output to the quantum measurement and control link (e.g., the RF transmission and acquisition link) as a high-frequency reference clock signal for that link, or output to other circuits that require such signals.
[0060] Figure 5A schematic diagram of the power dividing unit provided in an embodiment of this utility model; as shown Figure 5 As shown: In some embodiments of this example, the power divider unit 40 includes a second amplifier 41 and a power divider 42; the input terminal of the second amplifier 41 is electrically connected to the output terminal of the voltage-controlled oscillator 30 to amplify the frequency signal; the input terminal of the power divider 42 is electrically connected to the output terminal of the second amplifier 41, and one of the multiple output terminals of the power divider 42 is electrically connected to one input terminal of the mixer 10 to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
[0061] In this embodiment, the power divider unit 40 amplifies the frequency signal output from the voltage-controlled oscillator 30 via the second amplifier 41, enhancing the signal power to compensate for possible attenuation during transmission and subsequent power division, and ensuring signal integrity. The power divider 42 evenly distributes the amplified signal to multiple output terminals. This not only allows the same frequency signal to be used for different circuit requirements, such as as a feedback signal for the mixer 10 and a high-frequency reference clock signal for the quantum measurement and control link, but also helps reduce interference between different circuit sections, improving the overall stability and signal quality of the circuit.
[0062] In some embodiments of this example, the phase-locked loop circuit further includes an attenuator 50, which is electrically connected between the power divider 42 and the mixer 10, and is used to reduce the power of the frequency signal after power division to a preset range.
[0063] In this embodiment, the preset range is the linear input power range of the mixer 10, ensuring that the mixer 10 operates within its optimal dynamic range to prevent performance degradation or damage due to excessively strong signals. Furthermore, the attenuator 50 in this embodiment can be an adjustable attenuator 50 constructed from a π-type resistor network, including series resistors (R1, R2) and parallel resistors (R3). The attenuation range can be adjusted by changing the combination of R1 / R2 / R3 resistance values.
[0064] In this embodiment, the initial voltage control signal of the voltage-controlled oscillator 30 can be provided by the voltage-controlled oscillator 30 itself or by an external circuit. To accelerate the locking process of the phase-locked loop (PLL) circuit and improve its stability and dynamic performance, in some implementations of this embodiment, the PLL circuit further includes a spreader circuit 60 for providing a second voltage control signal. This second voltage control signal serves as the initial voltage control signal, enabling the voltage-controlled oscillator 30 to output a frequency signal. The spreader circuit 60 provides the initial voltage control signal when the PLL circuit starts up, thus prompting the frequency signal output by the voltage-controlled oscillator 30 to quickly approach the target frequency.
[0065] In this embodiment, the specific type of the capture circuit 60 is not limited. For example, it can be a Wien bridge oscillator circuit, a triangular wave generation circuit, or other circuits. In some implementations of this embodiment, the capture circuit 60 is a triangular wave generation circuit. Compared with other capture circuits 60, the triangular wave generation circuit has the advantages of fast frequency sweep, high controllability, low noise level, and simple circuit.
[0066] The signal generating device of this embodiment includes a frequency multiplier circuit and a phase-locked loop (PLL) circuit. To avoid mutual interference between these two circuits, in some embodiments of this embodiment, the signal generating device further includes a PCB board. The frequency multiplier circuit and the PLL circuit are integrated on opposite sides of the PCB board, respectively. This layout not only reduces mutual interference between the frequency multiplier circuit and the PLL circuit, improving the final signal quality, but also increases the circuit integration. In addition to integrating the frequency multiplier circuit and the PLL circuit on opposite sides of the PCB board, a partition can also be provided on the PCB board to separate the frequency multiplier circuit and the PLL circuit into different areas to reduce signal interference and improve the final signal quality.
[0067] In order to further reduce mutual interference between signals and improve the final signal quality, in some embodiments of this example, when the frequency multiplier circuit includes multiple signal processing units, the signal processing units can be separated into different areas by setting a partition on the PCB board to reduce signal interference.
[0068] Based on the same concept, this application also proposes a quantum computing measurement and control system, including a quantum measurement and control link and a signal generating device as described in the above embodiment. The quantum measurement and control link is electrically connected to a phase-locked loop circuit to use a frequency signal of the target frequency as a reference clock signal.
[0069] The quantum computing measurement and control system of this application includes the signal generating device of the above embodiments, and therefore has the same beneficial effects as the above signal generating device, which will not be described again here.
[0070] Based on the same concept, this application also proposes a quantum computer, including the above-mentioned quantum computing measurement and control system.
[0071] The quantum computer of this application includes the aforementioned quantum computing measurement and control system. Since the aforementioned quantum computing measurement and control system includes the aforementioned signal generating device, the quantum computer of this application has the same beneficial effects as the aforementioned signal generating device, which will not be described in detail here.
[0072] In this specification, references to terms such as "some embodiments" or "examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0073] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.
Claims
1. A signal generating device, characterized by include: A frequency multiplier circuit is used to process the received first clock signal to generate a second clock signal with a higher frequency. A phase-locked loop circuit includes a mixer, a first filter, and a voltage-controlled oscillator. The two input terminals of the mixer are electrically connected to the output terminals of the frequency multiplier circuit and the voltage-controlled oscillator, respectively, to generate a difference frequency signal based on the frequency difference between a received second clock signal and a frequency signal. The input terminal of the first filter is electrically connected to the output terminal of the mixer to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal. The input terminal of the voltage-controlled oscillator is electrically connected to the output terminal of the first filter to output the frequency signal and adjust the frequency of the frequency signal according to the first voltage-controlled signal until it is locked to a target frequency.
2. The signal generating device of claim 1, wherein The frequency multiplier circuit includes a signal processing unit, which includes a frequency multiplier element and a first amplifier connected in series. The input terminal of the frequency multiplier is used to receive a first clock signal, the output terminal of the frequency multiplier is electrically connected to the input terminal of the first amplifier, and one input terminal of the mixer is electrically connected to the output terminal of the first amplifier.
3. The signal generating device of claim 2, wherein, The signal processing unit further includes a second filter, and one input terminal of the mixer is electrically connected to the output terminal of the first amplifier through the second filter.
4. The signal generating device of claim 3, wherein The signal processing units are multiple and connected in series; the output terminal of the second filter of the previous stage signal processing unit is electrically connected to the input terminal of the frequency multiplier element of the next stage signal processing unit. The frequency multiplier elements operate in different frequency bands; the second filters operate in different frequency bands; and the output frequency bandwidth of the voltage-controlled oscillator is less than the passband width of the second filter in the last stage signal processing unit.
5. The signal generating device of claim 1, wherein The phase-locked loop circuit also includes a power divider unit. The input terminal of the power divider unit is electrically connected to the output terminal of the voltage-controlled oscillator, and one of the multiple output terminals of the power divider unit is electrically connected to one input terminal of the mixer, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.
6. The signal generating device of claim 5, wherein The power division unit includes a second amplifier and a power divider; The input terminal of the second amplifier is electrically connected to the output terminal of the voltage-controlled oscillator to amplify the frequency signal; The input terminal of the power divider is electrically connected to the output terminal of the second amplifier, and one of the multiple output terminals of the power divider is electrically connected to one input terminal of the mixer, so as to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
7. The signal generating device of claim 6, wherein The phase-locked loop circuit also includes an attenuator, which is electrically connected between the power divider and the mixer to reduce the power of the frequency signal after power division to a preset range.
8. The signal generating device of claim 1, wherein, It also includes a PCB board, on which the frequency multiplier circuit and the phase-locked loop circuit are respectively integrated on opposite sides of the PCB board.
9. A quantum computing control system, comprising: It includes a quantum measurement and control link and a signal generating device as described in any one of claims 1-8, wherein the quantum measurement and control link is electrically connected to the phase-locked loop circuit to use the frequency signal of the target frequency as a reference clock signal.
10. A quantum computer, comprising: The quantum computing system of claim 9.