An under voltage latch circuit with recovery time
By designing an undervoltage latch circuit with recovery time, and utilizing a power supply voltage detection module, a recovery time generation module, and logic circuits, the problem of false reversal of the undervoltage latch circuit during power fluctuations was solved, achieving high-precision recovery time and low-cost circuit protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- LIGHTWEIXIN SEMICONDUCTOR (WUXI) CO LTD
- Filing Date
- 2025-07-10
- Publication Date
- 2026-07-03
Smart Images
Figure CN224459228U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to an undervoltage latch circuit with recovery time, which is applied in the field of integrated circuits. Background Technology
[0002] As electronic devices become increasingly complex, power management has become crucial. Significant power fluctuations can negatively impact circuitry, necessitating the design of an undervoltage latch circuit with protective features. This is an electronic protection mechanism that monitors the power supply voltage and shuts down or locks the circuit when it falls below a set threshold voltage, preventing instability and damage caused by excessively low voltage. The power supply voltage detection module monitors the power supply voltage and determines the output signal; fluctuations in the power supply may cause corresponding oscillations in the output signal. Utility Model Content
[0003] The purpose of this invention is to overcome the defects in the existing technology and provide an undervoltage latch circuit with recovery time, which has the advantages of high-precision recovery time, good scalability, prevention of undervoltage reverse reversal, low cost, and simple circuit.
[0004] To achieve the above objectives, the technical solution of this utility model is to design an undervoltage latch circuit with recovery time, including a power supply voltage detection module and a recovery time generation module; the power supply voltage detection module consists of a sampling circuit and a first comparator circuit, and the recovery time generation module consists of a charge pump circuit and a second comparator circuit; the undervoltage latch circuit with recovery time also includes a bandgap reference circuit and logic circuits.
[0005] A further technical solution is that the power supply voltage detection module consists of three detection resistors, one switching NMOS transistor, four PMOS transistors, and three NMOS transistors;
[0006] The sampling circuit consists of resistors R1, R2, and R3, and a switching NMOS1 transistor;
[0007] The first comparator is composed of PMOS transistors M1, M2, M5, and M6 and NMOS1 transistors M3, M4, and M7; resistors R1, R2, and R3 are connected in series; the drain of the switching NMOS1 transistor is connected to the first end of resistor R3, and this node is also connected to the second end of resistor R2; the source of the switching NMOS1 transistor is connected to the second end of resistor R3 and connected to the power supply GND.
[0008] A further technical solution is that the source terminals of transistors M1 and M2 are both connected to the drain terminal of M5. The drain terminal of M1 is connected to the drain and gate terminals of M3 and M4. The drain terminals of M2 and M4 are connected to form the first stage output of the first comparator, which is input to the gate terminal of M7. The drain terminals of M6 and M7 are connected to form the second stage output of the first comparator. The source terminals of M5 and M6 are connected to the power supply VDD, and their gate terminals are connected to the first bias voltage. The source terminals of M3, M4, and M7 are connected to the power supply GND. The gate terminal of M1 is the negative input terminal of the first comparator, and the gate terminal of M2 is the positive input terminal of the first comparator.
[0009] A further technical solution is that transistors M1, M2, M3, M4, and M5 together form the first stage of the first comparator, and the second stage of the first comparator is composed of transistors M6 and M7; wherein transistors M5 and M6 are current source transistors.
[0010] A further technical solution is that the recovery time generation module consists of a capacitor C, a switching NMOS2 transistor, four PMOS transistors, and three NMOS transistors; the charge pump circuit consists of a capacitor C and a switching NMOS2 transistor; and the second comparator consists of PMOS transistors M8, M10, M11, and M12 and NMOS transistors M9, M13, and M14.
[0011] A further technical solution is as follows: the drain of the NMOS2 transistor is connected to the first terminal of capacitor C, and this node is also connected to the positive input terminal of the second comparator; the source of the NMOS2 transistor is connected to the second terminal of capacitor C and connected to the power supply GND; the sources of transistors M11 and M12 are connected to the drain of M10; the drain of M11 is connected to the drain of M13, and the gate of M13 is connected to the gate of M14; the drain of M12 and the drain of M14 are connected to form the first stage output of the second comparator, which is input to the gate of M9; the drain of M8 is connected to the drain of M9 to form the second stage output of the second comparator.
[0012] A further technical solution is as follows: the source terminals of M8 and M10 are connected to the power supply VDD, and the gate terminals are connected to the first bias voltage; the source terminals of M9, M13, and M14 are connected to the power supply GND; the gate terminal of M11 is the negative input terminal of the comparator, and the gate terminal of M12 is the positive input terminal of the comparator; transistors M10, M11, M12, M13, and M14 together form the first stage of the comparator, and the second stage of the comparator is composed of transistors M8 and M9; among them, transistors M8 and M10 are current source transistors.
[0013] A further technical solution is that the logic circuit consists of a first inverter, a second inverter, a third inverter, and a first AND gate.
[0014] A further technical solution is that the undervoltage latch circuit with recovery time also includes a charging current control circuit; the charging current control circuit is composed of transistors MC1 and MC2 and a current-limiting resistor RZ, with MC1 and MC2 forming a current mirror.
[0015] The advantages and beneficial effects of this invention are as follows: the recovery time generation module can shield the power supply fluctuations during the recovery time, thus providing more effective circuit protection. Furthermore, the designed logic circuit, responsible for processing the output signals of the power supply voltage detection module and the recovery time generation module, can effectively prevent the undervoltage latch circuit from generating false reversal signals during power-on, thereby solving the problem of low-voltage false reversal.
[0016] High-precision recovery time. Because a bandgap reference circuit is incorporated into the circuit, the generated voltage does not change with temperature and voltage. Therefore, the first charging current has high precision, enabling accurate recovery time.
[0017] To prevent false reversals due to low voltage, the output voltages of the first and second comparators are calculated using logic circuitry to avoid false reversals caused by undervoltage latch-up during power-on. Furthermore, as mentioned earlier... Figure 3 As shown in the diagram, the recovery time generation module can effectively avoid power fluctuations and provide more effective circuit protection.
[0018] It offers good scalability. As described in Example 2, the recovery time can be adjusted by adding a charging current control circuit.
[0019] Low cost. Easy to design and replicate, small footprint, and inexpensive. Attached Figure Description
[0020] Figure 1 This is a structural block diagram of an undervoltage latch circuit with recovery time according to an embodiment of this utility model;
[0021] Figure 2 This is a circuit diagram of an undervoltage latch with recovery time according to an embodiment of this utility model;
[0022] Figure 3 The voltage waveform diagram is shown when the undervoltage latch circuit with recovery time of this utility model is working.
[0023] Figure 4 This is a block diagram of the undervoltage latch circuit with adjustable recovery time, as shown in Example 2 of this utility model.
[0024] Figure 5 This is a circuit diagram of an undervoltage latch with adjustable recovery time, as shown in Example 2 of this utility model. Detailed Implementation
[0025] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solution of this utility model and should not be construed as limiting the scope of protection of this utility model.
[0026] Example 1: This utility model is an undervoltage latch circuit with recovery time, such as... Figure 1 As shown, this utility model provides an undervoltage latch circuit with recovery time. The overall circuit includes a power supply voltage detection module and a recovery time generation module. The power supply voltage detection module consists of a sampling circuit and a first comparator circuit, while the recovery time generation module consists of a charge pump circuit and a second comparator circuit. In addition, the circuit also includes a bandgap reference circuit and logic circuits.
[0027] The sampling circuit monitors voltage fluctuations on the power supply in real time. Its output signal, the sampled voltage, is input to the positive input of the first comparator. The negative input of the first comparator receives a first reference voltage generated by the bandgap reference circuit. When the sampled voltage is lower than the first reference voltage, the first comparator output voltage is low. At this time, the first comparator output voltage passes through the logic circuit, and the output switch enable signal triggers the charge pump circuit to reset to zero. When the sampled voltage is higher than the first reference voltage, the first comparator output voltage is high. At this time, the first comparator output voltage passes through the logic circuit, and the output switch enable signal triggers the charge pump circuit to charge. The charge pump charging current comes from the first charging current generated by the bandgap reference circuit. The charge pump circuit outputs a charge pump voltage, which is input to the positive input of the second comparator. The negative input of the second comparator receives a second reference voltage generated by the bandgap reference circuit. When the charge pump voltage is lower than the second reference voltage, the second comparator output voltage is low; when the charge pump voltage exceeds the second reference voltage, the second comparator output voltage is high, indicating that the charge pump circuit has completed its recovery time generation process. The recovery time is defined as the time from when the output voltage of the first comparator circuit changes from low to high to when the output voltage of the second comparator circuit changes from low to high. The bandgap reference circuit provides the first reference voltage, second reference voltage, and first charging current to the first comparator circuit, the second comparator circuit, and the charge pump circuit, ensuring their normal operation. Finally, the logic circuit monitors the output signals of the power supply voltage detection module and the recovery time generation module, and outputs the undervoltage latch signal of the undervoltage latch circuit with recovery time. Furthermore, the logic circuit simultaneously controls the voltage division ratio of the sampling circuit and the activation and deactivation of the charge pump. This will be analyzed in detail below.
[0028] This utility model proposes an undervoltage latch circuit with recovery time, as follows: Figure 2As shown, the power supply voltage detection module consists of three detection resistors, one switching NMOS transistor, four PMOS transistors, and three NMOS transistors. Specifically: the sampling circuit comprises resistors R1, R2, and R3, and the switching NMOS transistor; the first comparator consists of PMOS transistors M1, M2, M5, and M6, and NMOS transistors M3, M4, and M7. Resistors R1, R2, and R3 are connected in series. The drain of the switching NMOS transistor is connected to the first terminal of resistor R3, which is also connected to the second terminal of resistor R2. The source of the switching NMOS transistor is connected to the second terminal of resistor R3 and then to the power supply GND. The sources of transistors M1 and M2 are connected to the drain of M5. The drain of M1 is connected to the drain and gate of M3, and the gate of M4. The drain of M2 is connected to the drain of M4, forming the first stage output of the first comparator, which is input to the gate of M7. The drain of M6 is connected to the drain of M7, forming the second stage output of the first comparator. The source terminals of transistors M5 and M6 are connected to the power supply VDD, and their gate terminals are connected to the first bias voltage. The source terminals of transistors M3, M4, and M7 are connected to the power supply GND. The gate terminal of M1 is the negative input terminal of the first comparator, and the gate terminal of M2 is the positive input terminal of the first comparator. Transistors M1, M2, M3, M4, and M5 together form the first stage of the first comparator, and the second stage of the first comparator is composed of transistors M6 and M7. Transistors M5 and M6 are current source transistors, providing the correct operating current to the first comparator and ensuring its normal operation.
[0029] The basic working principle of the power supply voltage detection module is as follows: the power supply voltage VDD is divided by resistors R1, R2, and R3, and the sampled voltage on resistor R2 is input to the positive input terminal of the first comparator, the bandgap reference circuit ( Figure 2 The first reference voltage (not shown) is input to the negative input of the first comparator. After comparison by the first comparator, the first comparator outputs its output voltage. When the output signal of the first comparator is high, it indicates that the power supply voltage VDD is normal and the sampled voltage is higher than the first reference voltage; when the output signal of the first comparator is low, it indicates that the power supply voltage VDD is too low and the sampled voltage is lower than the first reference voltage.
[0030] Furthermore, the output voltage of the first comparator drives the NMOS1 transistor to turn on and off via the first inverter in the logic circuit. Its function is to bypass or connect resistor R3 in the sampling circuit, thereby changing the voltage division ratio of the sampling circuit. Keeping the first reference voltage constant, the two states of resistor R3 in the sampling circuit—on and off—correspond to the low threshold voltage VRL and high threshold voltage VRH at the power supply voltage VDD. When the power supply voltage VDD is too low, resistor R3 is bypassed; when the power supply voltage VDD is greater than the high threshold voltage VRH, the power supply is considered normal. When the power supply voltage VDD is normal, resistor R3 is on; when the power supply voltage VDD is less than the low threshold voltage VRL, the power supply voltage VDD is considered too low (abnormal).
[0031] When the power supply voltage VDD is applied:
[0032] ① When the power supply voltage VDD is less than the high threshold voltage VRH, that is, when the sampling voltage is less than the first reference voltage, the gate-source voltage of transistor M2 is less than the gate-source voltage of M1, and the output of the first comparator is low. The switch enable signal is high, turning on the bypass resistor R3 of NMOS1 transistor. This state continues until VDD is greater than the high threshold voltage VRH.
[0033] ② When the power supply voltage VDD is greater than the high threshold voltage VRH, that is, when the sampling voltage is greater than the first reference voltage, the gate-source voltage of transistor M2 is greater than the gate-source voltage of M1, the output of the first comparator is high, the switch enable signal is low, driving transistor NMOS1 to turn off, and resistor R3 is connected to the sampling circuit.
[0034] When the power supply voltage VDD drops:
[0035] ① When the power supply voltage VDD starts to drop but is still greater than the low threshold voltage VRL (i.e., the sampling voltage is greater than the first reference voltage), the gate-source voltage of transistor M2 is greater than the gate-source voltage of M1. The output of the first comparator is high, the switch enable signal is low, the NMOS1 transistor is turned off, and resistor R3 is connected to the sampling circuit. This state continues until VDD is less than the low threshold voltage VRL.
[0036] ② When the power supply voltage VDD is less than the low threshold voltage VRL, that is, when the sampling voltage is less than the first reference voltage, the gate-source voltage of transistor M2 is less than the gate-source voltage of M1, and the output of the first comparator is low. The switch enable signal is high, turning on the bypass resistor R3 of NMOS1 transistor.
[0037] Once the specific voltage values of VRH and VRL are determined, the resistance values of R1, R2, and R3 can be calculated based on the specific voltage division ratio of the resistors.
[0038] The recovery time generation module consists of a capacitor C, a switching NMOS2 transistor, four PMOS transistors, and three NMOS transistors. Specifically: the charge pump circuit comprises capacitor C and the switching NMOS2 transistor; the second comparator consists of PMOS transistors M8, M10, M11, and M12, and NMOS transistors M9, M13, and M14. The drain of the switching NMOS2 transistor is connected to the first terminal of capacitor C, which is also connected to the positive input of the second comparator and receives the first charging current generated by the bandgap reference circuit. The source of the NMOS2 transistor is connected to the second terminal of capacitor C and to the power supply GND. The sources of transistors M11 and M12 are connected to the drain of M10. The drain and gate of M11 are connected to the drain and gate of M13, respectively. The drain of M12 and the drain of M14 are connected to form the first stage output of the second comparator, which is input to the gate of M9. The drain of M8 is connected to the drain of M9 to form the second stage output of the second comparator. The source terminals of transistors M8 and M10 are connected to the power supply VDD, and their gate terminals are connected to the first bias voltage. The source terminals of transistors M9, M13, and M14 are connected to the power supply GND. The gate terminal of M11 is the negative input terminal of the comparator, and the gate terminal of M12 is the positive input terminal. Transistors M10, M11, M12, M13, and M14 together form the first stage of the comparator. The second stage of the comparator is composed of transistors M8 and M9. Transistors M8 and M10 are current source transistors, providing the correct operating current to the second comparator and ensuring its normal operation.
[0039] The basic working principle of the recovery time generation module is as follows: The second comparator monitors the voltage across capacitor C in the charge pump and compares it with the second reference voltage. When the charge pump starts charging, its output voltage, i.e., the charge pump voltage, slowly increases. When it exceeds the second reference voltage, the second comparator output voltage is high, and the recovery time generation module completes its operation. The charge pump voltage across capacitor C is connected to the positive input terminal of the second comparator, and the second reference voltage generated by the bandgap reference circuit is input to the negative input terminal of the second comparator.
[0040] When the power supply voltage VDD is too low, the first inverter drives the NMOS2 transistor to conduct, and the charge pump voltage is set to 0. At this time, after comparison by the second comparator, the output voltage of the second comparator is low. When the power supply voltage VDD is normal, the first inverter drives the NMOS2 transistor to turn off, and charge begins to accumulate on capacitor C. The charge pump voltage gradually increases. After comparison by the second comparator, when the charge pump voltage is higher than the second reference voltage, the output voltage of the second comparator is high. The comparator module in the circuit uses a two-stage structure to improve accuracy. Because the comparator is used in an open-loop application, no compensation circuit is needed.
[0041] The logic circuit consists of a first inverter, a second inverter, a third inverter, and a first AND gate. It processes the output voltages of the first and second comparators. When the sampling circuit detects a high level output from the first comparator, it waits for the charge pump to charge. During this time, the charge pump voltage rises slowly but remains below the second reference voltage, and the undervoltage latch signal output by the logic circuit is low. When the charge pump voltage exceeds the second reference voltage, the second comparator output voltage is high, the recovery time generation module completes its work, and the undervoltage latch signal output by the logic circuit is high.
[0042] If, during charge pump charging, the power supply voltage VDD drops, causing the first comparator output voltage to go low, the charge pump voltage is set to 0, awaiting the next charging cycle. This protection is triggered when the power supply fluctuates. It requires the power supply voltage VDD to be greater than the high threshold voltage VRH for a period exceeding the recovery time, meaning both the first and second comparators must be high for the undervoltage latch signal to be high. At this point, the power supply voltage VDD is considered normal and stable, thus providing more effective circuit protection.
[0043] Figure 3 The diagram presents the voltage waveforms of an undervoltage latch circuit with recovery time according to this invention, including the power supply voltage VDD, the output voltage of the first comparator, the output voltage of the second comparator, the charge pump voltage, and the undervoltage latch signal. The diagram illustrates the power supply voltage VDD during power-on and power-off, divided into two scenarios: the first scenario is a sudden power outage of VDD within the recovery time; the second scenario is a normal power-on and power-off of VDD. The waveforms are explained below:
[0044] ①T0~t1 time period: At this time, the power supply voltage VDD is less than the high threshold voltage VRH. The output of the first comparator and the output of the second comparator are both low level. The first inverter driving transistors NMOS1 and NMOS2 are turned on, the resistor R3 is bypassed, the charge pump voltage is set to 0, so the undervoltage latch signal is also low level.
[0045] ②T1~t2 time period: At this time, the power supply voltage VDD is greater than the high threshold voltage VRH, the output of the first comparator is high, the first inverter drives transistors NMOS1 and NMOS2 to turn off, resistor R3 is connected to the circuit, the charge pump voltage rises but has not yet reached the second reference voltage (the set recovery time has not been reached), so the output of the second comparator is low, and the undervoltage latch signal is low.
[0046] ③Temporal period t2~t3: At this time, the power supply voltage VDD fluctuates and is less than the low threshold voltage VRL. The output of the first comparator is low, the first inverter level drives transistors NMOS1 and NMOS2 to conduct, resistor R3 is bypassed, the charge pump voltage is set to 0, the output of the second comparator is low, and the undervoltage latch signal is also low.
[0047] ④T3~t4 time period: At this time, the power supply voltage VDD is greater than the high threshold voltage VRH, the output of the first comparator is high, the first inverter drives transistors NMOS1 and NMOS2 to turn off, resistor R3 is connected to the circuit, the charge pump voltage rises but has not yet reached the second reference voltage, so the output of the second comparator is low, and the undervoltage latch signal is low.
[0048] ⑤T4~t5 time period: During this time, the power supply voltage VDD continues to remain normal, and the output of the first comparator remains unchanged. When the charge pump voltage is greater than the second reference voltage, that is, after the set recovery time t4-t3 is met, the second comparator reverses and outputs a high level. At this time, the undervoltage latch signal outputs a high level.
[0049] During the time period t5~t6: At this time, the power supply voltage VDD is less than the low threshold voltage VRL, the output of the first comparator is low, the first inverter drives transistors NMOS1 and NMOS2 to conduct, resistor R3 is bypassed, the charge pump voltage is set to 0, the output of the second comparator is low, and the undervoltage latch signal is low.
[0050] Example 2: The difference from Example 1 is that, as shown in Example 2... Figure 4 As shown, the circuit of this invention has good expandability. For example, a charging current control circuit can be added to adjust the recovery time. Figure 4 A design example of an undervoltage latch circuit with adjustable recovery time is given. The figure adds a charging current control circuit to output a second charging current, which can be added to the first charging current provided by the bandgap reference circuit and act together on the charge pump circuit, thereby achieving the effect of adjusting the recovery time.
[0051] Undervoltage latch circuit design with adjustable recovery time, such as Figure 5 As shown. The sampling circuit, charge pump circuit, bandgap reference circuit, first comparator circuit, second comparator circuit, and logic circuit design are all consistent with those described above, and will not be repeated here. The difference is the addition of a charging current control circuit composed of transistors MC1 and MC2, and a current-limiting resistor RZ. MC1 and MC2 form a current mirror. The second charging current is determined by transistor MC2 and the current-limiting resistor RZ; therefore, the magnitude of the second charging current can be changed simply by altering the value of the current-limiting resistor RZ or the mirror ratio of the current mirror. The second charging current is summed with the first charging current, and together they charge capacitor C, changing the charging speed of capacitor C (also the length of its recovery time).
[0052] Compared with other undervoltage latch circuits, the advantages of this invention include:
[0053] 1. High-precision recovery time. Because a bandgap reference circuit is incorporated into the circuit, the generated voltage does not change with temperature and voltage. Therefore, the first charging current has high precision, enabling accurate recovery time.
[0054] 2. Preventing false reversals due to low voltage. By calculating the output voltages of the first and second comparators using logic circuitry, false reversal signals caused by undervoltage latch-up during power-on can be avoided. Furthermore, as mentioned earlier... Figure 3 As shown in the diagram, the recovery time generation module can effectively avoid power fluctuations and provide more effective circuit protection.
[0055] 3. Good scalability. As described in Example 2, the recovery time can be adjusted by adding a charging current control circuit.
[0056] Low cost. Easy to design and replicate, small footprint, and inexpensive.
[0057] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. An under voltage latch circuit with recovery time, characterized by, It includes a power supply voltage detection module and a recovery time generation module; the power supply voltage detection module consists of a sampling circuit and a first comparator circuit, and the recovery time generation module consists of a charge pump circuit and a second comparator circuit; the undervoltage latch circuit with recovery time also includes a bandgap reference circuit and logic circuits.
2. The under voltage latch circuit with recovery time according to claim 1, wherein, The power supply voltage detection module consists of three detection resistors, one switching NMOS transistor, four PMOS transistors, and three NMOS transistors. The sampling circuit consists of resistors R1, R2, and R3, and a switching NMOS1 transistor; The first comparator is composed of PMOS transistors M1, M2, M5, and M6 and NMOS1 transistors M3, M4, and M7; resistors R1, R2, and R3 are connected in series; the drain of the NMOS1 transistor is connected to the first terminal of resistor R3; the node where the drain of the NMOS1 transistor is connected to the first terminal of resistor R3 is also connected to the second terminal of resistor R2; and the source of the NMOS1 transistor is connected to the second terminal of resistor R3 and connected to the power supply GND.
3. The under voltage latch circuit with recovery time according to claim 2, wherein, The sources of transistors M1 and M2 are both connected to the drain of M5. The drain of M1 is connected to the drain and gate of M3 and the gate of M4. The drain of M2 is connected to the drain of M4 to form the first stage output of the first comparator, which is input to the gate of M7. The drain of M6 is connected to the drain of M7 to form the second stage output of the first comparator. The sources of M5 and M6 are connected to the power supply VDD, and their gates are connected to the first bias voltage. The sources of M3, M4, and M7 are connected to the power supply GND. The gate of M1 is the negative input of the first comparator, and the gate of M2 is the positive input of the first comparator.
4. An under voltage latch circuit with recovery time according to claim 3, characterized in that, The transistors M1, M2, M3, M4, and M5 together form the first stage of the first comparator, and the second stage of the first comparator is composed of transistors M6 and M7; wherein transistors M5 and M6 are current source transistors.
5. The under voltage latch circuit with recovery time according to claim 4, wherein, The recovery time generation module consists of a capacitor C, a switching NMOS2 transistor, four PMOS transistors, and three NMOS transistors; the charge pump circuit consists of a capacitor C and a switching NMOS2 transistor; the second comparator consists of PMOS transistors M8, M10, M11, and M12 and NMOS transistors M9, M13, and M14.
6. An under voltage latch circuit with recovery time according to claim 5, characterized in that, The drain of the NMOS2 transistor is connected to the first terminal of capacitor C, and this node is also connected to the positive input terminal of the second comparator; the source of the NMOS2 transistor is connected to the second terminal of capacitor C and connected to the power supply GND; the sources of transistors M11 and M12 are connected to the drain of M10; the drain of M11 is connected to the drain of M13, and the gate of M11 is connected to the gate of M14; the drain of M12 and the drain of M14 are connected to form the first stage output of the second comparator, which is input to the gate of M9; the drain of M8 is connected to the drain of M9 to form the second stage output of the second comparator.
7. The under voltage latch circuit with recovery time according to claim 6, wherein, The source terminals of M8 and M10 are connected to the power supply VDD, and their gate terminals are connected to the first bias voltage. The source terminals of M9, M13, and M14 are connected to the power supply GND. The gate terminal of M11 is the negative input terminal of the comparator, and the gate terminal of M12 is the positive input terminal of the comparator. Transistors M10, M11, M12, M13, and M14 together form the first stage of the comparator, and the second stage of the comparator is composed of transistors M8 and M9. Transistors M8 and M10 are current source transistors.
8. The under voltage latch circuit with recovery time according to claim 7, wherein, The logic circuit consists of a first inverter, a second inverter, a third inverter, and a first AND gate.
9. The under voltage latch circuit with recovery time according to claim 8, wherein, The undervoltage latch circuit with recovery time also includes a charging current control circuit; the charging current control circuit consists of transistors MC1 and MC2 and a current-limiting resistor RZ, with MC1 and MC2 forming a current mirror.