Visible light communication transmitting device

Abstract

This utility model discloses a visible light communication transmitting device, relating to the field of visible light communication technology. The visible light communication transmitting device includes a format conversion circuit, a bandwidth expansion circuit, a level bias circuit, and a modulation and LED array circuit connected in sequence. The input terminal of the format conversion circuit receives a high-speed differential electrical signal, and the output terminal outputs a serial electrical signal. The input terminal of the bandwidth expansion circuit receives the serial electrical signal, and the output terminal outputs an inverted high-speed signal. The input terminal of the level bias circuit receives the inverted high-speed signal, and the output terminal outputs a forward high-speed signal. The input terminal of the modulation and LED array circuit receives the forward high-speed signal, and the output terminal outputs visible light. This utility model can reduce the hardware cost of the device while ensuring a large bandwidth for the visible light communication device.

Description

Technical Field

[0001] This utility model relates to the field of visible light communication technology, and in particular to a visible light communication transmitting device. Background Technology

[0002] VLC (Visible Light Communication) uses light sources such as LEDs to emit visible light signals with rapid brightness changes to transmit information. It has advantages such as high single-point speed, abundant communication spectrum resources, no electromagnetic interference, and large system capacity, and is a key technology for future communication.

[0003] Traditional visible light communication transmitters generally use a serial signal access mode. This mode limits signal transmission rates, makes it difficult to support high-frequency signals, and causes rapid signal attenuation during transmission, significantly restricting transmission distance. To compensate for insufficient bandwidth, traditional visible light communication transmitters often employ multi-cascaded bridge T-type equalizers or digital equalizers for bandwidth extension. However, these equalizers have complex circuit structures, increasing hardware costs.

[0004] In summary, how to reduce the hardware cost of visible light communication devices while ensuring a large bandwidth has become a pressing technical problem in this field. Utility Model Content

[0005] The main purpose of this invention is to propose a visible light communication transmitting device that aims to ensure that the visible light communication device has a large bandwidth while reducing the hardware cost of the device.

[0006] To achieve the above objectives, the visible light communication transmitting device proposed in this utility model includes a format conversion circuit, a bandwidth expansion circuit, a level bias circuit, a modulation circuit, and an LED (Light Emitting Diode) array circuit connected in sequence.

[0007] The input terminal of the format conversion circuit receives a high-speed differential electrical signal, and the output terminal of the format conversion circuit outputs a serial electrical signal.

[0008] The input terminal of the bandwidth expansion circuit receives the serial electrical signal, and the output terminal of the bandwidth expansion circuit outputs a reverse high-speed signal.

[0009] The input terminal of the level bias circuit receives the reverse high-speed signal, and the output terminal of the level bias circuit outputs a positive high-speed signal.

[0010] The input terminal of the modulation and LED array circuit receives the positive high-speed signal, and the output terminal of the modulation and LED array circuit outputs visible light.

[0011] In one embodiment, the format conversion circuit includes a first impedance matching module, a first DC blocking module, and a signal conversion module that are electrically connected in sequence.

[0012] The first impedance matching module receives the high-speed differential electrical signal, and the signal conversion module outputs the serial electrical signal.

[0013] In one embodiment, the high-speed differential electrical signal includes a positive-phase signal and an inverted signal; the first impedance matching module includes a first resistor and a second resistor; the first DC blocking module includes a first capacitor and a second capacitor; and the signal conversion module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, and a first operational amplifier.

[0014] The first terminal of the first resistor receives the inverted signal, and the second terminal of the first resistor is grounded.

[0015] The first terminal of the second resistor receives the positive phase signal, and the second terminal of the second resistor is grounded.

[0016] The first terminal of the first capacitor receives the inverted signal, and the second terminal of the first capacitor is connected to the first terminal of the third resistor.

[0017] The first terminal of the second capacitor receives the positive phase signal, and the second terminal of the second capacitor is connected to the first terminal of the fourth resistor;

[0018] The inverting input terminal of the first operational amplifier is connected to the second terminal of the third resistor, the non-inverting input terminal of the first operational amplifier is connected to the second terminal of the fourth resistor, and the output terminal of the first operational amplifier outputs the serial electrical signal.

[0019] The fifth resistor is connected in parallel with the third capacitor, the first end of the fifth resistor is connected to the second end of the third resistor, and the second end of the fifth resistor is connected to the output terminal of the first operational amplifier.

[0020] The first end of the sixth resistor is connected to the second end of the fourth resistor, and the second end of the sixth resistor is grounded.

[0021] In one embodiment, the bandwidth extension circuit includes a second impedance matching module, a high-frequency compensation module, a low-frequency suppression module, and a synthesis module;

[0022] The first terminal of the second impedance matching module receives the serial electrical signal, and the second terminal of the second impedance matching module is grounded.

[0023] The first terminal of the high-frequency supplementation module receives the serial electrical signal, and the second terminal of the high-frequency supplementation module is connected to the inverting input terminal of the synthesis module;

[0024] The first terminal of the low-frequency suppression module receives the serial electrical signal, the second terminal of the low-frequency suppression module is connected to the inverting input terminal of the synthesis module, and the output terminal of the synthesis module outputs the inverted high-speed signal.

[0025] In one embodiment, the high-frequency compensation module includes a seventh resistor, a first inductor, and a fourth capacitor connected in sequence.

[0026] The second impedance matching module includes an eighth resistor, the first end of which receives the serial electrical signal, and the second end of which is grounded.

[0027] In one embodiment, the low-frequency suppression module includes a ninth resistor, a tenth resistor, an eleventh resistor, a second inductor, and a fifth capacitor; the synthesis module includes a second operational amplifier; and the bandwidth extension circuit further includes a twelfth resistor and a thirteenth resistor.

[0028] The first terminal of the ninth resistor receives the serial electrical signal, and the second terminal of the ninth resistor is connected to the first terminal of the tenth resistor and the first terminal of the eleventh resistor, respectively.

[0029] The second terminal of the tenth resistor is connected to the inverting input terminal of the second operational amplifier;

[0030] The second end of the eleventh resistor is connected to the second inductor and the fifth capacitor, respectively.

[0031] The first end of the twelfth resistor is connected to the inverting input terminal of the second operational amplifier, and the second end of the twelfth resistor is connected to the output terminal of the second operational amplifier.

[0032] The first end of the thirteenth resistor is connected to the non-inverting input of the second operational amplifier, and the second end of the thirteenth resistor is grounded.

[0033] In one embodiment, the level bias circuit includes a second DC blocking module and a bias module that are electrically connected;

[0034] The second DC blocking module receives the reverse high-speed signal, and the biasing module outputs the positive high-speed signal.

[0035] In one embodiment, the second DC blocking module includes a sixth capacitor, and the biasing module includes a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third operational amplifier;

[0036] The first terminal of the sixth capacitor receives the reverse high-speed signal, the second terminal of the sixth capacitor is connected to the first terminal of the fifteenth resistor, and the second terminal of the fifteenth resistor is connected to the inverting input terminal of the third operational amplifier.

[0037] The first end of the fourteenth resistor is connected to the inverting input of the third operational amplifier, the second end of the fourteenth resistor is connected to the output of the third operational amplifier, and the output of the third operational amplifier outputs the positive high-speed signal.

[0038] The first end of the sixteenth resistor is connected to the first end of the seventeenth resistor and the non-inverting input of the third operational amplifier, and the second end of the sixteenth resistor is grounded.

[0039] The second end of the seventeenth resistor is connected to the positive input terminal of the power supply of the third operational amplifier.

[0040] In one embodiment, the modulation and LED array circuit includes a driver array and an LED array, the driver array including multiple sets of driver units, and the LED array including multiple sets of light-emitting devices;

[0041] For each group of driving units and each group of light-emitting devices, the first end of the driving unit receives the positive high-speed signal, and the second end of the driving unit is connected to the light-emitting device to drive the light-emitting device to output visible light.

[0042] In one embodiment, for the first driving unit in each group of driving units and the first light-emitting device in each group of light-emitting devices, the first driving unit includes an eighteenth resistor, a nineteenth resistor, and a first transistor;

[0043] The first terminal of the first transistor is connected to the eighteenth resistor, and the other terminal of the eighteenth resistor receives the positive high-speed signal;

[0044] The second terminal of the first transistor is connected to the negative terminal of the first light-emitting device, and the positive terminal of the first light-emitting device is connected to a voltage source.

[0045] The third terminal of the first transistor is grounded after passing through the nineteenth resistor.

[0046] The present invention provides a visible light communication transmitting device, which includes a format conversion circuit, a bandwidth expansion circuit, a level bias circuit, and a modulation and LED array circuit connected in sequence. The input terminal of the format conversion circuit receives a high-speed differential electrical signal, and the output terminal of the format conversion circuit outputs a serial electrical signal. The input terminal of the bandwidth expansion circuit receives the serial electrical signal, and the output terminal of the bandwidth expansion circuit outputs an inverted high-speed signal. The input terminal of the level bias circuit receives the inverted high-speed signal, and the output terminal of the level bias circuit outputs a forward high-speed signal. The input terminal of the modulation and LED array circuit receives the forward high-speed signal, and the output terminal of the modulation and LED array circuit outputs visible light.

[0047] The visible light communication transmitting device provided by this invention employs a format conversion circuit, a bandwidth expansion circuit, a level bias circuit, and a modulation and LED array circuit connected in sequence. This enables the device to effectively expand the signal bandwidth without relying on a complex equalizer, converting the input high-speed differential signal into visible light that drives the LED array to emit high-speed signals. At the same time, compared with traditional visible light communication transmitting devices, this invention ensures that the visible light communication device has a large bandwidth without the need for a complex multi-level bridge T-type equalizer or digital equalizer, thereby reducing hardware costs. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0049] Figure 1 A schematic diagram of a visible light communication transmitting device according to an embodiment of the present invention;

[0050] Figure 2 A schematic diagram of the format conversion circuit in one embodiment of the visible light communication transmitting device provided by this utility model;

[0051] Figure 3 A schematic diagram of the bandwidth extension circuit in one embodiment of the visible light communication transmitting device provided by this utility model;

[0052] Figure 4 A schematic diagram of the level bias circuit in one embodiment of the visible light communication transmitting device provided by this utility model;

[0053] Figure 5 A schematic diagram of the modulation and LED array circuit in one embodiment of the visible light communication transmitting device provided by this utility model.

[0054] Figures 1 to 5 Explanation of icon numbers:

[0055]

[0056]

[0057] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0058] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0059] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0060] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0061] Traditional visible light communication transmitters generally use a serial signal access mode. This mode limits signal transmission rates, makes it difficult to support high-frequency signals, and causes rapid signal attenuation during transmission, significantly restricting transmission distance. To compensate for insufficient bandwidth, traditional visible light communication transmitters often employ multi-cascaded bridge T-type equalizers or digital equalizers for bandwidth extension. However, these equalizers have complex circuit structures, increasing hardware costs.

[0062] In summary, how to reduce the hardware cost of visible light communication devices while ensuring a large bandwidth has become a pressing technical problem in this field.

[0063] To address this technical problem, this invention provides a visible light communication transmitting device that reduces the device's hardware cost while ensuring a large bandwidth for the visible light communication device.

[0064] This invention proposes a visible light communication transmitting device.

[0065] Please see Figure 1 In one embodiment of the present invention, the visible light communication transmitting device includes a format conversion circuit 10, a bandwidth expansion circuit 20, a level bias circuit 30, and a modulation and LED circuit 40 connected in sequence.

[0066] The input terminal of the format conversion circuit 10 receives a high-speed differential electrical signal, and the output terminal OUT of the format conversion circuit 10 outputs a serial electrical signal Uo1;

[0067] The input terminal of the bandwidth expansion circuit 20 receives the serial electrical signal Uo1, and the output terminal OUT of the bandwidth expansion circuit 20 outputs the inverted high-speed signal Uo2.

[0068] The input terminal of the level bias circuit 30 receives the reverse high-speed signal Uo2, and the output terminal OUT of the level bias circuit 30 outputs the positive high-speed signal Uo3.

[0069] The input terminal of the modulation and LED circuit 40 receives a positive high-speed signal Uo3, and the output terminal OUT of the modulation and LED circuit 40 outputs visible light.

[0070] In this embodiment, the visible light communication transmitting device includes a format conversion circuit 10, a bandwidth expansion circuit 20, a level bias circuit 30, and a modulation and LED circuit 40. The format conversion circuit 10 receives a high-speed differential electrical signal, performs format conversion processing, and converts the high-speed differential electrical signal into a high-speed single-ended serial electrical signal Uo1. Then, the bandwidth expansion circuit 20 performs bandwidth expansion processing on the high-speed single-ended serial electrical signal Uo1, and by compensating for the attenuation of high-frequency signals, outputs a frequency-compensated inverse high-speed signal Uo2, thereby expanding the communication bandwidth of visible light transmission and ensuring the reliability of high-speed communication.

[0071] Furthermore, the level bias circuit 30 performs level bias processing on the frequency-compensated reverse high-speed signal Uo2, adjusts the DC level of the high-speed signal, and outputs the high-speed signal after level bias processing, namely the forward high-speed signal Uo3, so that the signal driving capability is strong.

[0072] Furthermore, the modulation and LED circuit 40 controls the driving LED array 402 based on the positive high-speed signal Uo3 processed by the level bias circuit 30, so as to drive the LED array 402 to emit visible light with brightness changes or visible light with different intensity changes that are synchronized with the frequency of the positive high-speed signal Uo3, thereby realizing visible light modulation.

[0073] Finally, the LED array 402 emits visible light with varying brightness or intensity that is synchronized with the frequency of the positive high-speed signal Uo3. In other words, it emits visible light modulated by the positive high-speed signal Uo3, thereby converting the electrical signal into a visible light signal and emitting illumination visible light carrying the positive high-speed signal Uo3 through the LED array 402.

[0074] In one feasible embodiment, the format conversion circuit 10 includes a first impedance matching module 101, a first DC blocking module 102, and a signal conversion module 103 that are electrically connected in sequence.

[0075] The first impedance matching module 101 receives high-speed differential electrical signals, and the signal conversion module 103 outputs serial electrical signals Uo1.

[0076] In this embodiment, as Figure 2 As shown, the format conversion circuit 10 includes a first impedance matching module 101, a first DC blocking module 102, and a signal conversion module 103 connected in sequence. The first impedance matching module 101 performs impedance matching processing on the high-speed differential electrical signal, the first DC blocking module 102 performs DC blocking processing on the processed signal, and the signal conversion module 103 performs signal conversion processing to obtain a serial electrical signal Uo1.

[0077] In one feasible embodiment, the high-speed differential electrical signal includes a positive phase signal Up and an inverted phase signal Un. The first impedance matching module 101 includes a first resistor R1 and a second resistor R2. The first DC blocking module 102 includes a first capacitor C1 and a second capacitor C2. The signal conversion module 103 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, and a first operational amplifier U1A.

[0078] The first terminal of the first resistor R1 receives the inverted signal Un, and the second terminal of the first resistor R1 is grounded.

[0079] The first terminal of the second resistor R2 receives the positive phase signal Up, and the second terminal of the second resistor R2 is grounded.

[0080] The first terminal of the first capacitor C1 receives the inverted signal Un, and the second terminal of the first capacitor C1 is connected to the first terminal of the third resistor R3.

[0081] The first terminal of the second capacitor C2 receives the positive phase signal Up, and the second terminal of the second capacitor C2 is connected to the first terminal of the fourth resistor R4.

[0082] The inverting input terminal of the first operational amplifier U1A is connected to the second terminal of the third resistor R3, the non-inverting input terminal of the first operational amplifier U1A is connected to the second terminal of the fourth resistor R4, and the output terminal OUT of the first operational amplifier U1A outputs the serial electrical signal Uo1.

[0083] The fifth resistor R5 is connected in parallel with the third capacitor C3. The first end of the fifth resistor R5 is connected to the second end of the third resistor R3. The second end of the fifth resistor R5 is connected to the output terminal OUT of the first operational amplifier U1A.

[0084] The first end of the sixth resistor R6 is connected to the second end of the fourth resistor R4, and the second end of the sixth resistor R6 is grounded.

[0085] In this embodiment, as Figure 2 As shown, the high-speed differential electrical signal is divided into a positive phase signal Up and an inverted phase signal Un. The first impedance matching module 101 may include a first resistor R1 and a second resistor R2, or other devices or circuits with impedance matching function. The first DC blocking module 102 may include a first capacitor C1 and a second capacitor C2, or other devices or circuits with DC blocking function. The signal conversion module 103 may include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, and a first operational amplifier U1A, or other devices or circuits with signal conversion function.

[0086] For the inverting signal Un, impedance matching is performed through the first resistor R1 to ensure signal integrity, and then DC blocking is performed through the first capacitor C1. For the non-inverting signal Up, impedance matching is performed through the second resistor R2 to ensure signal integrity, and then DC blocking is performed through the second capacitor C2. Then, the signal is processed by the first operational amplifier U1A, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6. The positive input terminal V+ of the first operational amplifier U1A is connected to the power supply voltage VCC, and the negative input terminal V- is grounded.

[0087] In a feasible implementation scenario, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, and the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 are twice that of the third resistor R3; and the response speed of the output serial electrical signal Uo1 is improved by the third capacitor C3. The formula for converting the high-speed differential electrical signal into the high-speed single-ended serial electrical signal Uo1 is: Uo1=2(Up-Un).

[0088] In one feasible embodiment, the bandwidth extension circuit 20 includes a second impedance matching module 201, a high-frequency compensation module 202, a low-frequency suppression module 203, and a synthesis module 204.

[0089] The first terminal of the second impedance matching module 201 receives the serial electrical signal Uo1, and the second terminal of the second impedance matching module 201 is grounded.

[0090] The first terminal of the high-frequency supplementation module 202 receives the serial electrical signal Uo1, and the second terminal of the high-frequency supplementation module 202 is connected to the inverting input terminal of the synthesis module 204;

[0091] The first terminal of the low-frequency suppression module 203 receives the serial electrical signal Uo1, the second terminal of the low-frequency suppression module 203 is connected to the inverting input terminal of the synthesis module 204, and the output terminal OUT of the synthesis module 204 outputs the inverted high-speed signal Uo2.

[0092] In this embodiment, as Figure 3 As shown, the bandwidth extension circuit 20 includes a second impedance matching module 201, a high-frequency compensation module 202, a low-frequency suppression module 203, and a synthesis module 204. The second impedance matching module 201 performs impedance matching processing on the received serial electrical signal Uo1. The high-frequency compensation module 202 performs spread spectrum processing on the serial electrical signal Uo1 to obtain a high-frequency signal, and inputs the high-frequency signal to the inverting input terminal of the synthesis module 204. The low-frequency suppression module 203 performs low-frequency processing on the received serial electrical signal Uo1 to obtain a low-frequency signal, and inputs the low-frequency signal to the inverting input terminal of the synthesis module 204. The input signal at the inverting input terminal of the synthesis module 204 is essentially a spread spectrum signal obtained by superimposing the high-frequency signal and the low-frequency signal. After amplifying the spread spectrum signal, the synthesis module 204 outputs an inverted high-speed signal.

[0093] In one feasible embodiment, the high-frequency supplementation module 202 includes a seventh resistor R7, a first inductor L1 and a fourth capacitor C4 connected in sequence.

[0094] The second impedance matching module 201 includes an eighth resistor R8, the first end of which receives a serial electrical signal Uo1, and the second end of which is grounded.

[0095] In this embodiment, the high-frequency supplementation module 202 includes a seventh resistor R7, a first inductor L1 and a fourth capacitor C4 connected in sequence, or other devices or circuits with spread spectrum function; the second impedance matching module 201 can be an eighth resistor R8, or other devices or circuits with impedance matching function.

[0096] like Figure 3 As shown, the serial electrical signal Uo1 is impedance matched through the eighth resistor R8 to ensure signal integrity. The serial electrical signal Uo1 is spread spectrum processed by the high-frequency supplement module 202 composed of the seventh resistor R7, the first inductor L1 and the fourth capacitor C4 to output a high-frequency signal. The first inductor L1 and the fourth capacitor C4 are used to change the highest frequency cutoff frequency of the transmission channel. In practical application scenarios, by selecting the appropriate inductance value of the first inductor L1 and the appropriate capacitance value of the fourth capacitor C4, the spectrum can be widened. At the same time, the seventh resistor R7 is added to avoid the generation of pulse current.

[0097] In one feasible embodiment, the low-frequency suppression module 203 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second inductor L2 and a fifth capacitor C5, the synthesis module 204 includes a second operational amplifier U1B, and the bandwidth extension circuit 20 further includes a twelfth resistor R12 and a thirteenth resistor R13.

[0098] The first terminal of the ninth resistor R9 receives the serial electrical signal Uo1, and the second terminal of the ninth resistor R9 is connected to the first terminal of the tenth resistor R10 and the first terminal of the eleventh resistor R11, respectively.

[0099] The second terminal of the tenth resistor R10 is connected to the inverting input terminal of the second operational amplifier U1B;

[0100] The second terminal of the eleventh resistor R11 is connected to the second inductor L2 and the fifth capacitor C5, respectively.

[0101] The first end of the twelfth resistor R12 is connected to the inverting input terminal of the second operational amplifier U1B, and the second end of the twelfth resistor R12 is connected to the output terminal OUT of the second operational amplifier U1B.

[0102] The first terminal of the thirteenth resistor R13 is connected to the non-inverting input terminal of the second operational amplifier U1B, and the second terminal of the thirteenth resistor R13 is grounded.

[0103] In this embodiment, the low-frequency suppression module 203 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second inductor L2 and a fifth capacitor C5, or other devices or circuits with low-frequency suppression function; the synthesis module 204 is a second operational amplifier U1B, or other devices or circuits with signal amplification function.

[0104] like Figure 3 As shown, the serial electrical signal Uo1 undergoes low-frequency processing through the low-frequency suppression module 203, which consists of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the second inductor L2, and the fifth capacitor C5, outputting a low-frequency signal. The ninth resistor R9 and the tenth resistor R10 are used to adjust the starting amplitude of the low frequency, while the second inductor L2 and the fifth capacitor C5 are used to change the low-frequency cutoff frequency. The second operational amplifier U1B amplifies the high-speed differential electrical signal to obtain the inverted high-speed signal Uo2, with the following formula: Uo2 = -K * Uo1, where K represents the amplification factor. The amplification factor K in the low-frequency range is adjusted by the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12; the amplification factor K in the high-frequency range is adjusted by the seventh resistor R7, the first inductor L1, and the fourth capacitor C4.

[0105] In one feasible embodiment, the level bias circuit 30 includes a second DC blocking module 301 and a bias module 302 that are electrically connected;

[0106] The second DC blocking module 301 receives the reverse high-speed signal Uo2, and the bias module 302 outputs the positive high-speed signal Uo3.

[0107] In this embodiment, as Figure 4As shown, the level bias circuit 30 includes a second DC blocking module 301 and a bias module 302 that are electrically connected. The second DC blocking module 301 performs DC blocking processing on the received reverse high-speed signal Uo2, and the bias module 302 performs DC biasing and signal direction processing on the signal after DC blocking to obtain a positive high-speed signal Uo3.

[0108] In one feasible embodiment, the second DC blocking module 301 includes a sixth capacitor C6, and the biasing module 302 includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, and a third operational amplifier U1C.

[0109] The first terminal of the sixth capacitor C6 receives the reverse high-speed signal Uo2, the second terminal of the sixth capacitor C6 is connected to the first terminal of the fifteenth resistor R15, and the second terminal of the fifteenth resistor R15 is connected to the inverting input terminal of the third operational amplifier U1C.

[0110] The first end of the fourteenth resistor R14 is connected to the inverting input of the third operational amplifier U1C, and the second end of the fourteenth resistor R14 is connected to the output OUT of the third operational amplifier U1C. The output OUT of the third operational amplifier U1C outputs a positive high-speed signal Uo3.

[0111] The first terminal of the sixteenth resistor R16 is connected to the first terminal of the seventeenth resistor R17 and the non-inverting input terminal of the third operational amplifier U1C, respectively, and the second terminal of the sixteenth resistor R16 is grounded.

[0112] The second terminal of the seventeenth resistor R17 is connected to the positive input terminal V+ of the power supply of the third operational amplifier U1C.

[0113] In this embodiment, the second DC blocking module 301 is the sixth capacitor C6, or other devices or circuits with impedance matching functions; the bias module 302 includes the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the third operational amplifier U1C, or other devices or circuits with DC bias and signal direction processing functions. After the reverse high-speed signal Uo2 is DC blocked by the sixth capacitor C6, the bias circuit composed of the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the third operational amplifier U1C performs DC bias and signal direction processing to obtain the positive high-speed signal Uo3 with a preset DC level Vref.

[0114] In a feasible implementation scenario, the resistance values ​​of the fourteenth resistor R14 and the fifteenth resistor R15 are equal. The level bias circuit 30 processes the reverse high-speed signal Uo2 by blocking DC, biasing DC and processing the signal direction to obtain the positive high-speed signal Uo3. The relationship is: Uo3=-Uo2+2Vref, that is, Uo3=K*Uo1+2Vref, where the preset DC level Vref=VCC*R16 / (R16+R17).

[0115] In one feasible embodiment, the modulation and LED circuit 40 includes a driver array 401 and an LED array 402. The driver array 401 includes multiple sets of driver units, and the LED array 402 includes multiple sets of light-emitting devices.

[0116] For each group of driving units and each group of light-emitting devices, the first end of the driving unit receives a positive high-speed signal Uo3, and the second end of the driving unit is connected to the light-emitting device to drive the light-emitting device to output visible light.

[0117] In this embodiment, as Figure 5 As shown, the modulation and LED circuit 40 includes a driver array 401 and an LED array 402. The driver array 401 includes multiple sets of driver units, and the LED array 402 includes multiple sets of light-emitting devices. Each set of driver units and each set of light-emitting devices are connected in series in a one-to-one correspondence. The positive high-speed signal Uo3 drives each set of light-emitting devices to output visible light through each set of driver units. Among them, a set of light-emitting devices can be a set of LED lamps connected in series.

[0118] The driving array 401 drives the input positive high-speed signal Uo3 to drive the LED array 402 to emit light. The LED array 402 emits visible light with brightness changes or visible light with different intensities that are synchronized with the frequency of the positive high-speed signal Uo3. That is, it emits visible light modulated by the positive high-speed signal Uo3, realizing the conversion of electrical signal into visible light signal and the emission of illumination visible light carrying high-speed signal through the LED array 402.

[0119] In one feasible embodiment, for the first driving unit in each group of driving units and the first light-emitting device in each group of light-emitting devices, the first driving unit includes an eighteenth resistor R18, a nineteenth resistor R19 and a first transistor Q11;

[0120] The first terminal of the first transistor Q11 is connected to the eighteenth resistor R18, and the other terminal of the eighteenth resistor R18 receives the positive high-speed signal Uo3.

[0121] The second terminal of the first transistor Q11 is connected to the negative terminal of the first light-emitting device, and the positive terminal of the first light-emitting device is connected to the voltage source Vsource.

[0122] The third terminal of the first transistor Q11 is grounded after passing through the nineteenth resistor R19.

[0123] In this embodiment, as Figure 5 As shown, for the first driving unit in each group of driving units and the first light-emitting device in each group of light-emitting devices, the first driving unit includes the eighteenth resistor R18, the nineteenth resistor R19 and the first transistor Q11, and the first light-emitting device includes LED11, LED12 and LED1N connected in series; similarly, for the Mth driving unit in each group of driving units and the Mth light-emitting device in each group of light-emitting devices, the Mth driving unit includes RM1, RM2 and the Mth transistor QM1, and the Mth light-emitting device includes LEDM1, LEDM2 and LEDMN connected in series. The positive terminal of each group of light-emitting devices is connected to the voltage source Vsource. The specific number of driving units and light-emitting devices can be set according to the actual application scenario, and this embodiment does not make a specific limitation on this.

[0124] When there is no high-speed signal, the Uo1 signal can be regarded as 0 level, Uo3 = 2Vref, which drives the transistors Q11 to QM1 of the drive array 401 to conduct, and current flows through LED11 to LED1N and LEDM1-LEDMN in the LED array 402, emitting stable light, and the LED array 402 realizes illumination.

[0125] When there is a high-speed signal, Uo1 is at a high level, Uo3 = K * Uo1 + 2Vref. At this time, Uo3 is greater than 2Vref, and the LED array 402 emits stronger light. Conversely, when Uo1 is at a low level, Uo3 = K * Uo1 + 2Vref. At this time, Uo3 is less than 2Vref, and the LED array 402 emits weaker light.

[0126] Therefore, by controlling the LED array 402 to emit light with varying intensity, the high-speed signal modulates the visible light, converting the electrical signal into a visible light signal, resulting in a strong emitted signal. Simultaneously, due to the extremely high frequency of the high-speed signal, the human eye experiences a residual effect, thus perceiving primarily stable light; the visible light emitted by the LED array 402 can still provide illumination.

[0127] In summary, the visible light communication transmitting device provided in this embodiment employs a format conversion circuit 10, a bandwidth expansion circuit 20, a level bias circuit 30, and a modulation and LED circuit 40 connected in sequence. This enables the device to effectively expand the signal bandwidth without relying on a complex equalizer, converting the input high-speed differential signal into visible light that drives the LED array 402 to emit high-speed signals. At the same time, compared with traditional visible light communication transmitting devices, this embodiment ensures that the visible light communication device has a large bandwidth while eliminating the need for complex multi-level bridge T-type equalizers or digital equalizers, thereby reducing hardware costs.

[0128] The above are merely exemplary embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural transformations made based on the technical concept of this utility model and the contents of the specification and drawings of this utility model, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A visible light communication transmitting device, characterized in that, The visible light communication transmitting device includes a format conversion circuit, a bandwidth expansion circuit, a level bias circuit, a modulation and LED array circuit connected in sequence. The input terminal of the format conversion circuit receives a high-speed differential electrical signal, and the output terminal of the format conversion circuit outputs a serial electrical signal. The input terminal of the bandwidth expansion circuit receives the serial electrical signal, and the output terminal of the bandwidth expansion circuit outputs a reverse high-speed signal. The input terminal of the level bias circuit receives the reverse high-speed signal, and the output terminal of the level bias circuit outputs a positive high-speed signal. The input terminal of the modulation and LED array circuit receives the positive high-speed signal, and the output terminal of the modulation and LED array circuit outputs visible light.

2. The visible light communication transmitting apparatus of claim 1, wherein, The format conversion circuit includes a first impedance matching module, a first DC blocking module, and a signal conversion module that are electrically connected in sequence. The first impedance matching module receives the high-speed differential electrical signal, and the signal conversion module outputs the serial electrical signal.

3. The visible light communication transmitting apparatus of claim 2, wherein, The high-speed differential electrical signal includes a positive phase signal and an inverted phase signal. The first impedance matching module includes a first resistor and a second resistor. The first DC blocking module includes a first capacitor and a second capacitor. The signal conversion module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, and a first operational amplifier. The first terminal of the first resistor receives the inverted signal, and the second terminal of the first resistor is grounded. The first terminal of the second resistor receives the positive phase signal, and the second terminal of the second resistor is grounded. The first terminal of the first capacitor receives the inverted signal, and the second terminal of the first capacitor is connected to the first terminal of the third resistor. The first terminal of the second capacitor receives the positive phase signal, and the second terminal of the second capacitor is connected to the first terminal of the fourth resistor; The inverting input terminal of the first operational amplifier is connected to the second terminal of the third resistor, the non-inverting input terminal of the first operational amplifier is connected to the second terminal of the fourth resistor, and the output terminal of the first operational amplifier outputs the serial electrical signal. The fifth resistor is connected in parallel with the third capacitor, the first end of the fifth resistor is connected to the second end of the third resistor, and the second end of the fifth resistor is connected to the output terminal of the first operational amplifier. The first end of the sixth resistor is connected to the second end of the fourth resistor, and the second end of the sixth resistor is grounded.

4. The visible light communication transmitting apparatus of claim 1, wherein, The bandwidth extension circuit includes a second impedance matching module, a high-frequency compensation module, a low-frequency suppression module, and a synthesis module; The first terminal of the second impedance matching module receives the serial electrical signal, and the second terminal of the second impedance matching module is grounded. The first terminal of the high-frequency supplementation module receives the serial electrical signal, and the second terminal of the high-frequency supplementation module is connected to the inverting input terminal of the synthesis module; The first terminal of the low-frequency suppression module receives the serial electrical signal, the second terminal of the low-frequency suppression module is connected to the inverting input terminal of the synthesis module, and the output terminal of the synthesis module outputs the inverted high-speed signal.

5. The visible light communication transmitting apparatus of claim 4, wherein, The high-frequency supplement module includes a seventh resistor, a first inductor, and a fourth capacitor connected in sequence. The second impedance matching module includes an eighth resistor, the first end of which receives the serial electrical signal, and the second end of which is grounded.

6. The visible light communication transmitting apparatus of claim 4, wherein, The low-frequency suppression module includes a ninth resistor, a tenth resistor, an eleventh resistor, a second inductor, and a fifth capacitor; the synthesis module includes a second operational amplifier; and the bandwidth extension circuit further includes a twelfth resistor and a thirteenth resistor. The first terminal of the ninth resistor receives the serial electrical signal, and the second terminal of the ninth resistor is connected to the first terminal of the tenth resistor and the first terminal of the eleventh resistor, respectively. The second terminal of the tenth resistor is connected to the inverting input terminal of the second operational amplifier; The second end of the eleventh resistor is connected to the second inductor and the fifth capacitor, respectively. The first end of the twelfth resistor is connected to the inverting input terminal of the second operational amplifier, and the second end of the twelfth resistor is connected to the output terminal of the second operational amplifier. The first end of the thirteenth resistor is connected to the non-inverting input of the second operational amplifier, and the second end of the thirteenth resistor is grounded.

7. The visible light communication transmitting apparatus of claim 1, wherein, The level bias circuit includes a second DC blocking module and a bias module that are electrically connected; The second DC blocking module receives the reverse high-speed signal, and the biasing module outputs the positive high-speed signal.

8. The visible light communication transmitting apparatus of claim 7, wherein, The second DC blocking module includes a sixth capacitor, and the biasing module includes a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third operational amplifier; The first terminal of the sixth capacitor receives the reverse high-speed signal, the second terminal of the sixth capacitor is connected to the first terminal of the fifteenth resistor, and the second terminal of the fifteenth resistor is connected to the inverting input terminal of the third operational amplifier. The first end of the fourteenth resistor is connected to the inverting input of the third operational amplifier, the second end of the fourteenth resistor is connected to the output of the third operational amplifier, and the output of the third operational amplifier outputs the positive high-speed signal. The first end of the sixteenth resistor is connected to the first end of the seventeenth resistor and the non-inverting input of the third operational amplifier, and the second end of the sixteenth resistor is grounded. The second end of the seventeenth resistor is connected to the positive input terminal of the power supply of the third operational amplifier.

9. The visible light communication transmitting apparatus of claim 1, wherein, The modulation and LED array circuit includes a driver array and an LED array. The driver array includes multiple sets of driver units, and the LED array includes multiple sets of light-emitting devices. For each group of driving units and each group of light-emitting devices, the first end of the driving unit receives the positive high-speed signal, and the second end of the driving unit is connected to the light-emitting device to drive the light-emitting device to output visible light.

10. The visible light communication transmitting apparatus of claim 9, wherein, For the first driving unit in each group of driving units and the first light-emitting device in each group of light-emitting devices, the first driving unit includes an eighteenth resistor, a nineteenth resistor, and a first transistor; The first terminal of the first transistor is connected to the eighteenth resistor, and the other terminal of the eighteenth resistor receives the positive high-speed signal; The second terminal of the first transistor is connected to the negative terminal of the first light-emitting device, and the positive terminal of the first light-emitting device is connected to a voltage source. A third terminal of the first transistor is connected to ground through the nineteenth resistor.

Images