Circuit board structure
By setting a solder resist layer in the circuit board structure to reduce the height difference at the bottom of the groove area, the problem of air bubbles caused by unevenness at the bottom of the groove area is solved, thereby improving the reliability and electrical conductivity stability of the product.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- UNIMICRON TECH CORP
- Filing Date
- 2025-08-08
- Publication Date
- 2026-07-03
AI Technical Summary
In existing circuit board structures, there is a height difference between the bottom of the groove area and the substrate, which causes air bubbles to form in the conductive paste at the solder joints, affecting the bonding strength and electrical conductivity stability, and thus reducing the reliability of the end electronic products.
By setting a solder mask layer in the circuit board structure to reduce the height difference at the bottom of the recessed area, surface flatness is ensured, thereby avoiding the generation of air bubbles during the application of conductive paste.
It improves the flatness of the groove area, avoids the formation of air bubbles, and enhances the reliability and electrical conductivity stability of electronic products.
Smart Images
Figure CN224460106U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a circuit board structure, and more particularly to a circuit board structure having a recessed area. Background Technology
[0002] In existing technologies, there is often a height difference between the wiring at the bottom of the recessed area of a circuit board and the substrate. This unevenness can lead to air bubbles being trapped in the conductive paste during subsequent electronic component mounting processes due to the irregular bottom surface. These air bubbles remaining in the solder joints may reduce the bonding strength and electrical conductivity stability, thereby affecting the long-term reliability of the final electronic product. Utility Model Content
[0003] To address the aforementioned problems, this utility model provides a circuit board structure.
[0004] An embodiment of this utility model discloses a circuit board structure comprising a base layer, a first circuit layer, a first extension layer structure, and a first solder resist layer. The first circuit layer is disposed on one side of the base layer, and has a first groove exposing the base layer. The first extension layer structure is disposed on the side of the first circuit layer opposite to the base layer, and has a second groove exposing both the first circuit layer and the first groove. The first solder resist layer fills the first groove. The surface of the base layer and the surface of the first circuit layer have a first height difference, and the surface of the first solder resist layer and the surface of the first circuit layer have a second height difference, wherein the second height difference is less than the first height difference.
[0005] According to the circuit board structure disclosed in the above embodiments, the flatness of the bottom of the groove area can be improved by using a solder resist layer, thereby making it less likely for air bubbles to be generated when applying conductive paste to the groove area, and avoiding air bubbles from affecting product reliability.
[0006] The above description of the present invention and the following description of the embodiments are used to demonstrate and explain the principle of the present invention, and to provide a further explanation of the claims of the present invention. Attached Figure Description
[0007] Figure 1 A cross-sectional schematic diagram of a circuit board structure according to an embodiment of the present invention is presented.
[0008] Figures 2 to 12 for Figure 1 Cross-sectional diagrams of the circuit board structure at different process stages. Detailed Implementation
[0009] The detailed features and advantages of this utility model are described below in the embodiments. The content is sufficient for any person skilled in the art to understand the technical content of this utility model and to implement it accordingly. Furthermore, based on the disclosure, claims, and drawings in this specification, any person skilled in the art can easily understand the related objectives and advantages of this utility model. The following embodiments further illustrate the viewpoints of this utility model in detail, but are not intended to limit the scope of this utility model in any way.
[0010] Please see Figure 1 , Figure 1 A cross-sectional schematic diagram of a circuit board structure according to an embodiment of the present invention is presented. The circuit board structure 1 includes a base layer 11, a first circuit layer 12, a first solder resist layer 13, a first external layer structure 15, a conductive layer 16, a second circuit layer 12', a second solder resist layer 13', and a second external layer structure 15'. The conductive layer 16, the second circuit layer 12', the second solder resist layer 13', and the second external layer structure 15' are selectively configured layers or structures.
[0011] A first circuit layer 12 is disposed on one side of a substrate layer 11 and has a first groove C1, which exposes the substrate layer 11. A first extension layer structure 15 is disposed on the side of the first circuit layer 12 opposite to the substrate layer 11 and has a second groove C2, which exposes both the first circuit layer 12 and the first groove C1. A first solder resist layer 13 fills the first groove C1. The surface of the substrate layer 11 and the surface of the first circuit layer 12 have a first height difference h1, and the surface of the first solder resist layer 13 and the surface of the first circuit layer 12 have a second height difference h2, wherein the second height difference h2 is less than the first height difference h1. Further, the second height difference h2 can be greater than 10 micrometers (μm) and less than 50 μm.
[0012] In this embodiment, the second circuit layer 12' is disposed on the other side of the base layer 11 and has a third groove C1', which exposes the base layer 11. The second extension layer structure 15' is disposed on the side of the second circuit layer 12' opposite to the base layer 11 and has a fourth groove C2', which exposes the second circuit layer 12' and the third groove C1'. The second solder resist layer 13' fills the third groove C1'. The surface of the base layer 11 and the surface of the second circuit layer 12' have a third height difference h3, and the surface of the second solder resist layer 13' and the surface of the second circuit layer 12' have a fourth height difference h4, wherein the fourth height difference h4 is less than the third height difference h3. Figure 1 The second circuit layer 12', the second solder resist layer 13' and the second external layer structure 15' are illustrated as symmetrical structures with the first circuit layer 12, the first solder resist layer 13 and the first external layer structure 15 about the base layer 11 as the axis of symmetry, but the present invention is not limited thereto.
[0013] In this embodiment, the base layer 11 may include a substrate 111, a first inner circuit layer 112, a first inner dielectric layer 113, a first inner conductive layer 114, a second inner circuit layer 112', a second inner dielectric layer 113', and a second inner conductive layer 114'. The first inner circuit layer 112 is disposed on one side of the substrate 111, and the first inner dielectric layer 113 is disposed on the side of the first inner circuit layer 112 opposite to the substrate 111. The first circuit layer 12 is electrically connected to the first inner circuit layer 112 through a first conductive via V penetrating the first inner dielectric layer 113. The first conductive via V may be obtained by filling a conductive material into a first blind via BH of the first inner dielectric layer 113. The first inner conductive layer 114 is a selectively disposed layer between the first circuit layer 12 and the first inner dielectric layer 113. Similarly, a second inner circuit layer 112' is disposed on the other side of the substrate 111, and a second inner dielectric layer 113' is disposed on the side of the second inner circuit layer 112' opposite to the substrate 111. The second circuit layer 12' is electrically connected to the second inner circuit layer 112' through a second conductive via V' penetrating the second inner dielectric layer 113'. The second conductive via V' can be obtained by filling a conductive material into a second blind via BH' of the second inner dielectric layer 113'. The second inner conductive layer 114' is a selectively disposed layer between the second circuit layer 12' and the second inner dielectric layer 113'. Figure 1 The substrate 11 is illustrated by way of example, including the layers and the arrangement relationship between the layers. In other embodiments, the substrate 11 may include a substrate 111, a first inner circuit layer 112, and a first inner dielectric layer 113 but not a second inner circuit layer 112' and a second inner dielectric layer 113'. Alternatively, the substrate 11 may include other types of layers and / or have other types of layer arrangement relationships.
[0014] In this embodiment, the first solder resist layer 13 may partially overlap the first circuit layer 12 and / or may contain epoxy resin or other materials.
[0015] In this embodiment, the first external layer structure 15 may include a first external dielectric layer 151, a first external circuit layer 152, and a first external solder mask layer 153. The first external dielectric layer 151 is disposed on the side of the first external circuit layer 152 opposite to the substrate layer 11, the first external circuit layer 152 is disposed on the side of the first external dielectric layer 151 opposite to the first external circuit layer 152, and the first external solder mask layer 153 is disposed on the side of the first external circuit layer 152 opposite to the first external dielectric layer 151. Similarly, the second external layer structure 15' may include a second external dielectric layer 151', a second external circuit layer 152', and a second external solder mask layer 153'. The second outer dielectric layer 151' is disposed on the side of the second outer circuit layer 152' relative to the substrate layer 11, the second outer circuit layer 152' is disposed on the side of the second outer dielectric layer 151' relative to the second outer circuit layer 152', and the second outer solder resist layer 153' is disposed on the side of the second outer circuit layer 152' relative to the second outer dielectric layer 151'. Figure 1 The present invention exemplarily illustrates the layers and their arrangement relationships within the first and second external layer structures 15 and 15', but is not limited thereto.
[0016] In this embodiment, the circuit board structure 1 may optionally have a through-hole TH. The through-hole TH penetrates the first extension layer 15 and the base layer 11. The through-hole TH may selectively penetrate the second extension layer 15'.
[0017] In this embodiment, the circuit board structure 1 may optionally include a conductive layer 16. The conductive layer 16 is disposed between the first outer circuit layer 152 and the first outer solder mask layer 153, and is disposed on the inner surface of the through-hole TH. The conductive layer 16 may optionally be disposed between the second outer circuit layer 152' and the second outer solder mask layer 153'.
[0018] Please see Figures 2 to 12 See also Figure 1 ,in Figures 2 to 12 for Figure 1 The circuit board structure 1 in the diagram is a cross-sectional view at different process stages.
[0019] First, such as Figure 2 As shown, a substrate 111 is provided, and a first internal circuit layer 112 is formed on one side of the substrate 111. The first internal circuit layer 112 may be made of a conductive material, such as, but not limited to, copper, and may be formed by, but not limited to, an etching process. The present invention may optionally form a second internal circuit layer 112' on the other side of the substrate 111 using the same process as the first internal circuit layer 112.
[0020] Next, as Figure 3As shown, a first inner dielectric layer 113 and a first inner conductive layer 114 are formed on one side of the first inner circuit layer 112 opposite to the substrate 111. The first inner dielectric layer 113 and the first inner conductive layer 114 are formed on the first inner circuit layer 112 by, for example but not limited to, a lamination process. The first inner conductive layer 114 is made of, for example but not limited to, copper foil. In this invention, a second inner dielectric layer 113' and a second inner conductive layer 114' can be selectively formed on the second inner circuit layer 112' on the other side of the substrate 111 using the same process as the first inner dielectric layer 113.
[0021] Next, as Figure 4 As shown, a first blind via BH is formed in the first inner dielectric layer 113 and the first inner conductive layer 114. The first blind via BH extends from the first inner conductive layer 114 to the first inner circuit layer 112 to expose the first inner circuit layer 112. Alternatively, the present invention can selectively form a second blind via BH' in the second inner dielectric layer 113' and the second inner conductive layer 114' on the other side of the substrate 111 using the same process as the first blind via BH.
[0022] Next, as Figure 5 As shown, conductive material is filled into the first blind via BH to form a first conductive via V, and a first circuit layer 12 is formed in the first inner conductive layer 114, which is then patterned to give the first circuit layer 12 a first groove C1. The above process is, for example, but not limited to, a modified semi-additive process (mSAP). The conductive material is, for example, but not limited to, copper. This invention can selectively fill conductive material into the second blind via BH' on the other side of the substrate 111 to form a second conductive via V', and form a second circuit layer 12' in the second inner conductive layer 114' using the same process as the first circuit layer 12, wherein the second circuit layer 12' has a third groove C1'. Figure 4 The example presents two grooves, but in other embodiments, the number of grooves may be one or more than two, and this invention is not limited thereto.
[0023] Next, as Figure 6 As shown, a first solder resist layer 13 is filled into the first groove C1 such that the height difference between the surface of the first solder resist layer 13 and the surface of the first circuit layer 12 is less than the height difference between the surface of the first inner dielectric layer 113 and the surface of the first circuit layer 12. Specifically, the material of the first solder resist layer 13 may include epoxy resin or other materials. Optionally, a second solder resist layer 13' can be formed on the other side of the substrate 111 using the same process.
[0024] Next, as Figure 7As shown, a first release film 14 is formed on the first circuit layer 12 and the first solder resist layer 13 to perform release film pre-pressing. In this invention, a second release film 14' can be selectively formed on the second circuit layer 12' and the second solder resist layer 13' on the other side of the substrate 111 to perform release film pre-pressing.
[0025] Next, as Figure 8 As shown, a first outer dielectric layer 151 is formed on the first circuit layer 12 and the first release film 14, and a first outer circuit layer 152 is formed on the side of the first outer dielectric layer 151 opposite to the substrate 111. The first outer circuit layer 152 can be made of a conductive material, such as, but not limited to, copper. The first outer dielectric layer 151 and the first outer circuit layer 152 are formed, for example, but not limited to, by a lamination process. In this invention, the second outer dielectric layer 151' and the second outer circuit layer 152' can be selectively formed on the second circuit layer 12' and the second release film 14' on the other side of the substrate 111 using the same process.
[0026] Next, as Figure 9 As shown, a through-hole TH is formed in the circuit board structure 1, penetrating the first outer circuit layer 152, the first outer dielectric layer 151, the first inner dielectric layer 113, the first inner circuit layer 112, and the substrate 111. This invention can selectively allow the through-hole TH to penetrate the second outer circuit layer 152', the second outer dielectric layer 151', the second inner dielectric layer 113', and the second inner circuit layer 112'.
[0027] Next, as Figure 10 As shown, a conductive layer 16 is formed on one side of the first outer circuit layer 152 opposite to the first outer dielectric layer 151 and on the inner surface of the via TH. The conductive layer 16 located on the inner surface of the via TH can be electrically connected to the first inner circuit layer 112. The conductive layer 16 is made of copper, for example, but not limited to. The via TH and the conductive layer 16 are formed, for example, but not limited to, using a subtractive process. In this invention, the conductive layer 16 can optionally also be formed on the other side of the substrate 111 on the side of the second outer circuit layer 152' opposite to the second outer dielectric layer 151', and the via TH can also be electrically connected to the second inner circuit layer 112'.
[0028] Next, as Figure 11 As shown, a first external solder resist layer 153 is formed on the side of the first external circuit layer 152 opposite to the conductive layer 16. This invention can selectively provide a second external solder resist layer 153' on the side of the second external circuit layer 152' opposite to the conductive layer 16 on the other side of the substrate 111. This invention can, but is not limited to, remove portions of the first external circuit layer 152, the first external solder resist layer 153, the second external circuit layer 152', the second external solder resist layer 153', and the conductive layer 16 by laser processing.
[0029] Next, as Figure 12 As shown, the first outer dielectric layer 151 and the first release film 14 are cut, such as, but not limited to, laser cutting and / or outline cutting, to form a first cutting groove S. This invention can selectively cut the second outer dielectric layer 151' and the second release film 14' on the other side of the substrate 111 to form a second cutting groove S'.
[0030] Next, return to Figure 1 The first outer solder resist layer 153, conductive layer 16, first outer circuit layer 152, first outer dielectric layer 151, and first release film 14 are removed from the area surrounded by the first cutting groove S to form the second groove C2. This invention can selectively remove the area surrounded by the second cutting groove S' on the other side of the substrate 111 to form a fourth groove C2'. The above process yields... Figure 1 The circuit board structure shown is 1.
[0031] According to the circuit board structure disclosed in the above embodiments, the flatness of the bottom of the groove area can be improved by using a solder resist layer, thereby making it less likely for air bubbles to be generated when applying conductive paste to the groove area, and avoiding air bubbles from affecting product reliability.
[0032] [Symbol Explanation]
[0033] 1: Circuit board structure
[0034] 11: Basal layer
[0035] 111:Substrate
[0036] 112: First Inner Circuit Layer
[0037] 112': Second Inner Circuit Layer
[0038] 113: First inner dielectric layer
[0039] 113': Second inner dielectric layer
[0040] 114: First inner conductive layer
[0041] 114': Second inner conductive layer
[0042] 12: First Line Layer
[0043] 12': Second line layer
[0044] 13: First solder resist layer
[0045] 13': Second weld resist layer
[0046] 14: First release membrane
[0047] 14': Second release membrane
[0048] 15: First outer layer structure
[0049] 151: First outer dielectric layer
[0050] 152: First outer circuit layer
[0051] 153: First outer weld shielding layer
[0052] 15': Second outer layer structure
[0053] 151': Second outer dielectric layer
[0054] 152': Second outer circuit layer
[0055] 153': Second outer weld shielding layer
[0056] 16: Conductive layer
[0057] BH: First blind hole
[0058] V: First conductive via
[0059] BH': Second blind hole
[0060] V': Second conductive via
[0061] TH: Through hole
[0062] S: First cutting groove
[0063] S': Second cutting groove
[0064] C1: First groove
[0065] C2: Second groove
[0066] C1': Third groove
[0067] C2': Fourth groove
[0068] h1: First height difference
[0069] h2: Second elevation difference
[0070] h3: Third elevation difference
[0071] h4: Fourth height difference.
Claims
1. A circuit board structure, characterized by, Include: basal layer; A first circuit layer is disposed on one side of the substrate layer, wherein the first circuit layer has a first groove that exposes the substrate layer; A first external layer structure is disposed on one side of the first circuit layer relative to the base layer, wherein the first external layer structure has a second groove, the second groove exposing the first circuit layer and the first groove; as well as A first solder resist layer is filled in the first groove; The surface of the base layer has a first height difference with the surface of the first circuit layer, and the surface of the first solder resist layer has a second height difference with the surface of the first circuit layer, wherein the second height difference is less than the first height difference.
2. The circuit board structure according to claim 1, characterized by The second height difference is greater than 10 micrometers and less than 50 micrometers.
3. The circuit board structure according to claim 1, characterized by The first solder resist layer partially overlaps the first circuit layer.
4. The circuit board structure according to claim 1, characterized by The first solder resist layer contains epoxy resin.
5. The circuit board structure of claim 1, wherein The base layer comprises: substrate; An internal circuit layer is disposed on one side of the substrate; and A dielectric layer is disposed on one side of the inner circuit layer relative to the substrate, and the first circuit layer is electrically connected to the inner circuit layer through a conductive via penetrating the dielectric layer.
6. The circuit board structure of claim 1, wherein The first external layer structure includes: A dielectric layer is disposed on the side of the first circuit layer relative to the substrate layer; An outer circuit layer is disposed on one side of the dielectric layer opposite to the first circuit layer; and An outer solder mask layer is disposed on the side of the outer circuit layer opposite to the dielectric layer.
7. The circuit board structure according to claim 6, characterized in that The circuit board structure has a through hole that penetrates the first outer layer structure and the base layer, and the circuit board structure further includes: A conductive layer is disposed between the outer circuit layer and the outer solder mask layer, and is disposed on the inner surface of the through hole.
8. The circuit board structure of claim 1, wherein Also includes: A second circuit layer is disposed on the other side of the substrate layer, wherein the second circuit layer has a third groove that exposes the substrate layer; A second external layer structure is disposed on one side of the second circuit layer relative to the substrate layer, wherein the second external layer structure has a fourth groove, the fourth groove exposing the second circuit layer and the third groove; as well as A second solder resist layer is filled in the third groove; The surface of the base layer and the surface of the second circuit layer have a third height difference, and the surface of the second solder resist layer and the surface of the second circuit layer have a fourth height difference, wherein the fourth height difference is less than the third height difference.