Power semiconductor devices

Abstract

This invention provides a power semiconductor device. The top corner of the metal field plate in the power semiconductor device is chamfered, and the dihedral angle formed by the side surface and bottom surface of the metal field plate is acute. Based on this, the passivation layer covering the multiple metal field plates also has the same morphological characteristics at its position relative to the metal field plates. This helps to disperse stress in the passivation layer, preventing crack formation due to stress concentration at the corners, thereby effectively blocking external environmental interference to the device's internal structure and improving the device's stability and reliability.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to a power semiconductor device. Background Technology

[0002] To meet the design requirements of power devices, special structures are typically designed at the device terminals to improve the device's breakdown voltage, reliability, and reduce leakage current. Common terminal designs include field plates, field limiting rings, junction extensions, and lateral doping, which are used to suppress the concentration of surface electric fields by changing the surface potential distribution, thereby improving the device's breakdown voltage.

[0003] like Figure 1 As shown, a field limiting ring 101 is formed within the substrate 100, and a field oxide layer 102 is formed on the surface of the substrate 100 to provide isolation and protection. A polysilicon field plate 103, an interlayer dielectric layer 104, and a metal field plate 105 are sequentially formed on the surface of the field oxide layer 102. To prevent external environmental factors such as moisture from affecting the device, a passivation layer 106 is also formed on the metal field plate 105 for protection.

[0004] However, stress concentration exists in the corner areas of the passivation layer 106, making it highly susceptible to crack formation 107 during power cycling tests (PC). This crack formation is particularly pronounced between the continuously spaced metal field plates 105 in the terminal region. The formation of these cracks 107 significantly increases the risk of moisture and contaminants from the external environment penetrating the device, affecting its electrical performance, and potentially leading to device failure.

[0005] Therefore, a new device structure design is urgently needed to solve the above-mentioned technical problems. Utility Model Content

[0006] The purpose of this invention is to provide a power semiconductor device to solve the problems of how to alleviate stress concentration at the corners of the passivation layer and how to avoid the formation of cracks in the passivation layer.

[0007] To solve the above-mentioned technical problems, this utility model provides a power semiconductor device, comprising:

[0008] Substrate, the substrate having a termination region;

[0009] Multiple metal field plates are spaced apart on the terminal area; wherein the top corners of the metal field plates are chamfered, and the dihedral angle formed by the side surface and the bottom surface of the metal field plate is an acute angle.

[0010] A passivation layer, which covers the plurality of metal field plates at least along the surface morphology of the plurality of metal field plates.

[0011] Optionally, in the power semiconductor device, the top corner of the metal field plate includes a rounded chamfer and / or a beveled chamfer.

[0012] Optionally, in the power semiconductor device, the angle range of the dihedral angle formed by the side surface of the metal field plate and the bottom surface of the metal field plate includes 45° to 85°.

[0013] Optionally, in the power semiconductor device, the power semiconductor device further includes a plurality of polysilicon field plates and an interlayer dielectric layer;

[0014] The plurality of polycrystalline silicon field plates are spaced apart on the surface of the substrate;

[0015] The interlayer dielectric layer covers the exposed surfaces of the plurality of polysilicon field plates and the substrate;

[0016] The plurality of metal field plates are spaced apart on the surface of the interlayer dielectric layer, and the passivation layer at least covers a portion of the surface of the plurality of metal field plates and the exposed surface of the interlayer dielectric layer; and...

[0017] The plurality of polycrystalline silicon field plates are arranged in a one-to-one correspondence with the plurality of metal field plates, and the projection of the metal field plate toward the substrate is located on the corresponding polycrystalline silicon field plate.

[0018] Optionally, in the power semiconductor device, the dihedral angle formed by the side surface of the polysilicon field plate and the bottom surface of the polysilicon field plate is an acute angle, so that at least the partial surfaces of the interlayer dielectric layer and the passivation layer, which are sequentially covered on the side surface of the polysilicon field plate, form obtuse angles with the horizontal plane extending away from the corresponding partial surfaces.

[0019] Optionally, in the power semiconductor device, the angle range of the dihedral angle formed by the side surface of the polycrystalline silicon field plate and the bottom surface of the polycrystalline silicon field plate includes 40° to 70°.

[0020] Optionally, in the power semiconductor device, in two adjacent metal field plates, the side of one metal field plate has an inclination direction opposite to the opposite side of the polycrystalline silicon field plate corresponding to the other metal field plate.

[0021] Optionally, in the power semiconductor device, the substrate further comprises a cellular region; a top metal layer is formed on the top surface of the cellular region, and the passivation layer further covers a portion of the surface of the top metal layer; and,

[0022] The top corner of the top metal layer is chamfered, and the dihedral angle formed by the side surface and the bottom surface of the top metal layer is acute.

[0023] Optionally, in the power semiconductor device, the top corner of the top metal layer includes a rounded chamfer and / or a beveled chamfer.

[0024] Optionally, in the power semiconductor device, the angle range of the dihedral angle formed by the side surface of the top metal layer and the bottom surface of the top metal layer includes 45° to 85°.

[0025] In summary, this utility model provides a power semiconductor device. Compared to the prior art, the top corner of the metal field plate in the power semiconductor device is chamfered, and the dihedral angle formed by the side surface and the bottom surface of the metal field plate is acute. Based on this, the passivation layer covering the multiple metal field plates also has the same morphological characteristics at its position relative to the metal field plates, which helps to disperse the stress in the passivation layer, avoids the formation of cracks due to stress concentration at the corner positions, and effectively blocks external environmental interference to the device's internal structure, improving the device's stability and reliability. Attached Figure Description

[0026] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention.

[0027] Figure 1 This is a schematic diagram of the formation of cracks in the passivation layer under stress in existing technology.

[0028] Figure 2 This is a schematic diagram of the terminal region of the power semiconductor device in an embodiment of this utility model.

[0029] Figure 3 This is a schematic diagram showing the side tilt of the polycrystalline silicon field plate in an embodiment of this utility model.

[0030] Figure 4 This is a schematic diagram of the first included angle and the adjacent supplementary angle in an embodiment of this utility model.

[0031] Figure 5 In this embodiment of the invention, when the side of the metal field plate is perpendicular, the third included angle is at... Figure 2 A magnified view of a portion of region A.

[0032] Figure 6 In this embodiment of the invention, when the side of the metal field plate is tilted, the third included angle is at... Figure 2 A magnified view of a portion of region A.

[0033] Figure 7 The fourth included angle in this embodiment of the utility model is Figure 2 A magnified view of a portion of region A.

[0034] Figure 8 This is a schematic diagram showing the tilt direction of the first side, the second side, and the third side in an embodiment of this utility model.

[0035] Figure 9 This is a schematic diagram of the terminal region and cell region of the power semiconductor device in an embodiment of this utility model.

[0036] And, in the attached image:

[0037] 100 - Substrate; 101 - Field confinement ring; 102 - Field oxide layer; 103 - Polysilicon field plate; 104 - Interlayer dielectric layer; 105 - Metal field plate; 106 - Passivation layer; 107 - Crack;

[0038] 200-Substrate; 201-Field confinement ring; 202-Field oxide layer; 203-Polysilicon field plate; 204-Interlayer dielectric layer; 205-Metal field plate; 206-Passivation layer; 207-Top metal layer;

[0039] θ1 - First included angle; θ1' - Adjacent supplementary angle of the first included angle; θ2 - Second included angle; θ3 - Third included angle; θ4 - Fourth included angle; θ5 - Fifth included angle; θ6 - Sixth included angle; C - Cell region; T - Terminal region; L1 - First straight dashed line; L2 - Second straight dashed line; L3 - Third straight dashed line. Detailed Implementation

[0040] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the purpose of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0041] Furthermore, the X-axis, Y-axis, and Z-axis directions referred to in this application specification are three mutually perpendicular directions in three-dimensional space. The horizontal plane refers to the plane formed by the X-axis and Y-axis.

[0042] Please see Figure 2 This embodiment provides a power semiconductor device, including:

[0043] Substrate 200, the substrate 200 having a termination region T;

[0044] Multiple metal field plates 205 are spaced apart on the terminal area T; wherein the top corner of each metal field plate 205 is chamfered, and the dihedral angle formed by the side surface and the bottom surface of each metal field plate 205 is acute.

[0045] A passivation layer 206 is applied to the plurality of metal field plates 205 at least along the surface morphology of the plurality of metal field plates 205.

[0046] Based on this, the power semiconductor device provided in this embodiment has a special morphology for the metal field plate 205 so that the passivation layer 206 also forms the same morphology at the corresponding position. This morphological feature is used to disperse the stress in the passivation layer 206, avoid the formation of cracks due to stress concentration at the corner position, and effectively block the interference of the external environment on the inside of the device, thereby improving the stability and reliability of the device.

[0047] The power semiconductor device provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0048] It should be noted that the power semiconductor device referred to in this embodiment can be a discrete device or an integrated device. The integrated device is an extension of the discrete device structure. Furthermore, to specifically illustrate the power semiconductor device, this embodiment uses an Insulated Gate Bipolar Transistor (IGBT) device as an example for detailed description.

[0049] Please continue reading. Figure 2 The power semiconductor device includes a substrate 200. The substrate 200 has a termination region T, within which P-type well regions and / or N-type well regions (not shown) are formed to create a specific electric field distribution, improving the device's breakdown voltage and reliability. A field limiting ring 201 is also formed within the substrate 200. The field limiting ring 201 includes a P-type ring, which is an electric field modulation structure used to optimize the electric field distribution of the termination region T by introducing multiple concentric or stepped P-type doped regions, suppressing electric field concentration caused by the PN junction edge curvature effect, thereby significantly improving the device's breakdown voltage and enhancing its reverse blocking capability. Furthermore, a field oxide layer 202 is formed on the top surface of the substrate 200, which achieves electrical isolation between devices and reduces leakage current by selectively growing an oxide layer on the surface of the substrate 200.

[0050] The power semiconductor device further includes a plurality of polysilicon field plates 203, an interlayer dielectric layer 204, a plurality of metal field plates 205, and a passivation layer 206. The plurality of polysilicon field plates 203 are spaced apart on the surface of the field oxide layer 202. The interlayer dielectric layer 204 covers the plurality of polysilicon field plates 203, the substrate 200, and the exposed surfaces of the field oxide layer 202. The plurality of metal field plates 205 are spaced apart on the surface of the interlayer dielectric layer 204 and correspond one-to-one with the plurality of polysilicon field plates 203; that is, the projection of each metal field plate 205 toward the substrate 200 lies on the corresponding polysilicon field plate 203. The passivation layer 206 covers at least a portion of the surfaces of the plurality of metal field plates 205 and the exposed surfaces of the interlayer dielectric layer 204. In order to achieve electrical lead-out, the passivation layer 206 covering the surface of the metal field plate 205 also has an opening (not shown), which exposes part of the surface of the metal field plate 205 in order to form a conductive structure in contact with the metal field plate 205.

[0051] Understandably, the polysilicon field plate 203, as the primary modulation layer for electric field modulation in the terminal region T, is responsible for fine electric field modulation in the area near the substrate 200, thus alleviating electric field concentration near the surface of the substrate 200. The metal field plate 205, as the extended modulation layer for electric field modulation in the terminal region T, is responsible for extending the electric field modulation range, dispersing the high electric field throughout the entire terminal region T, further avoiding electric field concentration, and improving the breakdown voltage and reliability of the device. The interlayer dielectric layer 204 is typically made of insulating materials such as SiO2 or Si3N4. On one hand, it serves to electrically isolate the polysilicon field plate 203 from the metal field plate 205, preventing short circuits and ensuring that each independently performs its electric field modulation function; on the other hand, it protects the substrate 200 and the polysilicon field plate 203, while also blocking external environmental erosion of the terminal region T. The passivation layer 206 is made of materials such as SiO2 and Si3N4. It can be a single film structure or a multilayer composite film structure of different materials. It is used to prevent moisture, pollutants and other substances in the external environment from entering the device and to ensure the electrical stability of the device.

[0052] Preferably, in this embodiment, the dihedral angle formed by the side surface of the polycrystalline silicon field plate 203 and the bottom surface of the polycrystalline silicon field plate 203 is an acute angle. For example... Figure 3 and Figure 4As shown, the top and bottom surfaces of the polycrystalline silicon field plate 203 are parallel to the horizontal plane. The side surface of the polycrystalline silicon field plate 203 has a certain tilt angle and forms a dihedral angle with the bottom surface of the polycrystalline silicon field plate 203, denoted as the first included angle θ1, which is an acute angle. In other words, the angle between the side surface of the polycrystalline silicon field plate 203 and the horizontal plane extending in a direction away from the side surface of the polycrystalline silicon field plate 203 is the adjacent supplementary angle θ1' of the first included angle θ1, and the adjacent supplementary angle θ1' is an obtuse angle. Preferably, the first included angle θ1 ranges from 40° to 70°.

[0053] Based on this, a portion of the interlayer dielectric layer 204 covering the side surface of the polysilicon field plate 203 protrudes beyond the other portions of the interlayer dielectric layer 204. This causes the surface of the portion of the interlayer dielectric layer 204 covering the side surface of the polysilicon field plate 203 to form a dihedral angle with a horizontal plane extending away from the corresponding surface of the interlayer dielectric layer 204, denoted as the second included angle θ2, which is an obtuse angle. In other words, the second included angle θ2 is the dihedral angle formed by the side surface of the protruding portion of the interlayer dielectric layer 204 and the remaining surfaces of the interlayer dielectric layer 204 that connect with the bottom of the side surface of the protruding portion. This forms... Figure 3 The morphology of the side slope of the protruding portion of the interlayer dielectric layer 204 shown.

[0054] like Figure 2 , Figures 5 to 7 As shown, the metal field plate 205 is formed on the interlayer dielectric layer 204. Based on the morphology of the interlayer dielectric layer 204, the dihedral angle formed by the side surface of the metal field plate 205 and the side surface of the protruding portion in the adjacent interlayer dielectric layer 204 is denoted as the third included angle θ3, and the third included angle θ3 is an obtuse angle. Based on this, as... Figure 7 As shown, the angle formed by the passivation layer 206 covering the multiple metal field plates 205 at the position corresponding to the third included angle θ3 is denoted as the fourth included angle θ4, which is also an obtuse angle. That is, the angle formed between the portion of the passivation layer 206 located on the side of the polysilicon field plate 203 and the horizontal plane extending away from the corresponding portion of the surface is an obtuse angle. It can be understood that the obtuse shape of the fourth included angle θ4 is beneficial for dispersing the stress of the passivation layer 206 and avoiding the formation of cracks due to stress concentration.

[0055] To further alleviate the stress concentration problem, such as Figure 2 , Figures 5 to 7As shown, in this embodiment, the top corner of the metal field plate 205 is chamfered, and the dihedral angle formed by the side surface and the bottom surface of the metal field plate 205 is acute. Specifically, the top corner of the metal field plate 205 includes a rounded chamfer and / or a beveled chamfer; that is, the top corner of the metal field plate 205 is not a sharp corner structure, but a beveled shape set at an angle to the horizontal plane, or a rounded corner shape. The passivation layer 206 covering it also forms a chamfered corner accordingly, to disperse stress and release stress, and to prevent tip discharge. Furthermore, the side surface of the metal field plate 205 has a certain tilt angle, and the dihedral angle formed with the bottom surface of the metal field plate 205 is denoted as the fifth included angle θ5. Preferably, the angle range of the fifth included angle θ5 includes 45° to 85°. Correspondingly, the angle formed between the side surface of the metal field plate 205 and the horizontal plane extending in a direction away from the side surface of the metal field plate 205 is an obtuse angle. Compared to a metal field plate 205 with a vertical side surface, the morphology of the metal field plate 205 provided in this embodiment can further disperse stress, effectively alleviate the stress concentration problem at the corner of the passivation layer 206, thereby avoiding crack formation and effectively isolating the device from external environmental interference. It should be noted that, compared Figure 5 and Figure 6 It can be seen that, compared to the vertical sidewalls, the inclined sidewalls in the metal field plate 205 can further increase the angle of the third included angle θ3, and simultaneously increase... Figure 7 The passivation layer 206 shown is at the angle of the fourth angle θ4 at the corner corresponding to the third angle θ3, so as to better disperse stress, prevent crack formation, and greatly improve the stability and reliability of the device.

[0056] Please see Figure 8 As described above, the metal field plate 205 and the polycrystalline silicon field plate 203 are correspondingly arranged, and the sides of both the metal field plate 205 and the polycrystalline silicon field plate 203 are inclined. Preferably, in two adjacent metal field plates 205, the inclination direction of the side of one metal field plate 205 is opposite to that of the opposite side of the polycrystalline silicon field plate 203 corresponding to the other metal field plate 205. Specifically, Figure 8Two adjacent metal field plates 205 are designated as a first side and a second side, respectively. The slope of the first side is equal to the slope of a first dashed line L1 passing through it; the slope of the second side is equal to the slope of a second dashed line L2 passing through it. The slopes of the first and second dashed lines L1 and L2 have opposite signs; that is, the first and second sides have opposite inclination directions. The polycrystalline silicon field plate 203 corresponding to the metal field plate 205 opposite to the second dashed line L2 has a third side. This third side is also opposite to the first side. The slope of the third side is equal to the slope of a third dashed line L3 passing through it. Similarly, the slope of the third dashed line L3 has opposite signs to the slope of the first dashed line L1; that is, the third side has opposite inclination directions. Based on this, the fourth included angle θ4 in the passivation layer 206 is kept as an obtuse angle to achieve stress dispersion and release, avoid the formation of cracks at the corner position of the passivation layer 206 due to stress concentration, and ensure that the passivation layer 206 can effectively block the interference of the external environment on the device interior, which is conducive to improving the stability and reliability of the device.

[0057] Optionally, the side surface of the polysilicon field plate 203 can be fabricated by adding a lateral etching process during the polysilicon etching process, so that the side surface of the polysilicon field plate 203 has a certain tilt angle. The top and bottom corners of the metal field plate 205 can be formed by multiple distributed etching processes. Furthermore, the angle of the fifth included angle θ5 can be determined based on the spacing between adjacent metal field plates 205. When the spacing between two adjacent metal field plates 205 is small, the angle of the fifth included angle θ5 should not be too small. If the side surface of the metal field plate 205 is too tilted, the bottom surfaces of adjacent metal field plates 205 will be close to each other, easily leading to electric field concentration and a decrease in breakdown voltage. Therefore, the angle of the fifth included angle θ5 can be optimally selected based on the specific spacing.

[0058] Please see Figure 9 The substrate 200 also has a cell region C. The cell region C is the core device region of the power semiconductor device, responsible for the main functions of device switching on and off. The interlayer dielectric layer 204 extends into and covers the cell region C, and a top metal layer 207 is formed on its surface. The passivation layer 206 extends and covers a portion of the surface of the top metal layer 207 located within the cell region C. Similarly, the passivation layer 206 on the top metal layer 207 also has openings to facilitate the formation of a conductive structure connected to the top metal layer 207, enabling electrical lead-out.

[0059] To prevent the passivation layer 206 within the cell region C from cracking due to stress concentration, the top corner of the top metal layer 207 in this embodiment is chamfered. The dihedral angle formed by the side surface and bottom surface of the top metal layer 207 is denoted as the sixth included angle θ6. This sixth included angle θ6 is also acute, so that the angle formed by the side surface of the top metal layer 207 and the horizontal plane extending away from the side surface of the top metal layer 207 is obtuse. Therefore, the passivation layer 206 covering the corner corresponding to the sixth included angle θ6 has the same morphology, which is beneficial for dispersing and releasing corresponding forces and preventing crack formation. Preferably, the angle range of the sixth included angle θ6 is 45° to 85°. Furthermore, the top corner of the top metal layer 207 includes a rounded chamfer and / or a beveled chamfer, so that the portion of the passivation layer 206 covering the top corner of the top metal layer 207 has the same chamfer morphology, thereby achieving stress dispersion and release, avoiding crack formation, and further improving the stability and reliability of the device.

[0060] In summary, the power semiconductor device provided in this embodiment has a chamfered top corner of the metal field plate 205 within the terminal region T, and the dihedral angle formed by the side surface and bottom surface of the metal field plate 205 is an acute angle. Based on this, the passivation layer 206 covering the multiple metal field plates 205 also has the same morphological characteristics at its position relative to the metal field plates 205. This helps to disperse the stress in the passivation layer 206, preventing crack formation due to stress concentration at the corner position, thereby effectively blocking external environmental interference to the device's internal structure and improving the device's stability and reliability. Furthermore, the polysilicon field plate 203 within the terminal region T also has an inclined side surface, so that the interlayer dielectric layer 204 formed on the polysilicon field plate 203 has the same inclined side surface at corresponding positions, thereby increasing the size of the obtuse angle at the bottom of the metal field plate 205. Correspondingly, the obtuse angle at the bottom of the passivation layer 206 corresponding to the metal field plate 205 is also increased, further realizing the release of the corresponding force, eliminating the influence of cracks, and improving device performance.

[0061] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention's technical solutions using the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention's technical solutions. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention's technical solutions, shall still fall within the protection scope of the present invention's technical solutions.

Claims

1. A power semiconductor device, characterized in that, include: Substrate, the substrate having a termination region; Multiple metal field plates are spaced apart on the terminal area; wherein the top corners of the metal field plates are chamfered, and the dihedral angle formed by the side surface and the bottom surface of the metal field plate is an acute angle. A passivation layer, wherein the passivation layer covers the plurality of metal field plates at least along the surface morphology of the plurality of metal field plates.

2. The power semiconductor device according to claim 1, characterized in that, The top corner of the metal field plate includes rounded chamfers and / or beveled chamfers.

3. The power semiconductor device according to claim 1 or 2, characterized in that, The angle range of the dihedral angle formed by the side surface of the metal field plate and the bottom surface of the metal field plate includes 45° to 85°.

4. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device also includes multiple polysilicon field plates and interlayer dielectric layers; The plurality of polycrystalline silicon field plates are spaced apart on the surface of the substrate; The interlayer dielectric layer covers the exposed surfaces of the plurality of polysilicon field plates and the substrate; The plurality of metal field plates are spaced apart on the surface of the interlayer dielectric layer, and the passivation layer covers at least a portion of the surface of the plurality of metal field plates and the exposed surface of the interlayer dielectric layer; as well as, The plurality of polycrystalline silicon field plates are arranged in a one-to-one correspondence with the plurality of metal field plates, and the projection of the metal field plate toward the substrate is located on the corresponding polycrystalline silicon field plate.

5. The power semiconductor device according to claim 4, characterized in that, The dihedral angle formed by the side surface of the polycrystalline silicon field plate and the bottom surface of the polycrystalline silicon field plate is an acute angle, such that at least a portion of the surface of the interlayer dielectric layer and a portion of the passivation layer, which are sequentially covered on the side surface of the polycrystalline silicon field plate, form an obtuse angle with a horizontal plane extending away from the corresponding portion of the surface.

6. The power semiconductor device according to claim 4 or 5, characterized in that, The angle range of the dihedral angle formed by the side surface of the polycrystalline silicon field plate and the bottom surface of the polycrystalline silicon field plate includes 40° to 70°.

7. The power semiconductor device according to claim 4 or 5, characterized in that, In two adjacent metal field plates, the side of one metal field plate has an inclination direction opposite to the opposite side of the polycrystalline silicon field plate corresponding to the other metal field plate.

8. The power semiconductor device according to claim 1, characterized in that, The substrate further comprises a cellular region; a top metal layer is formed on the top surface of the cellular region, and the passivation layer further covers a portion of the surface of the top metal layer; and, The top corner of the top metal layer is chamfered, and the dihedral angle formed by the side surface and the bottom surface of the top metal layer is acute.

9. The power semiconductor device according to claim 8, characterized in that, The top corner of the top metal layer includes rounded chamfers and / or beveled chamfers.

10. The power semiconductor device according to claim 8 or 9, characterized in that, The angle range of the dihedral angle formed by the side surface of the top metal layer and the bottom surface of the top metal layer includes 45° to 85°.

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