METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Abstract

Method for forming a semiconductor device, comprising: providing a semiconductor structure (102); forming an auxiliary layer (104) directly on a part of the semiconductor structure (102), wherein silicon and nitrogen are the main components of the auxiliary layer (104); forming a conductive material (106) on the auxiliary layer (104), wherein the conductive material (106) comprises AlSiCu, AlSi or tungsten and is electrically connected to the part of the semiconductor structure (102) via the auxiliary layer (104);and forming a first load contact over a first surface of the semiconductor structure (102) and forming a second load contact over a second surface of the semiconductor structure (102), wherein the second surface is opposite to the first surface, and the semiconductor device is a power semiconductor device configured to conduct a load current of more than 1 A, and the part of the semiconductor structure (102) directly adjacent to the auxiliary layer (104) is at least one region consisting of a source region (1082), an emitter region, a body region (1081), a body contact region (1083), a cathode region, or an anode region.

Description

TECHNICAL AREA The present disclosure relates to a method for manufacturing a transistor device, in particular to a method which includes forming an auxiliary layer on a semiconductor structure. BACKGROUND The technological development of new generations of semiconductor devices, such as insulated-gate field-effect transistors (IGFETs) like metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. Exemplary semiconductor devices are known, for instance, from US Patent 8,811,056 B2. Although costs can be reduced by shrinking device geometries, increasing device functionality per unit area presents a number of trade-offs and challenges. For example, shrinking device geometries can pose challenges in meeting electrical characteristic requirements, such as…the contact resistance or latch-up robustness, which are associated with conductive fillings in tight contact holes. There may be a desire to improve manufacturing processes for electrical contact structures in semiconductor devices. SUMMARY The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are enclosed to provide a further understanding of the embodiments and are incorporated into and form part of this description. The drawings illustrate examples of semiconductor device fabrication and, together with the description, serve to explain the principles of the examples. Further examples are set forth in the following detailed description and the claims. Fig. 1 contains schematic cross-sectional views to illustrate an example of a method for fabricating an auxiliary layer on a first surface of a semiconductor structure of a semiconductor device. Fig. 2 contains schematic cross-sectional views to explain an example of a method for fabricating an auxiliary layer that lines the sidewalls and bottom of a recess of a first surface of a semiconductor structure of a semiconductor device. Figs. 3, 4, 5, 6, 7 to 8Figure 8 shows schematic cross-sectional views of semiconductor devices that include an auxiliary layer arranged between the semiconductor structure and the conductive material. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings, which form part of the disclosure and in which specific examples of semiconductor substrate processing are shown by means of illustrations. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated with the same reference numerals in the various drawings unless otherwise stated. The terms "have," "contain," "comprise," "exhibit," and similar terms are open-ended, indicating the presence of the identified structures, elements, or features, but not excluding the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise. The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" implies that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. A resistive contact is a non-rectifying electrical junction. For physical dimensions, specified ranges include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least". The term "on" should not be interpreted as meaning only "directly on". Rather, if an element is positioned "on" or "over" another element (e.g., a layer is "on" or "over" another layer or "on" or "over" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" or "over" the substrate). An example in the present disclosure relates to a method for forming a semiconductor device. The method may include providing a semiconductor structure. Furthermore, the method may include forming an auxiliary layer directly onto a portion of the semiconductor substrate. Silicon (Si) and nitrogen (N) may be the main components of the auxiliary layer. The method may also include forming a conductive material on the auxiliary layer. The conductive material may contain AlSiCu, AlSi, tungsten, or doped polycrystalline silicon. The conductive material may be electrically connected to the portion of the semiconductor structure via the auxiliary layer. The semiconductor device can be a vertical power semiconductor device with a load current flowing between a first load terminal or contact on a first surface and a second load terminal or contact on a second main surface opposite the first. For example, the first surface can correspond to the surface where the auxiliary layer is formed. The semiconductor device can be a vertical power semiconductor IGBT (insulated-gate bipolar transistor), a reverse-conducting (RC) power semiconductor IGBT, or a vertical power semiconductor transistor such as a vertical power semiconductor IGFET (insulated-gate field-effect transistor, e.g., a metal-oxide semiconductor field-effect transistor), a vertical power diode, or a vertical power thyristor.The vertical power semiconductor device can be configured to conduct currents greater than 1 A, 10 A, or even 30 A, and can further be configured to block voltages between load terminals, such as between the emitter and collector of an IGBT or between the drain and source of a MOSFET, in the range of a few tens or hundreds up to a few thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device. In some other examples, the semiconductor device can be a lateral power semiconductor device with a load current flowing between a first load terminal or contact on the first surface and a second load terminal or contact on the first surface.The first and second load connections are spaced laterally apart. The semiconductor structure may contain or consist of a semiconductor material from the elemental semiconductors of group IV, a IV-IV compound semiconductor material, a III-V compound semiconductor material, or a II-VI compound semiconductor material. Examples of semiconductor materials from the elemental semiconductors of group IV include silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include silicon carbide (SiC) and silicon germanium (SiGe). Examples of III-V compound semiconductor materials include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of II-VI compound semiconductor materials include cadmium telluride (CdTe), mercury-cadmium telluride (CdHgTe), and cadmium-magnesium telluride (CdMgTe). The semiconductor structure can be, for example, a Czochralski or CZ structure.The semiconductor structure can be, for example, a magnetic Czochralski (MCZ) or float-zone (FZ) or epitaxially deposited silicon semiconductor structure. For instance, the semiconductor structure can comprise a semiconductor substrate, such as a semiconductor wafer or a die separated from the wafer after wafer splitting, and one or more epitaxial layers deposited thereon. For example, the one or more epitaxial layers can be positioned between the semiconductor substrate and the auxiliary layer. The conductive material can, for example, be a filler material for a contact hole. The contact hole can extend through an interlayer dielectric arranged on a first surface of the semiconductor structure. The conductive material can be shaped as a contact plug, a contact line, or a contact structure with one or more segments extending along a lateral direction, such as a direction parallel to the first main surface. The one or more segments can, for example, take the form of a strip, a ring or ring segment, or a meander. The conductive material can be formed, for example, as part of a first wiring layer above the semiconductor structure or prior to its formation. The formation of the semiconductor device can include the formation of one or more wiring layers as parts of a wiring zone above the semiconductor structure. Each wiring layer can be formed by a single or a stack of conductive layers, such as a metal layer(s). The wiring layers can be structured, for example, lithographically. An interlayer dielectric can be placed between stacked wiring layers. Contact plugs or contact leads can be formed in openings in the interlayer dielectric to electrically connect parts, such as metal leads or contact zones, of different wiring layers.For example, a first wiring layer directly adjacent to the conductive material can be a layer containing AlSiCu. Silicon (Si) and nitrogen (N) can be the main components of the auxiliary layer and are therefore the elements whose atoms form the chemical compound. For example, silicon and nitrogen are the main constituents or principal components of a silicon nitride (SiN) layer. Before the auxiliary layer is formed, the exposed portion of the semiconductor structure can be bare or terminated by hydrogen, for example, through a chemical cleaning process in a hydrogen fluoride (HF) solution. The exposed portion of the semiconductor structure can also be covered by a thin native or wet-chemically grown oxide. The auxiliary layer formation process can transform at least part of the thin oxide layer covering the exposed portion of the semiconductor structure into silicon oxynitride or silicon nitride, which forms part of the auxiliary layer. The conductive material and / or the one or more wiring levels can be formed by a layer formation process or by a combination of such processes, e.g. by chemical vapor deposition (CVD), electrochemical deposition (ECD), physical vapor deposition (PVD). The formation of the auxiliary layer offers several technical advantages. For example, in silicon-based semiconductor structures, the auxiliary layer can prevent silicon regrowth on the surface of the semiconductor structure, which can be caused by an AlSiCu material. It can also prevent silicon regrowth within narrow contact holes, thus avoiding their complete filling in some areas with a weakly conductive material. Consequently, the auxiliary layer can improve contact resistance and / or latch-up robustness in conjunction with conductive fillings in narrow contact holes. For example, the molar fraction of components other than silicon or nitrogen in the auxiliary layer is 30% or less. The molar fraction of components other than silicon or nitrogen can vary along a thickness direction. For instance, the molar fraction of oxygen in a first part of the auxiliary layer can be higher than in a second part, where the first part is located between the semiconductor structure and the second part of the auxiliary layer. This can be attributed to a transformation of a thin oxide layer covering the exposed part of the semiconductor structure into silicon oxynitride or silicon nitride, which forms part of the auxiliary structure. The thickness of the auxiliary layer can, for example, range from 0.3 nm to 2 nm or from 0.5 nm to 1.5 nm. The thickness can be chosen to be large enough to prevent silicon regrowth caused by an AlSiCu layer above or as part of a conductive material, and small enough to allow ohmic contact between the semiconductor structure and the conductive material. For example, the auxiliary layer can be formed, at least partially, by a thermal nitriding process. The thermal nitriding process can be carried out in a furnace, e.g., a rapid thermal processing furnace. An atmosphere surrounding the semiconductor structure during the thermal nitriding process can, for example, contain NH3. Other reactive nitrogen species can be used. For example, other reactive nitrogen species can be supplied via a remote plasma process or an upstream plasma process. The thermal nitriding process can, for example, involve processing the semiconductor substrate at temperatures ranging from 600°C to 1100°C or from 700°C to 1000°C. The thermal nitriding process can be performed for a period of between 15 seconds and 5 minutes before the formation of the conductive material. The thermal nitriding process can include processing the semiconductor structure in an oven, such as a rapid thermal processing oven. The auxiliary layer can, for example, be formed at least partially by means of an atomic layer deposition (ALD) process. The provision of the semiconductor structure can, for example, involve forming at least one doped region in a semiconductor substrate by introducing dopants through a surface of the semiconductor substrate. For example, the semiconductor substrate can comprise a CZ or FZ silicon wafer, which may have no, one, or more semiconductor layers on it. The surface can be a surface on the front or top side of the semiconductor substrate, such as a surface where bond wires are used to provide an electrical connection to bond pads of the semiconductor device. The at least one doped region can be formed, for example, by a masked or unmasked ion implantation process and / or a diffusion process using a gaseous or solid diffusion source.The method can further include forming an interlayer dielectric on the first surface of the semiconductor substrate. For example, the interlayer dielectric can be a first dielectric located between the semiconductor structure and a first wiring layer, such as a first metallization layer of a wiring zone above the semiconductor structure. The method can also include structuring the interlayer dielectric by forming at least one opening in the interlayer dielectric to expose the portion of the semiconductor structure. For example, the at least one opening can be a contact opening or a contact hole located between the first wiring layer and active device regions, such as doped semiconductor regions in the semiconductor structure.Structuring the interlayer dielectric can, for example, include a lithographic structuring process. The process can, for example, include exposing part of the semiconductor structure after structuring the interlayer dielectric by forming at least one depression in the semiconductor substrate on the first surface through etching of the semiconductor substrate in a region below the at least one opening in the interlayer dielectric. A mask used for structuring the interlayer dielectric can, for example, also be used to form the at least one depression in the semiconductor substrate. Etching agents can differ, for example, with respect to the at least one opening in the interlayer dielectric and the at least one depression in the semiconductor substrate. The auxiliary layer can, for example, completely line the exposed part of the semiconductor structure. The auxiliary layer can, for example, line opposite side walls of the at least one opening in the interlayer dielectric. For instance, the auxiliary layer can line an entire lateral surface of the at least one opening in the interlayer dielectric. After the auxiliary layer has formed, for example, a portion of the auxiliary layer covering an upper surface of the interlayer dielectric can be removed. The method can further include, for example, forming a first load contact or load connection over the first surface of the semiconductor structure and forming a second load contact or load connection over a second surface of the semiconductor structure, the second surface being opposite the first surface. The first surface can be a surface on the front or top side of the semiconductor structure. A wiring zone can be formed on the first surface. For example, bond pads can be formed on the first main surface. The second surface can be a surface on the back or rear side of the semiconductor structure. The semiconductor device can be mounted on a support, such as a wireframe, over the second surface.The first load contact can be an emitter contact or emitter electrode of an IGBT or bipolar transistor, or an anode or cathode contact or anode or cathode electrode, or a source electrode or source contact of an IGFET. In addition to the first load contact across the first surface of the semiconductor structure, other contacts can be formed. For example, one or more control contacts can be formed across the first surface of the semiconductor structure, such as a gate contact or gate electrode of an IGBT or IGFET, or a base contact or base electrode of a bipolar transistor. The second load contact can be a collector contact or collector electrode of an IGBT or bipolar transistor, or a cathode or anode contact or a cathode or anode electrode, or a source electrode or source contact of an IGFET.For example, the second load contact can cover an entire rear surface of the semiconductor structure. The semiconductor device can, for example, be a power semiconductor device configured to carry a load current greater than 1 A. For example, a part of the semiconductor structure directly adjacent to the auxiliary layer can be a source region, a body region, or an anode region. Structural and / or functional details described above for features such as the auxiliary layer or the conductive material apply equally to corresponding features described below in relation to the semiconductor device or the figures. Another example from the present disclosure relates to a semiconductor device. The semiconductor device may include a semiconductor structure. The semiconductor device may further include an auxiliary layer directly on a portion of the semiconductor structure. Silicon and nitrogen may be the main components of the auxiliary layer. The semiconductor device may further include a conductive material on the auxiliary layer. The conductive material may include AlSiCu, AlSi, or tungsten and is electrically connected to the portion of the semiconductor structure via the auxiliary layer. The conductive material can, for example, be a contact plug that electrically connects the semiconductor structure and a wiring layer. The wiring layer can be a metallization layer of a wiring zone. For example, the wiring layer can be located at the smallest vertical distance to the semiconductor structure with respect to all wiring layers of the wiring zone above the semiconductor structure. The wiring layer can, for example, be the first among one or more wiring layers formed above the semiconductor structure. The aspects and features mentioned and described along with one or more of the previously described examples and figures can also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally introduce the feature into the other example. The description and drawings only illustrate the principles of revelation. It is understood that the disclosure of multiple actions, processes, operations, steps, or functions in the description or claims cannot be interpreted as requiring them to occur in a specific sequence unless expressly or implicitly stated otherwise, for example, for technical reasons, such as by expressions like "thereafter." Therefore, the disclosure of multiple actions or functions does not restrict them to a particular order unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may comprise or be subdivided into multiple sub-actions, functions, processes, operations, or steps.Such partial acts may be included in and form part of the disclosure of this single act, unless this is expressly excluded. Referring to the schematic cross-sectional view above in Fig. 1, a semiconductor structure 102 is provided. The semiconductor structure 102 can comprise a semiconductor substrate, e.g., a CZ or FZ silicon wafer, which may have, for example, no, one, or more semiconductor layers on it. Referring to the schematic cross-sectional view in the center of Fig. 1, an interlayer dielectric 110 is formed on a first surface 103 of the semiconductor substrate structure. The interlayer dielectric 110 is structured by forming an opening 114, e.g., a contact hole, in the interlayer dielectric 110. This exposes part of the semiconductor structure 102. An auxiliary layer 104 is formed on the exposed part of the semiconductor structure 102. Silicon and nitrogen are the main components of the auxiliary layer 104. Furthermore, the auxiliary layer 104 can be formed on sidewalls and on a surface of the interlayer dielectric 110 (not shown in Fig. 1, see Fig. 3 and Fig. 4), e.g., if the auxiliary layer 104 is formed by thermal nitriding or by atomic layer deposition (ALD). Referring to the schematic cross-sectional view below in Fig. 1, a conductive material 106 is formed on the auxiliary layer 104. The conductive material 106 contains AlSiCu, AlSi, tungsten, or polycrystalline silicon and is electrically connected to the part of the semiconductor structure 102 via the auxiliary layer 104. The conductive material can, for example, form a contact plug or a contact line, as well as a first wiring level, e.g., a first wiring layer above the first surface 103 of the semiconductor structure 102. Referring to the schematic cross-sectional view of Fig. 2, another example of a method for fabricating a semiconductor device is illustrated. The method illustrated in Fig. 2 differs from the method illustrated in Fig. 1 by the additional formation of a recess in the semiconductor structure 102 on the first surface 103, by etching the semiconductor structure 102 in a region below the opening 114. This allows for electrical contact with the semiconductor structure 102 not only via a bottom surface of the conductive material 106, but also via a portion of a lateral surface of the conductive material 106. The auxiliary layer 104 lines opposite side walls and a bottom surface of the recessed opening 114 in the interlayer dielectric 110. Furthermore, the auxiliary layer 104 can be applied to side walls and a surface of the interlayer dielectric 110 (in Fig.2 not illustrated, see Fig. 3 and Fig. 4 ) can be formed, e.g. when the auxiliary layer 104 is formed by thermal nitriding or by atomic layer deposition, ALD. In addition to the process features illustrated in the schematic cross-sectional views of Figures 1 and 2, further processes can be performed to form the semiconductor device. Some of the additional processes can be performed before the processes illustrated in Figures 1 and 2. Some other processes can be performed after the processes illustrated in Figures 1 and 2. Still other processes can be performed together with or between the processes illustrated in Figures 1 and 2. The process features illustrated in Fig. 1 can be part of a method for fabricating a semiconductor device 120 with a planar-gate IGFET or IGBT, as illustrated in the schematic cross-sectional view of Fig. 3. The planar-gate IGFET or IGBT comprises a planar gate electrode 1151 and a planar gate dielectric 1161. The semiconductor structure 102 has a semiconductor substrate 112, which includes a body region 1081 and a body contact region 1083 with a higher doping concentration than the body region 1081. The semiconductor structure 102 further includes a source region 1082. The source region 1082 and the body contact region 1083 are directly adjacent to the auxiliary layer 104 and are electrically connected to the conductive material 106 via the auxiliary layer 104. The process features illustrated in Fig. 2 can be part of a method for fabricating a semiconductor device 120 with a planar-gate IGFET or IGBT, as illustrated in the schematic cross-sectional view of Fig. 4. The planar-gate IGFET or IGBT illustrated in Fig. 4 differs from the planar-gate IGFET and IGBT illustrated in Fig. 3 by the arrangement of an electrical contact between the auxiliary layer 104 and the semiconductor structure 102. In the example illustrated in Fig. 4, the source region 1082 is electrically connected to the conductive material 106 by a lateral surface of a depression in the semiconductor structure 102, which is lined by the auxiliary layer 104.Likewise, part of the body contact area 1083 is electrically connected to the conductive material 106 by a lateral surface of the depression in the semiconductor structure 102, which is lined by the auxiliary layer 104. The process features illustrated in Fig. 1 can also be part of a method for manufacturing a semiconductor device 120 with a trench-gate IGFET or IGBT, as illustrated in the schematic cross-sectional view of Fig. 5. The trench-gate IGFET or IGBT includes a trench-gate electrode 1152 and a trench-gate dielectric 1162. The electrical contact between the semiconductor structure 102 and the conductive material is similar to the examples described with reference to Fig. 1 and Fig. 3. The process features illustrated in Fig. 2 can also be part of a method for manufacturing a semiconductor device 120 with an IGFET or IGBT with a trench gate, as illustrated in the schematic cross-sectional view of Fig. 6. The IGFET or IGBT with a trench gate includes a trench-gate electrode 1152 and a trench-gate dielectric 1162. The electrical contact between the semiconductor structure 102 and the conductive material is similar to the examples described with reference to Fig. 2 and Fig. 4. The exemplary semiconductor devices described with reference to the illustrated examples can be vertical or lateral semiconductor devices. An example of a vertical semiconductor device 120 is illustrated in the schematic cross-sectional view of Fig. 7. The semiconductor device 120 includes a first load terminal or load contact L1 above the first surface 103 of the semiconductor structure 102. The first load terminal L1 can correspond to or be electrically connected with the conductive material 106. A second load terminal or load contact L2 is arranged above a second surface 118 of the semiconductor substrate 102. The second load terminal 118 is arranged opposite the first main surface 103. An example of a lateral semiconductor device 120 is illustrated in the schematic cross-sectional view of Fig. 8. Unlike in Fig.Figure 4 shows the second load terminal or load contact L2 of the lateral semiconductor device 120 of Fig. 8, arranged above the first surface 103 and laterally spaced from the first load terminal L1. In the vertical semiconductor device 120 of Fig. 7, the load current flows along a vertical direction between the first surface 103 and the second surface 118. In the lateral semiconductor device 120 of Fig. 8, the load current flows predominantly along a lateral direction parallel to the first surface 103.

Claims

Method for forming a semiconductor device, comprising: providing a semiconductor structure (102); forming an auxiliary layer (104) directly on a part of the semiconductor structure (102), wherein silicon and nitrogen are the main components of the auxiliary layer (104); forming a conductive material (106) on the auxiliary layer (104), wherein the conductive material (106) comprises AlSiCu, AlSi or tungsten and is electrically connected to the part of the semiconductor structure (102) via the auxiliary layer (104);and forming a first load contact over a first surface of the semiconductor structure (102) and forming a second load contact over a second surface of the semiconductor structure (102), wherein the second surface is opposite to the first surface, and the semiconductor device is a power semiconductor device configured to conduct a load current of more than 1 A, and the part of the semiconductor structure (102) directly adjacent to the auxiliary layer (104) is at least one region consisting of a source region (1082), an emitter region, a body region (1081), a body contact region (1083), a cathode region, or an anode region. Method according to claim 1, wherein the molar fraction of components other than silicon or nitrogen in the auxiliary layer (104) is 30% or less. Method according to one of the preceding claims, wherein the thickness of the auxiliary layer (104) is in a range of 0.3 nm to 2 nm. Method according to one of the preceding claims, wherein the auxiliary layer (104) is formed at least partially by means of a thermal nitriding process. Method according to claim 4, wherein an atmosphere surrounding the semiconductor structure (102) during the thermal nitriding process contains NH3. Method according to one of the two preceding claims, wherein the thermal nitriding process includes processing the semiconductor structure (102) at temperatures ranging from 600°C to 1100°C for a period of time between 15 s and 5 min prior to the formation of the conductive material (106). Method according to one of the preceding claims, wherein the auxiliary layer (104) is formed at least partially by means of an atomic layer deposition (ALD) process. A method according to any of the preceding claims, wherein providing the semiconductor structure (102) comprises: forming at least one doped region (1081, 1082, 1083) in a semiconductor substrate (112) by introducing dopants through a surface of the semiconductor substrate (112); forming an interlayer dielectric (110) on the first surface of the semiconductor substrate (112); structuring the interlayer dielectric (110) by forming at least one opening (114) in the interlayer dielectric (110) to expose the part of the semiconductor structure (102). The method according to the preceding claim, further comprising: structuring the interlayer dielectric (110), exposing part of the semiconductor structure (102) by forming at least one depression in the semiconductor substrate (112) on the first surface by etching the semiconductor substrate (112) in an area below the at least one opening (114) in the interlayer dielectric (110). Method according to one of the two preceding claims, wherein the auxiliary layer (104) completely lines the exposed part of the semiconductor structure (102). Method according to one of the three preceding claims, wherein the auxiliary layer (104) lines opposite side walls of the at least one opening (114) in the interlayer dielectric (110). Semiconductor device comprising: a semiconductor structure (102); an auxiliary layer (104) directly on a part of the semiconductor structure (102), wherein silicon and nitrogen are the main components of the auxiliary layer (104); a conductive material (106) on the auxiliary layer (104), wherein the conductive material (106) comprises AlSiCu, AlSi or tungsten and is electrically connected to the part of the semiconductor structure (102) via the auxiliary layer (104); and wherein the semiconductor device is a power semiconductor device configured to conduct a load current of more than 1 A, and the part of the semiconductor structure (102) directly adjacent to the auxiliary layer (104) is at least one region consisting of a source region (1082), an emitter region, a body region (1081), a body contact region (1083), a cathode region, or an anode region. Semiconductor device according to the preceding claim, wherein the molar fraction of components of the auxiliary layer (104) other than silicon or nitrogen is 30% or less. Semiconductor device according to one of the two preceding claims, wherein the thickness of the auxiliary layer (104) is in a range of 0.3 nm to 2 nm. Semiconductor device according to one of the three preceding claims, wherein the conductive material (106) is a contact plug that electrically connects the semiconductor structure (102) and a wiring layer.

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