Optoelectronic unit
By using amorphous silicon semiconductor materials and glass substrates or silicon layers to replace SOI substrates, the manufacturing process of optoelectronic units is simplified, costs are reduced, and light absorption capacity and response speed are improved, making them suitable for solar cells, relays, and sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WISETOP TECHNOLOGY CO LTD
- Filing Date
- 2025-04-22
- Publication Date
- 2026-07-03
AI Technical Summary
Existing optoelectronic units are expensive and have complex manufacturing processes due to the use of silicon-on-insulator (SOI) as a substrate.
Using amorphous silicon semiconductor materials as the first and second doped semiconductor layers, combined with a glass substrate or silicon layer, simplifies the manufacturing process and reduces costs.
It simplifies the manufacturing process and reduces the cost of optoelectronic units, while enhancing light absorption capacity and photoelectric response speed, making it suitable for applications such as solar cells, relays, and sensors.
Smart Images
Figure CN224460446U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to an optoelectronic unit. Background Technology
[0002] A photoelectric unit is a device that can convert light energy into electrical energy or light signals into electrical signals. It is widely used in fields such as solar cells, relays, and sensors.
[0003] The substrate used in general optoelectronic units is silicon-on-insulator (SOI). Due to the high price of SOI and the complex manufacturing process of optoelectronic units using SOI as the substrate, the cost of optoelectronic units is high.
[0004] Therefore, designing a low-cost optoelectronic unit is one of the urgent problems to be solved. Utility Model Content
[0005] This invention provides an optoelectronic unit that can replace SOI with other materials and be combined with semiconductor components made of specific materials, thereby simplifying the manufacturing process and reducing the cost of the optoelectronic unit.
[0006] This utility model provides an optoelectronic unit, including: a substrate; and a first semiconductor component disposed on the substrate, including: a first doped semiconductor layer disposed on the substrate, and the material being amorphous silicon semiconductor material; and a second doped semiconductor layer disposed on the first doped semiconductor layer, and the material being amorphous silicon semiconductor material; wherein the first doped semiconductor layer and the second doped semiconductor layer are semiconductors with different doping types.
[0007] In some embodiments, the substrate is made of glass.
[0008] In some embodiments, the substrate includes: a silicon layer; and a first metal layer sandwiched between one side of the silicon layer and a first doped semiconductor layer.
[0009] In some embodiments, the substrate further includes a silicon oxide layer, one side of which is disposed on the other side of the silicon layer;
[0010] In some embodiments, the photoelectric unit further includes a second semiconductor component disposed on the other side of the silicon oxide layer.
[0011] In some embodiments, the substrate further includes a circuit layer disposed on one side of the silicon layer.
[0012] In some embodiments, there are multiple first metal layers, each first metal layer being adjacent to each other; there are multiple first semiconductor components, each first semiconductor component being disposed on each first metal layer; the photoelectric unit further includes: multiple second metal layers, each second metal layer being disposed on a second doped semiconductor layer of each first semiconductor component, and each second metal layer being electrically connected to each adjacent first metal layer.
[0013] In some embodiments, the glass transition temperature of the substrate is higher than the manufacturing temperature of the amorphous silicon semiconductor.
[0014] In some embodiments, the manufacturing temperature is less than or equal to 400 degrees Celsius.
[0015] In some embodiments, the first semiconductor component further includes:
[0016] The intrinsic semiconductor layer is sandwiched between the first doped semiconductor layer and the second doped semiconductor layer, and the material is amorphous silicon semiconductor material.
[0017] As described above, the photoelectric unit of this invention simplifies the manufacturing process and reduces costs because both the first and second doped semiconductor layers are made of amorphous silicon semiconductor materials, making it suitable for applications in solar cells, relays, and sensors. In contrast, conventional photoelectric units use silicon-on-insulator (SOI) substrates. However, SOI is expensive, and the manufacturing process for photoelectric units using SOI substrates is complex, resulting in high costs.
[0018] Furthermore, the first semiconductor component of the photoelectric unit also has an intrinsic semiconductor layer, which can enhance light absorption and improve photoelectric response speed.
[0019] In addition, the optoelectronic unit has a circuit layer and a second semiconductor component, so it can integrate more functions than the optoelectronic unit of the third embodiment.
[0020] Furthermore, the photoelectric unit has multiple first semiconductor components, multiple first metal layers, and multiple second metal layers that are sequentially and electrically connected in series. In this way, the voltage generated when the photoelectric unit is irradiated by light can be amplified through the series connection to form a larger voltage. Attached Figure Description
[0021] Details of one or more embodiments of the subject matter described herein are set forth in the following drawings and description. Other features, aspects, and advantages of the subject matter of this specification will become apparent from the description, drawings, and claims, wherein:
[0022] Figure 1 This is a schematic diagram of the photoelectric unit of the first embodiment of the present invention.
[0023] Figure 2This is a schematic diagram of the photoelectric unit of the second embodiment of the present invention.
[0024] Figure 3 This is a schematic diagram of the photoelectric unit of the third embodiment of the present invention.
[0025] Figure 4 This is a schematic diagram of the photoelectric unit of the fourth embodiment of the present invention.
[0026] Figure 5 This is a schematic diagram of the photoelectric unit of the fifth embodiment of this utility model. Detailed Implementation
[0027] The detailed description and technical content of this utility model are explained below with reference to the accompanying drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit this utility model.
[0028] As used herein, terms such as “first” and “second” describe various components, parts, regions, layers, and / or portions, which should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Unless the context clearly indicates otherwise, the use of terms such as “first” and “second” herein does not imply order or sequence.
[0029] Figure 1 This is a schematic diagram of the photoelectric unit according to the first embodiment of this utility model. Please refer to... Figure 1 As shown, the optoelectronic unit 1 in this embodiment includes a substrate 10 and a first semiconductor component 20.
[0030] The substrate 10 may, for example, possess rigid properties to support other components. In this embodiment, the substrate 10 is made of glass G. Glass G is composed of inorganic oxides such as silicon dioxide (SiO2), and it has high light transmittance, which is beneficial for the photoelectric unit 1 to receive light. In some embodiments, the glass transition temperature of the substrate 10 is higher than the manufacturing temperature of the amorphous silicon semiconductor. When the temperature of the substrate 10 is below the glass transition temperature (Tg), the substrate 10 is rigid; when the temperature of the substrate 10 is above Tg, the substrate 10 exhibits flexible properties. When the materials of the first doped semiconductor layer 21 and the second doped semiconductor layer 22 of the first semiconductor component 20 are both amorphous silicon semiconductor materials, if the glass transition temperature of the substrate 10 is lower than the manufacturing temperature of the amorphous silicon semiconductor, fabricating the first semiconductor component 20 on the substrate 10 will cause deformation of the substrate 10. The manufacturing temperature of the amorphous silicon semiconductor material is, for example, less than or equal to 400 degrees Celsius. The glass transition temperature of the substrate 10 may, for example, be 500 degrees Celsius.
[0031] A first semiconductor component 20 is disposed on a substrate 10 and includes a first doped semiconductor layer 21 and a second doped semiconductor layer 22. The first semiconductor component 20 may, for example, be in flat contact with the substrate 10, or it may be fixed to the substrate 10 by other materials. The first semiconductor component 20 may cover part or all of the substrate 10. The first semiconductor component 20 may, for example, be a photodiode with a PN junction, formed by combining a p-type semiconductor and an n-type semiconductor. When a photon strikes the depletion layer of the first semiconductor component 20, a voltage can be generated in the first semiconductor component 20.
[0032] A first doped semiconductor layer 21 is disposed on the substrate 10, and the material is amorphous silicon semiconductor material. The first doped semiconductor layer 21 can, for example, be in flat contact with the substrate 10, or it can be fixed to the substrate 10 by other materials. The first doped semiconductor layer 21 can cover part or all of the substrate 10. In this embodiment, the first doped semiconductor layer 21 covers a portion of the substrate 10. The doping type of the first doped semiconductor layer 21 can be P-type or N-type. In this embodiment, the doping type of the first doped semiconductor layer 21 is P-type, but this is not limiting. It is worth noting that the material of the first doped semiconductor layer 21 is amorphous silicon semiconductor material. Amorphous silicon (a-Si) semiconductor materials have no long-range order in their atomic arrangement. The advantages of amorphous silicon materials are lower manufacturing costs and, in some cases, excellent light absorption characteristics.
[0033] The second doped semiconductor layer 22 is disposed above the first doped semiconductor layer 21, and is made of amorphous silicon semiconductor material. The first doped semiconductor layer 21 and the second doped semiconductor layer 22 are semiconductors with different doping types. The second doped semiconductor layer 22 can, for example, make flat contact with the first doped semiconductor layer 21. The second doped semiconductor layer 22 can cover part or all of the first doped semiconductor layer 21. In this embodiment, the second doped semiconductor layer 22 covers all of the first doped semiconductor layer 21. In this embodiment, the first doped semiconductor layer 21 is P-type and the second doped semiconductor layer 22 is N-type, but this is not limiting.
[0034] As described above, the substrate 10 of the optoelectronic unit 1 in this embodiment is made of glass G, which facilitates the passage of light through the substrate 10. The light passing through the substrate 10 can be received by the first semiconductor component 20 to form a voltage. Since the materials of the first doped semiconductor layer 21 and the second doped semiconductor layer 22 are both amorphous silicon semiconductor materials, the manufacturing process of the optoelectronic unit 1 is simplified and the cost is reduced, making it suitable for applications in fields such as solar cells, relays, and sensors. In contrast, the substrate used in general optoelectronic units is silicon-on-insulator (SOI). Due to the high cost of SOI and the complex manufacturing process of optoelectronic units using SOI as a substrate, the cost of optoelectronic units is high.
[0035] Figure 2 This is a schematic diagram of the photoelectric unit according to the second embodiment of this utility model. Please refer to... Figure 2 As shown, the photoelectric unit 1A of the second embodiment and the photoelectric unit 1 of the first embodiment (as shown) Figure 1 The difference (shown) is that the first semiconductor component 20 in the second embodiment further includes an intrinsic semiconductor layer I. The substrate 10 in the second embodiment is similar to that in the first embodiment, and will not be described again here.
[0036] The first semiconductor component 20 also includes an intrinsic semiconductor layer I, sandwiched between the first doped semiconductor layer 21 and the second doped semiconductor layer 22, and made of amorphous silicon semiconductor material. The intrinsic semiconductor layer I can, for example, make flat contact with the first doped semiconductor layer 21 and the second doped semiconductor layer 22 to form a PIN diode. The intrinsic semiconductor layer I can also be called an intrinsic semiconductor layer, referring to a semiconductor without additional doping or with low doping. PIN diodes typically have a wider depletion layer and smaller junction capacitance than ordinary diodes, which can enhance light absorption and improve photoelectric response speed.
[0037] Therefore, compared to the photoelectric unit 1 of the first embodiment (such as...) Figure 1 As shown), the first semiconductor component 20 of the photoelectric unit 1A in the second embodiment also has an intrinsic semiconductor layer I, which can further enhance light absorption and improve photoelectric response speed.
[0038] Figure 3 This is a schematic diagram of the photoelectric unit according to the third embodiment of this utility model. Please refer to... Figure 3 As shown, the photoelectric unit 1B of the third embodiment and the photoelectric unit 1 of the first embodiment (as shown) Figure 1 The difference (shown) is that the substrate 10 in the third embodiment includes a silicon layer S and a first metal layer M1. The first semiconductor component 20 in the third embodiment is similar to that in the first embodiment, and will not be described again here.
[0039] The substrate 10 includes a silicon layer S, for example, made by cutting a high-purity silicon wafer, but this is not a limitation.
[0040] The substrate 10 includes a first metal layer M1 sandwiched between one side of the silicon layer S and a first doped semiconductor layer 21. The first metal layer M1 can, for example, be in flat contact with one side of the silicon layer S, or it can be fixed to the silicon layer S by other materials; the first metal layer M1 can cover part or all of the silicon layer S. The first metal layer M1 can, for example, be deposited on the silicon layer S by a deposition process. The first metal layer M1 can, for example, be in flat contact with the first doped semiconductor layer 21, or it can be fixed to the first doped semiconductor layer 21 by other materials.
[0041] Therefore, compared to the photoelectric unit 1 of the first embodiment (such as...) Figure 1 As shown, the photoelectric unit 1B in the third embodiment can also be enhanced with different configuration methods.
[0042] Figure 4 This is a schematic diagram of the photoelectric unit according to the fourth embodiment of this utility model. Please refer to... Figure 4 As shown, the photoelectric unit 1C of the fourth embodiment and the photoelectric unit 1B of the third embodiment (as shown) Figure 3 The difference (shown) is that the first semiconductor component 20 in the fourth embodiment further includes an intrinsic semiconductor layer I, the substrate 10 further includes a silicon oxide layer SO and a circuit layer C, and the optoelectronic unit 1C further includes a second semiconductor component 30. The silicon layer S and the first metal layer M1 in the fourth embodiment are similar to those in the third embodiment, and will not be described again here.
[0043] The first semiconductor component 20 is similar to that in the second embodiment, and will not be described again here.
[0044] The substrate 10 also includes a silicon oxide layer SO, one side of which is disposed on the other side of the silicon layer S. The silicon oxide layer SO can, for example, be in flat contact with the silicon layer S. The silicon oxide layer SO can cover part or all of the silicon layer S. In this embodiment, the silicon oxide layer SO covers the entire silicon layer S. The silicon oxide layer SO is typically composed of silicon oxides such as silicon dioxide, and has the effect of electrical isolation, preventing current interference between different components.
[0045] The substrate 10 also includes a circuit layer C disposed on one side of the silicon layer S. The circuit layer C is disposed on one side of the substrate 10. For example, the substrate 10 can be used to form components such as diodes and transistors through semiconductor processes, and can also be used to form integrated circuits through semiconductor processes. In other words, the circuit layer C can be pre-disposed on the silicon layer S of the substrate 10.
[0046] The optoelectronic unit 1C also includes a second semiconductor component 30 disposed on the other side of the silicon oxide layer SO. The second semiconductor component 30 may, for example, be in flat contact with the silicon oxide layer SO, or it may be fixed to the silicon oxide layer SO by other materials. The second semiconductor component 30 may cover part or all of the silicon oxide layer SO. In this embodiment, the second semiconductor component 30 covers a portion of the silicon oxide layer SO. The second semiconductor component 30 may be the same as or different from the first semiconductor component 20. The second semiconductor component 30 may be electrically connected to or electrically isolated from the first semiconductor component 20. The first semiconductor component 20 may, for example, be a photodiode, and the second semiconductor component 30 may, for example, be a photodiode or a phototransistor.
[0047] In some embodiments, the substrate 10 may further include vias (not shown) disposed thereon and conductive material (not shown) passing through the vias. The conductive material may include, for example, tungsten, aluminum, or copper. The conductive material may be formed, for example, by filling or plating. In this way, circuits on different layers of the substrate 10 can be electrically connected via the conductive material passing through the vias, integrating the circuits on different layers of the substrate 10 into a single circuit.
[0048] Therefore, compared to the photoelectric unit 1B of the third embodiment (such as...), Figure 3 As shown), the first semiconductor component 20 of the photoelectric unit 1C in the fourth embodiment further includes an intrinsic semiconductor layer I, which can enhance light absorption and improve photoelectric response speed. The photoelectric unit 1C of the fourth embodiment has a circuit layer C and a second semiconductor component 30, and therefore can be more efficient than the photoelectric unit 1B of the third embodiment (as shown). Figure 3 (As shown) Integrates more functions.
[0049] Figure 5 This is a schematic diagram of the photoelectric unit according to the fifth embodiment of this utility model. Please refer to... Figure 5 As shown, the photoelectric unit 1D of this embodiment and the photoelectric unit 1B of the third embodiment (as shown) Figure 3 The difference (shown) is that the photoelectric unit 1D in the fifth embodiment includes a plurality of first semiconductor components 20, and each first semiconductor component 20 further includes an intrinsic semiconductor layer I. A plurality of first metal layers M1 are configured corresponding to the plurality of first semiconductor components 20. Furthermore, the photoelectric unit 1D also includes a plurality of second metal layers M2 disposed on the second doped semiconductor layer 22 of each first semiconductor component 20. The silicon layer S in the fourth embodiment is similar to that in the third embodiment and will not be described further here.
[0050] The first semiconductor component 20 is similar to that in the second embodiment, and will not be described again here.
[0051] Multiple first metal layers M1 are disposed adjacent to each other. These first metal layers M1 may be disposed adjacent to each other at equal or unequal intervals on the silicon layer S. The first metal layers M1 may, for example, contact the silicon layer S or be fixed to the silicon layer S by other materials. The first metal layers M1 may cover a portion of the silicon layer S. The first metal layers M1 may, for example, be deposited on the silicon layer S by a deposition process. Each first metal layer M1 may, for example, make planar contact with each first doped semiconductor layer 21.
[0052] Each first semiconductor component 20 is disposed on each first metal layer M1. Each first semiconductor component 20 may, for example, make flat contact with each first metal layer M1, or each first semiconductor component 20 may be fixed to each first metal layer M1 by other conductive materials. Each first semiconductor component 20 may cover part or all of each first metal layer M1. In this embodiment, each first semiconductor component 20 covers the entire first metal layer M1.
[0053] Each second metal layer M2 is disposed on the second doped semiconductor layer 22 of each first semiconductor component 20. Each second metal layer M2 may, for example, be in planar contact with each second doped semiconductor layer 22, or each second metal layer M2 may be fixed to each second doped semiconductor layer 22 by other conductive materials. Each second metal layer M2 may cover part or all of the second doped semiconductor layer 22. The second metal layer M2 may, for example, be deposited on each second doped semiconductor layer 22 by a deposition process. Each second metal layer M2 may cover part or all of the second doped semiconductor layer 22 of each first semiconductor component 20. In this embodiment, each second metal layer M2 covers the entire second doped semiconductor layer 22 of each first semiconductor component 20.
[0054] Each second metal layer M2 is electrically connected to each adjacent first metal layer M1. For example... Figure 5 The second metal layer M2 on the left and Figure 5 The first metal layer M1 on the left is electrically connected via wire W. Figure 5 The second metal layer M2 from the left and Figure 5 The first metal layer M1 on the left is electrically connected via wire W, etc.
[0055] Therefore, compared to the photoelectric unit 1B of the third embodiment (such as...), Figure 3 As shown, the first semiconductor component 20 of the photoelectric unit 1D in the fifth embodiment further includes an intrinsic semiconductor layer I, which can enhance light absorption and improve photoelectric response speed. The photoelectric unit 1D of the fifth embodiment has multiple first semiconductor components 20, multiple first metal layers M1, and multiple second metal layers M2 sequentially and electrically connected in series. Therefore, the voltage generated when the photoelectric unit 1D is irradiated by light can be accumulated due to the series connection to form a larger voltage.
[0056] In summary, the photoelectric unit of this invention simplifies the manufacturing process and reduces costs because both the first and second doped semiconductor layers are made of amorphous silicon semiconductor materials, making it suitable for applications in solar cells, relays, and sensors. In contrast, conventional photoelectric units use silicon-on-insulator (SOI) substrates, which are expensive and have complex manufacturing processes, resulting in high costs.
[0057] Furthermore, the first semiconductor component of the photoelectric unit also has an intrinsic semiconductor layer, which can enhance light absorption and improve photoelectric response speed.
[0058] In addition, the optoelectronic unit has a circuit layer and a second semiconductor component, so it can integrate more functions than the optoelectronic unit of the third embodiment.
[0059] Furthermore, the photoelectric unit has multiple first semiconductor components, multiple first metal layers, and multiple second metal layers that are sequentially and electrically connected in series. In this way, the voltage generated when the photoelectric unit is irradiated by light can be amplified through the series connection to form a larger voltage.
[0060] Unless otherwise defined, terms such as "substantially" are used to describe and narrate minor changes. When used in connection with an event or situation, the term may include the precise moment the event or situation occurred, or an approximate point in time. For example, when used in connection with a numerical value, the term may include a specific range of variation that is less than or equal to that numerical value.
[0061] The foregoing outlines components of several embodiments, enabling those skilled in the art to understand the concepts of the embodiments of this invention. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of this invention to achieve the same purpose and / or benefits as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this invention, and various changes, substitutions, and other options can be made therein without departing from the spirit and scope of this invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.
[0062] [Symbol Explanation]
[0063] 1: Photoelectric unit
[0064] 1A: Photoelectric unit
[0065] 1B: Photoelectric Unit
[0066] 1C: Photoelectric unit
[0067] 1D: Photoelectric unit
[0068] 10:Substrate
[0069] 20: First Semiconductor Component
[0070] 21: First doped semiconductor layer
[0071] 22: Second doped semiconductor layer
[0072] 30: Second semiconductor component
[0073] C: Circuit layer
[0074] G: Glass
[0075] I: Intrinsic Semiconductor Layer
[0076] M1: First metal layer
[0077] M2: Second metal layer
[0078] S: Silicon layer
[0079] SO: Silicon oxide layer
[0080] W: Conductor
Claims
1. An optoelectronic unit, characterized by include: One substrate; and A first semiconductor component is disposed on the substrate and includes: A first doped semiconductor layer is disposed on the substrate, and the material is an amorphous silicon semiconductor material; and A second doped semiconductor layer is disposed on top of the first doped semiconductor layer, and the material is the amorphous silicon semiconductor material; The first doped semiconductor layer and the second doped semiconductor layer are semiconductors with different doping types.
2. The optoelectronic unit of claim 1, wherein, The substrate is made of glass.
3. The optoelectronic unit of claim 1, wherein, The substrate includes: A silicon layer; and A first metal layer is sandwiched between one side of the silicon layer and the first doped semiconductor layer.
4. The optoelectronic unit of claim 3, wherein, The substrate further includes: A silicon oxide layer, one side of which is disposed on the other side of the silicon layer.
5. The optoelectronic unit of claim 4, wherein, Also includes: A second semiconductor component is disposed on the other side of the silicon oxide layer.
6. The photovoltaic unit of claim 3, wherein, The substrate further includes: A circuit layer is disposed on one side of the silicon layer.
7. The photoelectric unit according to claim 3, characterized in that, There are multiple first metal layers, and each first metal layer is adjacent to the other. There are multiple first semiconductor components, and each first semiconductor component is disposed on each first metal layer; The photoelectric unit further includes: A plurality of second metal layers are disposed on the second doped semiconductor layer of each of the first semiconductor components, and each second metal layer is electrically connected to each of the adjacent first metal layers.
8. The photovoltaic unit of claim 1, wherein, The first semiconductor component further includes: An intrinsic semiconductor layer is sandwiched between the first doped semiconductor layer and the second doped semiconductor layer, and the material is the amorphous silicon semiconductor material.