Test board
By designing a test carrier board that includes a first substrate, an electrical connection layer, and a second substrate, the problem of low product yield caused by excessively small test probes was solved, enabling testing suitable for high-density conductive contacts and ensuring the reliability of test results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- UNIMICRON TECH CORP
- Filing Date
- 2025-08-06
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, as the density and diameter of conductive contacts increase, the yield of finished test needles becomes low, affecting test results.
A test carrier board is designed, comprising a first substrate, an electrical connection layer, and a second substrate. Multiple second conductive contacts are connected to the first conductive contacts through the electrical connection layer. The size of the second conductive contacts is larger than that of the first conductive contacts to avoid low product yield caused by test probes that are too small.
During testing, the size of the test needles is not limited by the diameter and spacing of the conductive contacts, which improves the yield of finished products. It is applicable to conductive contact carriers formed by different technologies and ensures the accuracy of test results.
Smart Images
Figure CN224471804U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a test carrier plate. Background Technology
[0002] As advanced manufacturing technologies advance, the density of conductive contacts (such as bumps or pads) on existing substrates increases and their diameter decreases. Test needles also need to be made smaller to meet these technological trends. This limits the size of test needles, and the yield rate of finished test needles is directly proportional to the needle tip size and the minimum spacing between test needles. Utility Model Content
[0003] In view of the above, how to avoid low yield due to excessively small test probes when manufacturing test probes for testing carriers with high conductive contact density, thereby affecting the results of subsequent tests, is the problem that this utility model aims to solve. To solve this problem, this utility model provides a test carrier.
[0004] An embodiment of this utility model discloses a test substrate for testing a test substrate with multiple conductive contacts to be tested on its surface. The test substrate includes: a first substrate, multiple first conductive contacts, an electrical connection layer, a second substrate, and multiple second conductive contacts. The multiple first conductive contacts are disposed on a first surface of the first substrate, each corresponding to a multiple conductive contacts to be tested. The electrical connection layer is disposed on a second surface of the first substrate opposite to the first surface. The second substrate is disposed on the side of the electrical connection layer opposite to the first substrate. The multiple second conductive contacts are disposed on the side of the second substrate opposite to the electrical connection layer, wherein each of the multiple second conductive contacts is electrically connected to at least one of the multiple first conductive contacts through the electrical connection layer, and the size of the multiple second conductive contacts is larger than the size of the multiple first conductive contacts.
[0005] According to the test substrate disclosed in the above embodiments, the size of the test needle can be unrestricted by the diameter and spacing of the conductive contacts on the test substrate during testing. In this way, when manufacturing test needles for testing substrates with high conductive contact density, the yield of finished products can be avoided due to the test needles being too small, thus not affecting the results of subsequent tests.
[0006] The above description of the present invention and the following description of the embodiments are used to demonstrate and explain the principle of the present invention, and to provide a further explanation of the claims of the present invention. Attached Figure Description
[0007] Figure 1 This is a cross-sectional view of the test substrate and the test substrate according to an embodiment of the present invention.
[0008] Figure 2This is a cross-sectional view of a test carrier plate according to another embodiment of the present invention. Detailed Implementation
[0009] The detailed features and advantages of this utility model are described below in the embodiments. The content is sufficient for those skilled in the art to understand the technical content of this utility model and to implement it accordingly. Furthermore, based on the disclosure of this specification, the claims, and the accompanying drawings, those skilled in the art can easily understand the related objectives and advantages of this utility model. The following embodiments further illustrate the viewpoints of this utility model in detail, but are not intended to limit the scope of this utility model in any way.
[0010] Please refer to Figure 1 , Figure 1 This is a cross-sectional view of the test substrate and the substrate to be tested, according to an embodiment of the present invention. Figure 1 As shown, the test substrate 1 includes a first substrate 11, a plurality of first conductive contacts 12, an electrical connection layer 13, a second substrate 14, a plurality of second conductive contacts 15, and a set of test probes 16. The test substrate 1 is used to test a test substrate 2 on which a plurality of conductive contacts 21 to be tested are disposed on the surface. Figure 1 Test probe 16 is shown only as an example; test carrier 1 may not include test probe 16.
[0011] In this design, a plurality of first conductive contacts 12 are disposed on a first surface A1 of a first substrate 11, and each of the first conductive contacts 12 corresponds to a plurality of conductive contacts 21 to be tested. An electrical connection layer 13 is disposed on a second surface A2 of the first substrate 11 opposite to the first surface A1. A second substrate 14 is disposed on a surface A3 of the electrical connection layer 13 opposite to the first substrate 11. A plurality of second conductive contacts 15 are disposed on a surface A4 of the second substrate 14 opposite to the electrical connection layer 13. Each of the plurality of second conductive contacts 15 is electrically connected to at least one of the plurality of first conductive contacts 12 through the electrical connection layer 13, and the size of the plurality of second conductive contacts 15 may be larger than the size of the plurality of first conductive contacts 12. A test probe 16 can be regarded as a component included in the test carrier 1 or as an external component of the test carrier 1, and can be electrically connected to the plurality of second conductive contacts 15 and an external test device. The test device can use the test probe to test the carrier 1 and perform tests on the carrier 2 to be tested.
[0012] Figure 1 The relative dimensions, number, and spacing of the first conductive contact 12, the second conductive contact 15, the test probe 16, and the conductive contact 21 under test are exemplarily shown. The electrical connection structure in the electrical connection layer 13 and the substrate 2 under test, and the thickness relationship between the first substrate 11, the electrical connection layer 13, the second substrate 14, and the substrate 2 under test are also exemplarily shown. Figure 1 . Figure 1The second conductive contacts 15 are illustrated as being distributed non-equidistantly on the second substrate 14, but in other embodiments, the second conductive contacts 15 are evenly distributed on the second substrate 14, thereby achieving better test results.
[0013] In one embodiment, the size of the plurality of first conductive contacts 12 may be equal to the size of the plurality of conductive contacts 21 to be tested.
[0014] In one embodiment, the plurality of first conductive contacts 12 and the plurality of conductive contacts 21 to be tested can be symmetrical about the axis of symmetry I during testing, wherein the axis of symmetry I is located between the first substrate 11 and the carrier plate 2 to be tested.
[0015] In one embodiment, the test probe 16 may be an Electrical Test System (ETS), a Coreless Probe Card, or a Bump on line (BOL), but is not limited thereto.
[0016] Please refer to Figure 2 , Figure 2 This is a cross-sectional view of a test carrier plate according to another embodiment of the present invention. Figure 2 As shown, the test substrate 1' includes a first substrate 11, a plurality of first conductive contacts 12, an electrical connection layer 13, a second substrate 14, and a plurality of second conductive contacts 15. The connection relationship between the first substrate 11, the plurality of first conductive contacts 12, the electrical connection layer 13, the second substrate 14, and the plurality of second conductive contacts 15 is the same as in the above embodiment, and therefore will not be described again.
[0017] In this embodiment, the spacing S2 between the plurality of second conductive contacts 15 can be greater than the spacing S1 between the plurality of first conductive contacts 12.
[0018] In this embodiment, the diameter D1 of each of the plurality of first conductive contacts 12 can be from 20 micrometers to 90 micrometers, preferably from 20 micrometers to 35 micrometers.
[0019] In this embodiment, the spacing S1 between the plurality of first conductive contacts 12 can be from 20 micrometers to 150 micrometers, preferably from 20 micrometers to 45 micrometers. For example, the minimum spacing S1 between the plurality of first conductive contacts 12 corresponding to the conductive contacts 21 under test on the test substrate 2 made using Embedded Multi-die Interconnect Bridge (EMIB) technology can be from 20 micrometers to 45 micrometers, and the minimum spacing S1 between the plurality of first conductive contacts 12 corresponding to the conductive contacts 21 under test on the test substrate 2 made using Ball Grid Array (BGA) or Chip on Wafer on Substrate (CoWoS) technology can be from 110 micrometers to 150 micrometers. Additionally, Figure 1 The multiple first conductive contacts 12 of the test substrate 1 can also have the above-described dimensional design. The test conductive contacts 21 of a conventional test substrate 2 are designed with a diameter of 90 micrometers and a spacing of 100 micrometers. Through the above-described dimensional design of the first conductive contacts 12, test substrates 1 and 1' can be used with conventional test substrates 2, as well as with more precise test substrates 2. Through the bump-to-line design, test substrates 1 and 1' allow conventional testing techniques to be applied to miniature test conductive contacts 21 (e.g., 35 micrometers in diameter and 55 micrometers in spacing).
[0020] According to the test substrate of the above embodiments, the size of the test probe can be unrestricted by the diameter and spacing of the conductive contacts on the substrate under test during testing. This avoids low yield rates due to excessively small test probes when manufacturing test probes for substrates with high conductive contact density, thus ensuring the results of subsequent tests are not affected. Furthermore, the test substrate of the above embodiments also allows the test probes to be simultaneously applied to substrates with conductive contacts of various sizes and spacings formed using different technologies.
[0021] [Symbol Explanation]
[0022] 1,1': Test carrier board
[0023] 11: First substrate
[0024] 12: First conductive contact
[0025] 13: Electrical connection layer
[0026] 14: Second substrate
[0027] 15: Second conductive contact
[0028] 16: Test probe
[0029] 2: Test substrate
[0030] 21: Conductive contact to be tested
[0031] A1: First page
[0032] A2: Second page
[0033] A3, A4: Face
[0034] D1, D2: Diameter
[0035] S1, S2: Spacing.
Claims
1. A test substrate, used for a test substrate with multiple conductive contacts to be tested disposed on its surface, characterized in that, Include: First substrate; Multiple first conductive contacts are disposed on a first surface of the first substrate, wherein the multiple first conductive contacts respectively correspond to the multiple conductive contacts to be tested; An electrical connection layer is disposed on the second surface of the first substrate opposite to the first surface; The second substrate is disposed on the side of the electrical connection layer opposite to the first substrate; A plurality of second conductive contacts are disposed on one side of the second substrate opposite to the electrical connection layer, wherein each of the plurality of second conductive contacts is electrically connected to at least one of the plurality of first conductive contacts through the electrical connection layer, and the size of the plurality of second conductive contacts is larger than the size of the plurality of first conductive contacts.
2. The test carrier board according to claim 1, characterized in that, The dimensions of the plurality of first conductive contacts are equal to the dimensions of the plurality of conductive contacts to be tested.
3. The test carrier board according to claim 1, characterized in that, The plurality of first conductive contacts and the plurality of conductive contacts to be tested are symmetrical about each other with respect to an axis of symmetry during testing, wherein the axis of symmetry is located between the first substrate and the carrier plate to be tested.
4. The test carrier board according to claim 1, characterized in that, The spacing between the plurality of second conductive contacts is greater than the spacing between the plurality of first conductive contacts.
5. The test carrier board according to claim 1, characterized in that, The diameter of each of the plurality of first conductive contacts is between 20 micrometers and 90 micrometers.
6. The test carrier board according to claim 5, characterized in that, The diameter of each of the plurality of first conductive contacts is between 20 micrometers and 35 micrometers.
7. The test carrier board according to claim 1, characterized in that, The spacing between the plurality of first conductive contacts is 20 micrometers to 150 micrometers.
8. The test carrier board according to claim 7, characterized in that, The spacing between the plurality of first conductive contacts is 20 micrometers to 45 micrometers.
9. The test carrier board according to claim 1, characterized in that, The plurality of second conductive contacts are evenly distributed on the second substrate.
10. The test carrier board according to claim 1, characterized in that, It also includes a set of test probes electrically connected to the plurality of second conductive contacts, and the set of test probes are electrical test probes, coreless probe cards, or bump wiring.