memory circuit

Abstract

A memory circuit is provided. The memory circuit includes a plurality of memory cells, a precharge circuit, and a retention circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and includes one or more first transistors having a first conductivity type. The retention circuit is coupled to the bit line and includes one or more second transistors having a second conductivity type.

Description

Technical Field

[0001] This disclosure document pertains to memory circuitry. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). These improvements in integration density primarily stem from the continuous reduction in the size of the smallest feature, allowing more components to be integrated into a given area. Utility Model Content

[0003] This disclosure provides a memory circuit. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and includes one or more first transistors having a first conductivity type. The holding circuit is coupled to the bit line and includes one or more second transistors having a second conductivity type.

[0004] This disclosure provides a memory circuit. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and is used to precharge the bit line to a high logic state when none of the plurality of memory cells have been read or written. The precharge circuit includes at least one p-type transistor. The holding circuit is coupled to the bit line and is used to: hold the voltage level on the bit line substantially close to the first voltage level when at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and hold the voltage level on the bit line substantially close to the second voltage level when at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read. The holding circuit includes at least one n-type transistor.

[0005] This disclosure provides a memory circuit including a substrate, a plurality of memory cells, a precharge circuit, and a holding circuit. The substrate includes a main surface. The plurality of memory cells are formed along the main surface of the substrate and are commonly coupled to a bit line. The precharge circuit includes a first transistor formed along the main surface for precharging the bit line to a first logic state and for coupling a power supply voltage to the bit line. The holding circuit includes a second transistor formed along the main surface, wherein the first transistor and the second transistor have different doping types. The holding circuit is configured to: hold a voltage level on the bit line substantially close to a first voltage level when at least one of the plurality of memory cells storing a first logic state corresponding to a first voltage level is read; hold a voltage level on the bit line substantially close to a second voltage level when a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read; and couple a power supply voltage to the bit line. Attached Figure Description

[0006] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 A block diagram of a memory circuit according to some embodiments is shown;

[0008] Figure 2 Illustrations based on some embodiments Figure 1 A schematic diagram of a portion of the memory circuitry;

[0009] Figure 3 Illustrations based on some embodiments Figure 1 Another schematic diagram of a portion of the memory circuitry;

[0010] Figure 4 The diagram illustrates the operation according to some embodiments. Figure 3 Waveforms of various signals during memory circuit operation;

[0011] Figure 5 Illustrations based on some embodiments Figure 1 Another schematic diagram of a part of the memory circuitry;

[0012] Figure 6 Illustrations based on some embodiments Figure 1 Another schematic diagram of a part of the memory circuitry;

[0013] Figure 7 The diagram illustrates the operation according to some embodiments. Figure 6Waveforms of various signals during memory circuit operation;

[0014] Figure 8 Illustrations based on some embodiments Figure 1 Another schematic diagram of a part of the memory circuitry;

[0015] Figure 9 The diagram illustrates the operation according to some embodiments. Figure 8 Waveforms of various signals during memory circuit operation;

[0016] Figure 10 Illustrations based on some embodiments Figure 1 Another schematic diagram of a part of the memory circuitry;

[0017] Figure 11 The diagram illustrates the operation according to some embodiments. Figure 10 Waveforms of various signals during memory circuit operation;

[0018] Figure 12 A flowchart illustrating a method for forming a memory circuit according to some embodiments is shown; and

[0019] Figure 13 A flowchart illustrating the operation method of a memory circuit according to some embodiments is shown.

[0020] [Symbol Explanation]

[0021] 100: Memory System / Circuit

[0022] 105: Memory Controller

[0023] 112: Bit Line Controller

[0024] 114: Character Line Controller

[0025] 120: Memory Array

[0026] 125: Memory unit / bit unit

[0027] 130: Pre-charge circuit

[0028] 140,140[0],140[N-1]: Holding circuit

[0029] 150: Output Inverter

[0030] 152: n-type transistor

[0031] 154: p-type transistor

[0032] 210, 220: Gate-on transistors

[0033] 230, 240: Inverters

[0034] 250: Read port

[0035] 260: Transistor

[0036] 270: Gate-on transistor

[0037] 510: Common Holding Circuit

[0038] 610: Controller

[0039] 620: Delay Circuit

[0040] 630: Decoder

[0041] 640: Character Line Controller

[0042] 810: Controller

[0043] 820: Logic Gate

[0044] 830: Inverter

[0045] 840: Decoder

[0046] 850: Character Line Controller

[0047] 1010: Inverter

[0048] 1200: Method

[0049] 1210, 1220, 1230, 1240: Operations

[0050] 1300: Method

[0051] 1310, 1320: Operations

[0052] ADD: Address signal

[0053] BL, BL0, BL1, BL2, BLK: Bit lines

[0054] ICLK: Internal Clock

[0055] I kpr : Maintaining current

[0056] KPE,KPE[0],KPE[N-1]: keep signal

[0057] KPSRC: Source / Drain Terminal

[0058] n1, n2: Nodes

[0059] OUT: Output signal

[0060] PCH: Precharge signal

[0061] rBL,rBL[0],rBL[N-1]: Read bit lines

[0062] RWL: Read character lines

[0063] TRKBL: Tracking Bit Line

[0064] TRKWL: Tracking Character Lines

[0065] V DD Power supply voltage

[0066] WBL: Write Bit Line

[0067] WBLB: Complementary Write Bit Line

[0068] WL: Character Line

[0069] WL0, WL1, WL2, WLJ: Character lines

[0070] WWL: Write character line Detailed Implementation

[0071] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0072] Furthermore, for ease of description, this document uses spatially relative terms (such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar) to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein can be interpreted similarly.

[0073] Static random-access memory (SRAM) is a type of semiconductor memory typically used in computing applications requiring high-speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by the central processing unit (CPU). The cell structure and architecture of SRAM enable high-speed data access. An SRAM cell contains a bistable flip-flop structure and transistors that transfer voltage from bit lines to the flip-flop structure. A typical SRAM architecture includes one or more memory cell arrays and supporting circuitry. The memory cells in each SRAM array are arranged in rows and columns. Access to a memory cell in a row is controlled by word lines. Data is passed into (write operations) and out of (read operations) memory cells via bit lines. Each column of memory cells corresponds to at least one bit line. The supporting circuitry includes address circuitry and driver circuitry for accessing each SRAM cell via word lines and bit lines to perform various SRAM operations.

[0074] Generally, SRAM cells are coupled to hold circuits. If a bit line needs to be charged to a certain voltage level, the hold circuit helps to "hold" the bit line charged to that voltage level. For example, when reading logic 0 from an SRAM cell, the hold circuit makes the voltage level on the bit line coupled to the SRAM cell substantially close to the voltage level corresponding to logic 0; and when reading logic 1 from an SRAM cell, the hold circuit makes the voltage level on the bit line coupled to the SRAM cell substantially close to the voltage level corresponding to logic 1. In existing SRAM technology, implementing such hold circuits typically requires a large number of p-type transistors, which can undesirably cause unnecessary area overhead. Therefore, existing memory circuits with hold circuits are not entirely satisfactory in certain configurations.

[0075] This disclosure provides various embodiments of memory circuitry comprising a memory array having a plurality of memory cells, and further comprising a hold circuit and a precharge circuit coupled to each bit line of the memory array. The hold circuitry is used to hold a voltage level on the bit line during access (e.g., reading) of a corresponding memory cell, and the precharge circuitry is used to precharge the voltage level on the bit line to a high logic state. In various embodiments, the hold circuitry may include one or more first transistors having a first conductivity type, and the precharge circuitry may include one or more second transistors having a second conductivity type. By employing opposite conductivity types, the area occupied by such peripheral circuitry (e.g., the hold circuitry and the precharge circuitry) can be better utilized, thereby reducing area occupancy.

[0076] Figure 1Schematic diagrams of a memory system (or circuit) 100 according to various embodiments are shown. The memory system 100 is implemented in the form of an integrated circuit. Figure 1 As illustrated in the example, memory system 100 includes a memory controller 105 and a memory array 120. Memory array 120 may include a plurality of storage circuits, memory cells, memory bits, or bit cells 125 configured in a two-dimensional or three-dimensional array. Each memory cell 125 can be accessed via multiple access lines. For example, each memory cell 125 may be connected to at least one corresponding word line WL and a pair of corresponding bit lines BL. Each word line WL and bit line BL may contain any conductive material (e.g., metal). For example, each word line WL and bit line BL may be implemented as one or more metal lines. Memory controller 105 may write data to or read data from memory array 120 based on electrical signals transmitted through word lines WL and bit lines BL. In other embodiments, memory system 100 includes, compared to Figure 1 The document may show more, fewer, or different components, but these are still within the scope of this disclosure.

[0077] Memory array 120 is a hardware component for storing data. In various embodiments, memory array 120 is embodied as a semiconductor memory device. Memory array 120 includes a plurality of storage circuits or memory cells 125. In some embodiments, memory array 120 includes word lines WL0, WL1, ..., WLJ each extending along a first direction and bit lines BL0, BL1, ..., BLK each extending along a second direction. The word lines WL and bit lines BL may be conductive metal or conductive rails. Each memory cell 125 is connected to one or more corresponding word lines WL and one or more corresponding bit lines BL, and can operate according to the voltage or current through the corresponding word line WL and the corresponding bit line. Each memory cell 125 may be a static random access memory (SRAM) cell. For example, such as Figure 2 As shown, memory cell 125 can be implemented as an eight-transistor (8T) SRAM cell. However, it should be understood that memory cell 125 can be implemented by any of a variety of other memory configurations, but still within the scope of this disclosure. In some embodiments, memory array 120 includes additional lines (e.g., sense lines, reference lines, reference control lines, power rails, etc.).

[0078] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112 and word line controller 114, wherein the bit line controller may further include precharge circuitry 130 and holding circuitry 140. In one configuration, word line controller 114 is a circuit that provides voltage or current signals through one or more word lines WL of memory array 120. In one embodiment, bit line controller 112 is a circuit that provides voltage or current signals through one or more bit lines BL of memory array 120 and senses voltage or current from memory array 120 through one or more bit lines BL. In various embodiments, precharge circuitry 130 may utilize a precharge signal to precharge bit line BL to a high logic state (e.g., power supply voltage V) during a phase when memory array 120 is not being read or written. DD Furthermore, the holding circuit 140 can maintain the voltage level on the bit line BL at its assumed voltage level when the memory array 120 is read by supplying a holding current.

[0079] Bit line controller 112 can be connected to bit line BL of memory array 120, and word line controller 114 can be connected to word line WL of memory array 120. In one example, to write data to memory cell 125, word line controller 114 applies a voltage or current signal (sometimes referred to as a WL signal) to memory cell 125 via a corresponding word line WL connected to memory cell 125, and bit line controller 112 applies a voltage or current signal corresponding to the data to be stored to memory cell 125 via a pair of bit lines BL connected to memory cell 125. To read data from memory cell 125, word line controller 114 applies a WL signal to memory cell 125 via a corresponding word line WL connected to memory cell 125, and bit line controller 112 senses a voltage or current corresponding to the data stored by memory cell 125 via bit lines connected to memory cell 125. In some embodiments, memory controller 105 includes a voltage or current corresponding to the data stored by memory cell 125. Figure 1 The document may show more, fewer, or different components, but these are still within the scope of this disclosure.

[0080] Figure 2 Schematic diagrams of a memory cell 125 according to various embodiments are illustrated. The memory cell 125 is implemented as a dual-port SRAM cell with eight transistors. As mentioned above, the memory cell 125 is not limited to this implementation and can be implemented in any other configuration, but is still within the scope of this disclosure.

[0081] exist Figure 2In the illustrated example, memory cell 125 includes a pair of cross-coupled inverters 230 and 240, two gate transistors 210 and 220, and a read port 250. Inverters 230 and 240 are cross-coupled between nodes n1 and n2 to form a latch. Gate transistor 210 is coupled between write bit line wBL and node n1, and gate transistor 220 is coupled between complementary write bit line wBLB and node n2, wherein complementary write bit line wBLB is complementary to write bit line wBL. The gates of gate transistors 210 and 220 are coupled to the same write word line WWL. Furthermore, gate transistors 210 and 220 are n-type transistors. Read port 250 includes transistor 260 and gate transistor 270. Transistor 260 is an n-type transistor and is coupled between ground (GND) and gate transistor 270. The gate of transistor 260 is coupled to node n1. Gate transistor 270 is coupled between read bit line rBL and transistor 260. The gate of gate transistor 270 is coupled to read word line RWL.

[0082] Before accessing memory cell 125, the corresponding read bit line is precharged during precharge. When memory cell 125 is accessed, the corresponding read word line RWL is activated, and data is read by detecting the logic level at the read bit line rBL of the accessed memory cell 125. For example, when a low logic level (e.g., "0") is stored at node n1 of memory cell 125, transistor 260 of memory cell 125 is turned off (e.g., as an open circuit). Therefore, when memory cell 125 is accessed, a high logic level (e.g., "1") is detected in the read bit line rBL, i.e., a high logic level is read. Conversely, if a high logic level is stored at memory cell 125, transistor 260 of memory cell 125 is turned on, and the read bit line rBL is coupled to ground (GND) via transistor 260 and gate transistor 270 of memory cell 125. Therefore, when memory cell 125 is read, a low logic level is detected in the read bit line rBL, i.e., a low logic level is read. In this embodiment, the data in the read bit line rBL is processed to reflect the data stored in the accessed memory cell 125, i.e., the data in the read bit line rBL is complementary to the data stored in the accessed memory cell 125. In some embodiments, the data in the read bit line rBL is the same as the data stored in the accessed memory cell 125.

[0083] Refer to together Figure 1 and Figure 2The precharge circuit 130 and the hold circuit 140 can be jointly connected to the read bit line rBL. In some embodiments, the read bit line rBL is coupled to a plurality of memory cells 125, one of which is selected for reading while the others are not selected. During a read operation on the selected memory cell, the precharge circuit 130 can be deactivated while the hold circuit 140 is activated to maintain a voltage level on the read bit line rBL. For example, the hold circuit 140 can provide a hold current I. kpr Its current level is between the turn-off current I of the non-selected memory cell. cell_off The on-current I of the selected memory cell cell_on Between these, the voltage level on the read bit line rBL is kept substantially close to the assumed voltage level.

[0084] Figure 3 A schematic diagram of a portion of an example memory circuit according to various embodiments is shown. The example memory circuit includes read bit lines rBL coupled to selected memory cells and non-selected memory cells, and the precharge circuit 130 and the hold circuit 140 are implemented as transistors with different conductivity types. Figure 4 The diagram illustrates the operation according to some embodiments. Figure 3 Example waveforms of multiple signals during memory circuit operation.

[0085] like Figure 3 As shown, the pre-charge circuit 130 includes a p-type transistor, and the holding circuit 140 includes an n-type transistor. In some embodiments, the first source / drain terminal of the p-type transistor in the pre-charge circuit 130 is connected to a power supply voltage V. DD The second source / drain terminal of the p-type transistor is connected to the read bit line rBL, and the gate terminal of the p-type transistor is connected to the pre-charging (PCH) signal; while the first source / drain terminal of the n-type transistor in the holding circuit 140 is connected to the power supply voltage V. DD The second source / drain terminals of the n-type transistor are connected to the read bit line rBL, and the gate terminal of the n-type transistor is connected to the hold (KPE) signal. When reading the selected memory cell, the PCH signal can be pulled up to logic 1; when reading the selected memory cell, the KPE signal can be pulled up to logic 1. In some embodiments, the PCH signal and the KPE signal can be synchronized, i.e., pulled up / down simultaneously. Therefore, during the read operation, the precharge circuit 130 is deactivated, and at the same time, the hold circuit 140 is activated to supply the hold current I. kpr ,from Figure 4 This can be better understood from the waveform diagram.

[0086] like Figure 4As explained, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 to supply holding current I... kpr Therefore, it can be concluded that the voltage level on the read bit line rBL can be kept close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0.

[0087] In some embodiments, the read bit line rBL is coupled to the output inverter 150, which is composed of an n-type transistor 152 and a p-type transistor 154 connected in series. Specifically, the gate terminals of the n-type transistor 152 and the p-type transistor 154, which together serve as the input terminal of the inverter 150, are connected to the read bit line rBL, and the drain terminals of the n-type transistor 152 and the p-type transistor 154 together serve as the output terminal of the inverter 150. In some embodiments, the size of at least one of the n-type transistor 152 or the p-type transistor 154 may be larger than the size of any transistor forming the memory cell 125.

[0088] Figure 5 A schematic diagram of a portion of another example memory circuit according to various embodiments is illustrated. This example memory circuit includes multiple read bit lines, such as read bit lines rBL[0], ..., rBL[N-1], each read bit line coupled to a separate number of memory cells, and in a manner similar to... Figure 3 The corresponding holding circuits are implemented in a manner that allows for the following: For example, read bit line rBL[0] is coupled to holding circuit 140[0]; read bit line rBL[N-1] is coupled to holding circuit 140[N-1]; and so on. Each holding circuit 140[0] to 140[N-1] may contain an n-type transistor whose gate terminal is connected to a separate control signal KPE. Depending on the memory cell connected to the corresponding read bit line rBL, holding circuits 140[0] to 140[N-1] may be selectively activated. Furthermore, Figure 5 The memory circuit may further include a common holding circuit 510 coupled to different holding circuits 140[0] to 140[N-1]. In some embodiments, the common holding circuit 510 may include a power supply voltage V DDAn n-type transistor is coupled to one of the source / drain terminals of each holding circuit 140[0] to 140[N-1]. Furthermore, the gate terminal of the common holding circuit 510 can be connected to the power supply voltage V. DD Binding.

[0089] Figure 6 A schematic diagram of a portion of another example memory circuit according to various embodiments is shown, which includes a precharge circuit 130 and a hold circuit 140 connected to the read bit line rBL. Figure 7 The diagram illustrates the operation according to various embodiments. Figure 6 Example waveforms of multiple signals during memory circuit operation.

[0090] like Figure 6 As shown, in addition to the pre-charge circuit 130 and the holding circuit 140, the controller 610, the delay circuit 620, the decoder 630, and the character line controller 640 are also coupled to the pre-charge circuit 130 and the holding circuit 140. Such components can be... Figure 1 This is part of the memory controller 105 shown. In some embodiments, controller 610 may provide an address (ADD) signal to word line controller 640 to specify the selected memory cell 125. The ADD signal may be provided to word line controller 640 via decoder 630. Furthermore, the ADD signal may be provided to precharge circuit 130 and hold circuit 140 as PCH signal and KPE signal, respectively. In some embodiments, the KPE signal may be delayed after the PCH signal via delay circuit 620.

[0091] like Figure 7 As explained, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal, for example, with a slight delay. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 by pulling up the KPE signal, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0. Furthermore, since the KPE signal is delayed after the PCH signal, it can be ensured that the signal transition on the read bit line rBL is not too fast (compared to the undelayed KPE signal (shown as a dashed line)).

[0092] Figure 8A schematic diagram of a portion of another example memory circuit according to various embodiments is shown, which includes a precharge circuit 130 and a hold circuit 140 connected to the read bit line rBL. Figure 9 The diagram illustrates the operation according to various embodiments. Figure 8 Example waveforms of multiple signals during memory circuit operation.

[0093] like Figure 8 As shown, in addition to the precharge circuit 130 and the holding circuit 140, the controller 810, logic gate 820, inverter 830, decoder 840, word line controller 850, and several tracking units (with corresponding tracking bit lines and tracking word lines) are also coupled to the precharge circuit 130 and the holding circuit 140. The tracking units are generally used to simulate the behavior of the memory cell 125, and the tracking bit line (TRKBL) is used to simulate the RC behavior of the read bit line rBL. Such components can be... Figure 1 This is a portion of the memory controller 105 shown. In some embodiments, controller 810 may provide an address (ADD) signal to word line controller 850 to specify the selected memory cell 125. The ADD signal may be provided to word line controller 850 via decoder 840. Simultaneously with providing the ADD signal, controller 810 may provide an internal clock (ICLK) signal to initiate a tracking unit via the tracking word line. Based on the discharge state on the tracking bit line, a KPE signal may be provided to holding circuit 140, and precharge circuit 130 may receive the PCH signal based on the ICLK signal. In some embodiments, the KPE signal may be delayed after the signal on the tracking bit line.

[0094] like Figure 9As explained, when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal, for example, with a slight delay. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 by pulling up the KPE signal, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0. Furthermore, since the KPE signal is delayed after the voltage on the tracking bit line (TRKBL), it can be ensured that any propagation delay on the read bit line rBL can be tracked by the tracking bit line (TRKBL). Furthermore, the signal transitions on the read bit line rBL do not change too quickly.

[0095] Figure 10 A schematic diagram of a portion of another example memory circuit according to various embodiments is shown. This example memory circuit includes read bit lines rBL coupled to selected memory cells and non-selected memory cells, and the precharge circuit 130 and the hold circuit 140 are implemented as transistors with different conductivity types. Figure 11 The diagram illustrates the operation according to various embodiments. Figure 10 Example waveforms of multiple signals during memory circuit operation.

[0096] like Figure 10 As shown, the pre-charge circuit 130 includes a p-type transistor, and the holding circuit 140 includes an n-type transistor. In some embodiments, the first source / drain terminal of the p-type transistor in the pre-charge circuit 130 is connected to a power supply voltage V. DD The second source / drain terminal of the p-type transistor is connected to the read bit line rBL, and the gate terminal of the p-type transistor is connected to the pre-charging (PCH) signal. The first source / drain terminal (KPSRC) of the n-type transistor in the holding circuit 140 is coupled to the read bit line rBL via inverters 150 and 1010, the second source / drain terminal of the n-type transistor is connected to the read bit line rBL, and the gate terminal of the n-type transistor is connected to the keep (KPE) signal. In some embodiments, the PCH and KPE signals can be synchronized, i.e., simultaneously pulled up / down. Therefore, during a read operation, the pre-charging circuit 130 is deactivated, while the holding circuit 140 is activated to supply the holding current I. kprBecause the source / drain terminals (KPSRC) are coupled to the read bit line rBL, the holding current I provided by the holding circuit 140 is... kpr It can be adjusted according to the logical state of the selected memory unit.

[0097] like Figure 11 As explained, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 to supply holding current I... kpr Therefore, it can be concluded that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or logic 0. Furthermore, when reading logic 0 from the memory cell, the voltage at the source / drain terminals (KPSRC) of the holding circuit 140 can be pulled low (e.g., from the dashed line), thereby reducing the holding current I. kpr Therefore, the voltage level on the read bit line rBL can be kept at a low level.

[0098] Figure 12 A flowchart illustrating an example method 1200 for forming a memory circuit according to various embodiments is provided. For example, at least some operations (or steps) in method 1200 can be used to form the memory circuit described above. It should be noted that method 1200 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 12 Additional operations may be available before, during, and / or after Method 1200, and some other operations may be briefly described here.

[0099] Method 1200 begins with operation 1210. In operation 1210, a plurality of memory cells are formed along the main surface of the substrate. In some embodiments, each memory cell may be formed with a separate number of transistors, for example, a 6T SRAM cell, an 8T SRAM cell, etc. The operation of forming such transistors along the main surface is generally referred to as part of a front-end-of-line (FEOL) network or process.

[0100] The substrate can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., using p-type or n-type dopants) or undoped. The substrate can be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate may comprise: silicon; germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors comprising SiGe, GaAsP, AllnAs, AlGaAs, GainAs, GainP, and / or GainAsP; or combinations thereof.

[0101] Method 1200 continues to operation 1220. In operation 1220, a plurality of metallization layers are formed above the main surface, wherein at least one metallization layer contains bit lines commonly coupled to memory cells formed along the main surface. The operation of forming such metallization layers above the main surface is generally referred to as part of a back-end-of-line (BEOL) network or process.

[0102] Method 1200 continues to operation 1230. In operation 1230, a pre-charge circuit is formed along the main surface of the substrate, wherein the pre-charge circuit includes a p-type transistor. In some embodiments, the pre-charge circuit is used to pre-charge the bit line to a high logic state. For example, the p-type transistor of the pre-charge circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail, which is used to provide a power supply voltage (e.g., power supply voltage V). DD ) and bit lines. In some embodiments, the p-type transistor of the pre-charge circuit may have a gate terminal for receiving the pre-charge (PCH) signal.

[0103] Method 1200 continues to operation 1240. In operation 1240, a holding circuit is formed along the main surface of the substrate, wherein the holding circuit includes an n-type transistor. In some embodiments, when at least one of the memory cells storing a high logic state corresponding to a first voltage level is read, the holding circuit is used to maintain a voltage level on the bit line substantially close to the first voltage level; and when at least one memory cell storing a low logic state corresponding to a second voltage level is read, the holding circuit is used to maintain a voltage level on the bit line substantially close to the second voltage level. For example, the n-type transistor of the holding circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage (e.g., power supply voltage V). DD ) and bit lines. In some embodiments, the n-type transistor of the holding circuit may have a gate terminal for receiving the hold (KPE) signal.

[0104] Figure 13 A flowchart illustrating an example method 1300 for operating a memory circuit according to various embodiments is provided. It should be noted that method 1300 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 13 Additional operations may be available before, during, and / or after Method 1300, and some other operations may be briefly described here.

[0105] Method 1300 begins with operation 1310. In operation 1310, bit lines coupled to a plurality of memory cells are pre-charged to a first logic state. In some embodiments, a pre-charge circuit of the memory circuitry (e.g., pre-charge circuit 130) may pre-charge the bit lines to a high logic state, which corresponds to a power supply voltage (e.g., power supply voltage V). DD The pre-charge circuit may include a p-type transistor formed along the main surface of the substrate. For example, the p-type transistor of the pre-charge circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage and a bit line, respectively. In some embodiments, the p-type transistor of the pre-charge circuit may have a gate terminal for receiving a pre-charge (PCH) signal.

[0106] Method 1300 continues to operation 1320. In operation 1320, when at least a first of the memory cells storing a first logic state corresponding to a first voltage level is read, the voltage level on the holding bit line is substantially close to the first voltage level; and when a second of the memory cells storing a second logic state corresponding to a second voltage level is read, the voltage level on the holding bit line is substantially close to the second voltage level. In some embodiments, a holding circuit (e.g., holding circuit 140) of the memory circuit can hold the voltage level on the bit line. The holding circuit may include an n-type transistor formed along a major surface of a substrate. For example, the n-type transistor of the holding circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage (e.g., power supply voltage V). DD ) and bit lines. In some embodiments, the n-type transistor of the holding circuit may have a gate terminal for receiving the hold (KPE) signal.

[0107] In one embodiment of this disclosure, a memory circuit is provided. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and includes one or more first transistors having a first conductivity type. The holding circuit is coupled to the bit line and includes one or more second transistors having a second conductivity type.

[0108] In some embodiments of this type of memory circuit, a precharge circuit is used to precharge bit lines to a high logic state when multiple memory cells have not been read or written.

[0109] In some embodiments of this type of memory circuit, the holding circuit is used to: hold the voltage level on the bit line substantially close to the first voltage level when at least one of a plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and hold the voltage level on the bit line substantially close to the second voltage level when at least another of a plurality of memory cells storing a low logic state corresponding to a second voltage level is read.

[0110] In some embodiments of this type of memory circuit, the one or more first transistors of the precharge circuit include p-type transistors that couple power supply voltage to bit lines; and the one or more second transistors of the holding circuit include n-type transistors that couple power supply voltage to bit lines.

[0111] In some embodiments of this type of memory circuit, the gate terminal of the p-type transistor in the precharge circuit is connected to the precharge signal, and the gate terminal of the n-type transistor in the holding circuit is connected to the holding signal.

[0112] In some embodiments of this type of memory circuit, the hold signal and the precharge signal are synchronized with each other.

[0113] In some embodiments of this type of memory circuit, the hold signal is delayed after the precharge signal.

[0114] In some embodiments of this type of memory circuit, the memory circuit further includes an inverter. The inverter is coupled to a bit line and includes a third transistor and a fourth transistor connected in series. The size of the third transistor or the fourth transistor is larger than the size of any one of the one or more second transistors.

[0115] In some embodiments of this type of memory circuit, the memory circuit further includes multiple tracking units. These multiple tracking units are connected to a tracking bit line and are used to simulate multiple memory cells. A hold signal is delayed after the signal on the tracking bit line.

[0116] In some embodiments of this type of memory circuit, the drain terminal of the n-type transistor of the holding circuit is connected to the signal on the bit line.

[0117] In another embodiment of this disclosure, a memory circuit is provided. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and is used to precharge the bit line to a high logic state when none of the plurality of memory cells have been read or written. The precharge circuit includes at least one p-type transistor. The holding circuit is coupled to the bit line and is used to: hold the voltage level on the bit line substantially close to the first voltage level when at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and hold the voltage level on the bit line substantially close to the second voltage level when at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read. The holding circuit includes at least one n-type transistor.

[0118] In some embodiments of this other isomorphic memory circuit, the at least one p-type transistor is used to couple the power supply voltage to the bit line, and the at least one n-type transistor is used to couple the power supply voltage to the bit line.

[0119] In some embodiments of this alternative memory circuit, the gate terminal of the at least one p-type transistor in the precharge circuit is connected to a precharge signal, and the gate terminal of the at least one n-type transistor in the holding circuit is connected to a holding signal.

[0120] In some embodiments of this alternative memory circuit, the hold signal and the precharge signal are synchronized with each other.

[0121] In some embodiments of this alternative memory circuit, the hold signal is delayed after the precharge signal.

[0122] In some embodiments of this alternative memory circuit, the memory circuit further includes multiple tracking units. These multiple tracking units are connected to a tracking bit line and are used to simulate multiple memory cells. A hold signal is delayed after the signal on the tracking bit line.

[0123] In some embodiments of this alternative memory circuit, the drain terminal of the at least one n-type transistor of the holding circuit is connected to the signal on the bit line.

[0124] In another embodiment of this disclosure, an operating method is provided for a memory circuit. The operating method includes the following steps: pre-charging bit lines coupled to a plurality of memory cells to a first logic state via a pre-charging circuit; when at least one of the plurality of memory cells storing the first logic state corresponding to a first voltage level is read, holding the voltage level on the bit lines at a level substantially close to the first voltage level via a holding circuit; and when a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read, holding the voltage level on the bit lines at a level substantially close to the second voltage level via a holding circuit.

[0125] In some embodiments of this same operating method, a plurality of memory cells are formed along the main surface of the substrate, a pre-charge circuit includes a p-type transistor formed along the main surface, and a holding circuit includes an n-type transistor formed along the main surface.

[0126] In some embodiments of this same operating method, a pre-charge circuit is used to couple the power supply voltage to the bit line, and a holding circuit is used to couple the power supply voltage to the bit line.

[0127] In another embodiment of this disclosure, a memory circuit is provided. The memory circuit includes a substrate, a plurality of memory cells, a precharge circuit, and a holding circuit. The substrate includes a main surface. The plurality of memory cells are formed along the main surface of the substrate and are commonly coupled to a bit line. The precharge circuit includes a first transistor formed along the main surface for precharging the bit line to a first logic state and for coupling a power supply voltage to the bit line. The holding circuit includes a second transistor formed along the main surface, wherein the first transistor and the second transistor have different doping types. The holding circuit is used to: hold a voltage level on the bit line substantially close to a first voltage level when at least one of the plurality of memory cells storing a first logic state corresponding to a first voltage level is read; hold a voltage level on the bit line substantially close to a second voltage level when a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read; and couple a power supply voltage to the bit line.

[0128] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies from, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0129] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A memory circuit, characterized in that, Include: Multiple memory cells are coupled to a single bit line; A pre-charge circuit coupled to the bit line and comprising one or more first transistors having a first conductivity type; as well as A holding circuit, coupled to the bit line and comprising one or more second transistors having a second conductivity type.

2. The memory circuit as described in claim 1, characterized in that, The precharge circuit is used to precharge the bit line to a high logic state when none of the multiple memory cells have been read or written.

3. The memory circuit as described in claim 1, characterized in that, The holding circuit is used to: When at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read, a voltage level on the bit line is maintained substantially close to the first voltage level. as well as When at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read, the voltage level on the bit line is maintained substantially close to the second voltage level.

4. The memory circuit as described in claim 1, characterized in that, The one or more first transistors in the pre-charge circuit include a p-type transistor that couples a power supply voltage to the bit line; and The one or more second transistors in the holding circuit include an n-type transistor that couples the power supply voltage to the bit line.

5. The memory circuit as described in claim 4, characterized in that, In the pre-charge circuit, a gate terminal of the p-type transistor is connected to a pre-charge signal, and in the holding circuit, a gate terminal of the n-type transistor is connected to a holding signal.

6. The memory circuit as described in claim 1, characterized in that, Further includes: An inverter coupled to the bit line and comprising a third transistor and a fourth transistor connected in series; The third transistor or the fourth transistor has a size that is larger than the size of any one of the one or more second transistors.

7. The memory circuit as described in claim 5, characterized in that, Further includes: Multiple tracking units are connected to a single tracking bit line, and these multiple tracking units are used to simulate the multiple memory units; The hold signal is delayed after a signal on the tracking bit line.

8. The memory circuit as described in claim 4, characterized in that, In this holding circuit, one drain terminal of the n-type transistor is connected to a signal on the bit line.

9. A memory circuit, characterized in that, Include: Multiple memory cells are coupled to a single bit line; A precharge circuit is coupled to the bit line and is used to precharge the bit line to a high logic state when none of the plurality of memory cells are read or written, wherein the precharge circuit includes at least one p-type transistor. as well as A holding circuit, coupled to the bit line, is used to: When at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read, a voltage level on the bit line is maintained substantially close to the first voltage level. as well as When at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read, the voltage level on the bit line is maintained substantially close to the second voltage level. The holding circuit contains at least one n-type transistor.

10. A memory circuit, characterized in that, Include: A substrate, comprising a main surface; Multiple memory cells are formed along the main surface of the substrate and are coupled together to a bit line; A pre-charge circuit includes a first transistor formed along the main surface for pre-charging the bit line to a first logic state and for coupling a power supply voltage to the bit line. as well as A holding circuit includes a second transistor formed along the main surface, wherein the first transistor and the second transistor have different doping types, wherein the holding circuit is used to: When at least one of the plurality of memory cells storing the first logic state corresponding to a first voltage level is read, a voltage level on the bit line is maintained substantially close to the first voltage level. When a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read, the voltage level on the bit line is maintained substantially close to the second voltage level; and Couple the power supply voltage to this bit line.

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