An adaptive operating point bus voltage bleed circuit for an inverter

Abstract

The utility model discloses a kind of for inverter's self-adapting working condition bus voltage discharge circuit, including auxiliary source circuit, DC-DC boost circuit, high-voltage DC bus discharge circuit and DC-AC inverter circuit;The input end of auxiliary source circuit and DC-DC boost circuit is connected with power input end BAT, and the output end is connected with the input end of high-voltage DC bus discharge circuit;The output end of DC-DC boost circuit is also connected with the input end of DC-AC inverter circuit;DC-AC inverter circuit output end is connected with external load end;The utility model is switched by controlling MOS tube self-adaptation, cement resistance R5 is not accessed when power on, avoid energy consumption, promote efficiency;After power off, cement resistance R5 is automatically accessed, bus voltage is rapidly discharged to ≤60V to meet safety regulations, without complex control, efficiency and safety are considered.

Description

Technical Field

[0001] This utility model relates to the field of inverter design and safety control technology, specifically to an adaptive operating condition bus voltage discharge circuit for inverters. Background Technology

[0002] Currently, most inverters on the market adopt a conventional topology of battery boost and bus inversion, with their bus voltage typically maintained between 400V and 500V. According to industry safety regulations, the bus voltage must drop to 60V or below within 5 minutes of the inverter being powered off to avoid the risk of electric shock and ensure safe operation.

[0003] To meet this safety standard, inverters on the market generally achieve voltage discharge by connecting a large resistor in series in the bus discharge circuit. This means that the large resistor consumes the energy of the bus, reducing the voltage to a safe range. However, this method has a significant drawback: because the large resistor is connected in series in the bus discharge circuit both when the inverter is powered on and off, it continues to consume energy during normal operation, thus reducing the overall discharge efficiency of the unit. Summary of the Invention

[0004] To solve the above-mentioned technical problems, this utility model provides an adaptive operating condition bus voltage discharge circuit for inverters.

[0005] This utility model is achieved through the following technical solution:

[0006] An adaptive operating condition bus voltage bleed circuit for an inverter includes an auxiliary power supply circuit, a DC-DC boost circuit, a high-voltage DC bus bleed circuit, and a DC-AC inverter circuit.

[0007] The input terminals of both the auxiliary power supply circuit and the DC-DC boost circuit are connected to the power input terminal BAT, and the output terminals are both connected to the input terminal of the high-voltage DC bus discharge circuit. The output terminal of the DC-DC boost circuit is also connected to the input terminal of the DC-AC inverter circuit. The output terminal of the DC-AC inverter circuit is connected to the external load terminal.

[0008] The auxiliary power supply circuit includes an N-channel enhancement-mode MOSFET Q12, a flyback transformer T2, a diode D3, a capacitor C2, and a resistor R6;

[0009] The source of the N-channel enhancement-type MOSFET Q12 is connected to pin 2 of the flyback transformer T2, and the drain is connected to the negative terminal of the power input BAT. Pin 1 of the flyback transformer T2 is connected to the positive terminal of the power input BAT, pin 4 is connected to the anode of the diode D3, and pin 3 is grounded. The cathode of the diode D3 is connected to one end of the parallel connection of capacitor C2 and resistor R6, and the other end of the parallel connection of capacitor C2 and resistor R6 is connected to pin 3 of the flyback transformer T2 and then grounded.

[0010] The DC-DC boost circuit includes N-channel enhancement-mode MOSFETs Q3, Q4, Q5, and Q6, a main power transformer T1, and a rectifier bridge UR1.

[0011] The drains of N-channel enhancement-mode MOSFETs Q3 and Q4 are connected to the positive terminal of the power input BAT. The source of N-channel enhancement-mode MOSFET Q3 and the drain of N-channel enhancement-mode MOSFET Q5 are connected to pin 1 of the main power transformer T1. The source of N-channel enhancement-mode MOSFET Q4 and the drain of N-channel enhancement-mode MOSFET Q6 are connected to pin 2 of the main power transformer T1. The source of N-channel enhancement-mode MOSFETs Q5 and Q6 are connected to the negative terminal of the power input BAT. Pin 4 of the main power transformer T1 is connected to pin 2 of the rectifier bridge UR1, and pin 3 is connected to pin 3 of the rectifier bridge UR1.

[0012] The DC-AC inverter circuit includes N-channel enhancement-mode MOSFETs Q7, Q8, Q9, and Q10, and a common-mode filter inductor L1.

[0013] The drains of N-channel enhancement-mode MOSFETs Q7 and Q8 are both connected to one end of capacitor C1. The source of N-channel enhancement-mode MOSFETs Q7 and Q9 are both connected to pin 1 of common-mode filter inductor L1. The source of N-channel enhancement-mode MOSFETs Q8 and Q10 are both connected to pin 2 of common-mode filter inductor L1. The source of N-channel enhancement-mode MOSFETs Q9 and Q10 are connected to ground after being connected to each other.

[0014] Pin 2 of the common-mode filter inductor L1 has an "INV_L" terminal, and the common terminal of the common-mode filter inductor L1 has an "INV_N" terminal. The "INV_L" terminal and the "INV_N" terminal together constitute the output terminal of the DC-AC inverter circuit, which is used to output the inverter signal processed by the N-channel enhancement-mode MOSFETs Q7, Q8, Q9, Q10 and the common-mode filter inductor L1, and is connected to an external load.

[0015] The high-voltage DC bus discharge circuit includes capacitor C1, resistors R1, R2, R3, R4, R5, N-channel enhancement-mode MOSFET Q1, N-channel enhancement-mode MOSFET Q2, diode D1, and Zener diode D2.

[0016] One end of resistor R1 is connected to one end of capacitor C1, pin 4 of rectifier bridge UR1, and one end of resistor R5. The other end of resistor R1 is connected to one end of resistor R2, the gate of N-channel enhancement-mode MOSFET Q1, the cathode of Zener diode D2, and the source of N-channel enhancement-mode MOSFET Q2. The other end of resistor R5 is connected to the drain of N-channel enhancement-mode MOSFET Q1. The cathode of diode D1 is connected to one end of resistor R4 and the gate of N-channel enhancement-mode MOSFET Q2 through resistor R3. The anode is connected to the cathode of diode D3 and one end of the parallel connection of capacitor C2 and R6. The other end of resistor R2 is connected to the other end of resistor R4 and the drain of N-channel enhancement-mode MOSFET Q2 and then grounded. The source of N-channel enhancement-mode MOSFET Q1 is connected to the anode of Zener diode D2 and then grounded. The other end of capacitor C1 is connected to pin 1 of rectifier bridge UR1 and then grounded.

[0017] The rectifier bridge UR1 includes diodes D4, D5, D6, and D7;

[0018] The anode of diode D4 is connected to the anode of diode D5, and one pin is led out from this connection point; the cathode of diode D6 is connected to the cathode of diode D7, and four pins are led out from this connection point; the cathode of diode D4 is connected to the anode of diode D7, and two pins are led out from this connection point; the cathode of diode D5 is connected to the anode of diode D6, and three pins are led out from this connection point.

[0019] Resistors R1, R2, R3, R4, and R6 are all ceramic chip resistors, while resistor R5 is a cement resistor.

[0020] The beneficial effects achieved by this utility model through the high-voltage DC bus discharge circuit are as follows:

[0021] 1) When powered on normally, the cement resistor R5 is not connected to the bus circuit to avoid unnecessary energy consumption and improve circuit operating efficiency;

[0022] 2) After power is turned off, the cement resistor R5 is automatically connected to quickly discharge the energy of the busbar and ensure that the busbar voltage drops to ≤60V within 5 minutes to meet the safety requirements;

[0023] 3) By utilizing the adaptive switching of the MOSFET's conduction state according to the operating conditions, no additional complex control is required, and a simple safety discharge function that adapts to the operating conditions is achieved, balancing efficiency and safety. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the present invention;

[0025] Figure 2 This is a schematic diagram of the auxiliary power source circuit of this utility model;

[0026] Figure 3 This is a schematic diagram of the DC-DC boost circuit and DC-AC inverter circuit of this utility model;

[0027] Figure 4 This invention relates to a high-voltage DC bus discharge circuit. Detailed Implementation

[0028] The technical solution of this utility model is further described below with reference to the accompanying drawings and embodiments, but the scope of protection is not limited to the description:

[0029] like Figure 1 The diagram shown is a schematic of the present invention, which is an adaptive operating condition bus voltage discharge circuit for an inverter, including an auxiliary power supply circuit, a DC-DC boost circuit, a high voltage DC bus discharge circuit and a DC-AC inverter circuit.

[0030] The input terminals of both the auxiliary power supply circuit and the DC-DC boost circuit are connected to the power input terminal BAT, and the output terminals are both connected to the input terminal of the high-voltage DC bus discharge circuit. The output terminal of the DC-DC boost circuit is also connected to the input terminal of the DC-AC inverter circuit. The output terminal of the DC-AC inverter circuit is connected to the external load terminal.

[0031] like Figure 2 The diagram shown is a schematic of the auxiliary power supply circuit of this utility model; the auxiliary power supply circuit includes an N-channel enhancement-mode MOSFET Q12, a flyback transformer T2, a diode D3, a capacitor C2, and a resistor R6;

[0032] Specifically, the source of the N-channel enhancement-type MOSFET Q12 is connected to pin 2 of the flyback transformer T2, and the drain is connected to the negative terminal of the power input BAT. Pin 1 of the flyback transformer T2 is connected to the positive terminal of the power input BAT, pin 4 is connected to the anode of the diode D3, and pin 3 is grounded. The cathode of the diode D3 is connected to one end of the parallel connection of capacitor C2 and resistor R6, and the other end of the parallel connection of capacitor C2 and resistor R6 is connected to pin 3 of the flyback transformer T2 and then grounded.

[0033] The working principle and technical effect of the auxiliary power supply circuit: The N-channel enhancement-type MOSFET Q12 controls the flyback transformer T2 for energy transfer and transformation. The secondary side induced voltage of the flyback transformer T2 is rectified by diode D3 and filtered by capacitor C2. Then, it provides a stable +12V auxiliary voltage to the high-voltage DC bus discharge circuit through the branch where resistor R6 is located, realizing the conversion from BAT+ input to auxiliary voltage output.

[0034] like Figure 3The diagram shows the schematic of the DC-DC boost circuit and DC-AC inverter circuit of this utility model; the DC-DC boost circuit includes N-channel enhancement-mode MOSFET Q3, N-channel enhancement-mode MOSFET Q4, N-channel enhancement-mode MOSFET Q5, N-channel enhancement-mode MOSFET Q6, main power transformer T1, and rectifier bridge UR1;

[0035] Specifically, the drains of N-channel enhancement-mode MOSFETs Q3 and Q4 are connected to the positive terminal of the power input BAT; the source of N-channel enhancement-mode MOSFET Q3 and the drain of N-channel enhancement-mode MOSFET Q5 are connected to pin 1 of the main power transformer T1; the source of N-channel enhancement-mode MOSFET Q4 and the drain of N-channel enhancement-mode MOSFET Q6 are connected to pin 2 of the main power transformer T1; and the source of N-channel enhancement-mode MOSFETs Q5 and Q6 are connected to the negative terminal of the power input BAT. Pin 4 of the main power transformer T1 is connected to pin 2 of the rectifier bridge UR1, and pin 3 is connected to pin 3 of the rectifier bridge UR1.

[0036] The DC-AC inverter circuit includes N-channel enhancement-mode MOSFETs Q7, Q8, Q9, and Q10, and a common-mode filter inductor L1.

[0037] Specifically, the drains of N-channel enhancement-mode MOSFET Q7 and Q8 are both connected to one end of capacitor C1; the source of N-channel enhancement-mode MOSFET Q7 and the drain of N-channel enhancement-mode MOSFET Q9 are both connected to pin 1 of common-mode filter inductor L1; the source of N-channel enhancement-mode MOSFET Q8 and the drain of N-channel enhancement-mode MOSFET Q10 are both connected to pin 2 of common-mode filter inductor L1; and the source of N-channel enhancement-mode MOSFET Q9 and the source of N-channel enhancement-mode MOSFET Q10 are connected to ground.

[0038] Specifically, pin 2 of the common-mode filter inductor L1 has an "INV_L" terminal, and the common terminal of the common-mode filter inductor L1 has an "INV_N" terminal. The "INV_L" terminal and the "INV_N" terminal together constitute the output terminal of the DC-AC inverter circuit, which is used to output the inverter signal processed by the N-channel enhancement-mode MOSFETs Q7, Q8, Q9, Q10 and the common-mode filter inductor L1, and is connected to an external load.

[0039] The rectifier bridge UR1 includes diodes D4, D5, D6, and D7;

[0040] Specifically, the anode of diode D4 is connected to the anode of diode D5, and one pin is led out from this connection point; the cathode of diode D6 is connected to the cathode of diode D7, and four pins are led out from this connection point; the cathode of diode D4 is connected to the anode of diode D7, and two pins are led out from this connection point; the cathode of diode D5 is connected to the anode of diode D6, and three pins are led out from this connection point.

[0041] like Figure 4 The diagram shows the high-voltage DC bus discharge circuit of this utility model; the high-voltage DC bus discharge circuit includes capacitor C1, resistors R1, R2, R3, R4, R5, N-channel enhancement-mode MOSFET Q1, N-channel enhancement-mode MOSFET Q2, diode D1, and Zener diode D2;

[0042] Specifically, one end of resistor R1 is connected to one end of capacitor C1, pin 4 of rectifier bridge UR1, and one end of resistor R5. The other end of resistor R1 is connected to one end of resistor R2, the gate of N-channel enhancement-mode MOSFET Q1, the cathode of Zener diode D2, and the source of N-channel enhancement-mode MOSFET Q2. The other end of resistor R5 is connected to the drain of N-channel enhancement-mode MOSFET Q1. The cathode of diode D1 is connected to one end of resistor R4 and the gate of N-channel enhancement-mode MOSFET Q2 through resistor R3. The anode is connected to the cathode of diode D3 and one end of the parallel connection of capacitor C2 and R6. The other end of resistor R2 is connected to the other end of resistor R4 and the drain of N-channel enhancement-mode MOSFET Q2 and then grounded. The source of N-channel enhancement-mode MOSFET Q1 is connected to the anode of Zener diode D2 and then grounded. The other end of capacitor C1 is connected to pin 1 of rectifier bridge UR1 and then grounded.

[0043] Preferably, resistors R1, R2, R3, R4 and R6 are all ceramic chip resistors. Ceramic chip resistors achieve precise voltage division, current limiting and signal matching with small size and high precision.

[0044] Preferably, resistor R5 is a cement resistor, which, with its high power carrying capacity and high temperature resistance, achieves energy dissipation and overcurrent buffering.

[0045] Preferably, the selection of cement resistor R5 can be determined based on the bus discharge formula.

[0046] The known parameters are as follows:

[0047] The original bus voltage V0 is the voltage BUS value after being boosted by the DC-DC boost circuit. In this embodiment, V0 = 450V.

[0048] Target voltage Vtarget: In this embodiment, Vtarget = 60V;

[0049] Total capacitance of the bus capacitor C1: In this embodiment, C1 = 4080μF;

[0050] Discharge time t: In this embodiment, t = 5 min;

[0051] Calculation formula:

[0052] In the formula: R5 is the cement resistance value to be determined; C1 is the total capacitance of the busbar, a known parameter; t is the discharge time; Vgarget is the target voltage value; V0 is the original voltage value of the busbar.

[0053] Using the above formula, combined with the known original bus voltage value V0, total bus capacitance value C1, discharge time t, and target voltage value Vgarget parameters, the resistance value of cement resistor R5 under suitable operating conditions can be calculated. This enables safe discharge of bus voltage when the machine is powered off, meeting the safety requirement of dropping to ≤60V within 5 minutes, while avoiding energy loss when powered on.

[0054] The working process and technical effects of this utility model:

[0055] When the machine is powered on normally, the BAT+ voltage is connected, the auxiliary power circuit starts, and the +12V_aux auxiliary power output voltage is generated. The DC-DC boost circuit operates, boosting the low-voltage BAT+ voltage to the high-voltage BUS+ voltage; the DC-AC inverter circuit then inverts the high-voltage BUS+ voltage into AC voltage INV_L / INV_N, ensuring normal power supply and energy conversion for the machine.

[0056] When the machine is powered on normally, the bus bleed circuit does not operate. The +12V_aux auxiliary power supply, after passing through diode D1, is divided by resistors R3 and R4, causing MOSFET Q2 to close. At this time, the drain-source (DS) pin of Q2 is conducting, and the source (S) pin of Q2 is grounded, pulling the gate (GND) pin of Q1 to ground, causing MOSFET Q1 to turn off. The discharge resistor R5 is not connected to the bus + to ground (GND) loop to avoid unnecessary energy consumption of the bus during normal operation, ensuring efficient circuit operation.

[0057] After the machine is powered off, the bus discharge circuit is activated. The +12V_aux auxiliary power supply is de-energized, Q2 MOSFET is cut off, and its drain-source (DS) is disconnected. At this time, the source (S) pin of Q2 and the gate (G) pin of Q1 are both connected to the pins of BUS+ after voltage division by resistors R1 and R2. By properly setting the resistance values ​​of R1 and R2, voltage division is achieved, allowing MOSFET Q1 to conduct. Discharge resistor R5 is connected to the BUS+ circuit to ground (GND). Through this resistor, BUS+ quickly discharges energy, ensuring a safe voltage drop in the bus after shutdown.

[0058] By adaptively controlling the conduction state of the MOSFET, the bleeder resistor is connected to the bus circuit only when the power is off. This avoids energy loss during normal operation and efficiently bleeds the bus voltage after power-off, meeting the safety requirement that the bus voltage be below 60V within 5 minutes. This achieves a working condition-adaptive bus voltage safe bleed function, balancing circuit efficiency and safety standards.

Claims

1. An adaptive operating condition bus voltage discharge circuit for an inverter, characterized in that... This includes auxiliary power supply circuits, DC-DC boost circuits, high-voltage DC bus bleed circuits, and DC-AC inverter circuits. The input terminals of both the auxiliary power supply circuit and the DC-DC boost circuit are connected to the power input terminal BAT, and the output terminals are both connected to the input terminal of the high-voltage DC bus discharge circuit. The output terminal of the DC-DC boost circuit is also connected to the input terminal of the DC-AC inverter circuit. The output terminal of the DC-AC inverter circuit is connected to the external load terminal.

2. The adaptive operating condition bus voltage discharge circuit for an inverter according to claim 1, characterized in that: The auxiliary power supply circuit includes an N-channel enhancement-mode MOSFET Q12, a flyback transformer T2, a diode D3, a capacitor C2, and a resistor R6; The source of the N-channel enhancement-type MOSFET Q12 is connected to pin 2 of the flyback transformer T2, and the drain is connected to the negative terminal of the power input BAT. Pin 1 of the flyback transformer T2 is connected to the positive terminal of the power input BAT, pin 4 is connected to the anode of the diode D3, and pin 3 is grounded. The cathode of the diode D3 is connected to one end of the parallel connection of capacitor C2 and resistor R6, and the other end of the parallel connection of capacitor C2 and resistor R6 is connected to pin 3 of the flyback transformer T2 and then grounded.

3. The adaptive operating condition bus voltage discharge circuit for an inverter according to claim 1, characterized in that: The DC-DC boost circuit includes N-channel enhancement-mode MOSFETs Q3, Q4, Q5, and Q6, a main power transformer T1, and a rectifier bridge UR1. The drains of N-channel enhancement-mode MOSFETs Q3 and Q4 are connected to the positive terminal of the power input BAT. The source of N-channel enhancement-mode MOSFET Q3 and the drain of N-channel enhancement-mode MOSFET Q5 are connected to pin 1 of the main power transformer T1. The source of N-channel enhancement-mode MOSFET Q4 and the drain of N-channel enhancement-mode MOSFET Q6 are connected to pin 2 of the main power transformer T1. The source of N-channel enhancement-mode MOSFETs Q5 and Q6 are connected to the negative terminal of the power input BAT. Pin 4 of the main power transformer T1 is connected to pin 2 of the rectifier bridge UR1, and pin 3 is connected to pin 3 of the rectifier bridge UR1.

4. The adaptive operating condition bus voltage discharge circuit for an inverter according to claim 1, characterized in that: The DC-AC inverter circuit includes N-channel enhancement-mode MOSFETs Q7, Q8, Q9, and Q10, and a common-mode filter inductor L1. The drains of N-channel enhancement-mode MOSFETs Q7 and Q8 are both connected to one end of capacitor C1. The source of N-channel enhancement-mode MOSFETs Q7 and Q9 are both connected to pin 1 of common-mode filter inductor L1. The source of N-channel enhancement-mode MOSFETs Q8 and Q10 are both connected to pin 2 of common-mode filter inductor L1. The source of N-channel enhancement-mode MOSFETs Q9 and Q10 are connected to ground after being connected to each other. Pin 2 of the common-mode filter inductor L1 has an "INV_L" terminal, and the common terminal of the common-mode filter inductor L1 has an "INV_N" terminal. The "INV_L" terminal and the "INV_N" terminal together constitute the output terminal of the DC-AC inverter circuit, which is used to output the inverter signal processed by the N-channel enhancement-mode MOSFETs Q7, Q8, Q9, Q10 and the common-mode filter inductor L1, and is connected to an external load.

5. The adaptive operating condition bus voltage discharge circuit for an inverter according to claim 1, characterized in that: The high-voltage DC bus discharge circuit includes capacitor C1, resistors R1, R2, R3, R4, R5, N-channel enhancement-mode MOSFET Q1, N-channel enhancement-mode MOSFET Q2, diode D1, and Zener diode D2. One end of resistor R1 is connected to one end of capacitor C1, pin 4 of rectifier bridge UR1, and one end of resistor R5. The other end of resistor R1 is connected to one end of resistor R2, the gate of N-channel enhancement-mode MOSFET Q1, the cathode of Zener diode D2, and the source of N-channel enhancement-mode MOSFET Q2. The other end of resistor R5 is connected to the drain of N-channel enhancement-mode MOSFET Q1. The cathode of diode D1 is connected to one end of resistor R4 and the gate of N-channel enhancement-mode MOSFET Q2 through resistor R3. The anode is connected to the cathode of diode D3 and one end of the parallel connection of capacitor C2 and R6. The other end of resistor R2 is connected to the other end of resistor R4 and the drain of N-channel enhancement-mode MOSFET Q2 and then grounded. The source of N-channel enhancement-mode MOSFET Q1 is connected to the anode of Zener diode D2 and then grounded. The other end of capacitor C1 is connected to pin 1 of rectifier bridge UR1 and then grounded.

6. An adaptive operating condition bus voltage discharge circuit for an inverter according to any one of claims 3 to 4, characterized in that: The rectifier bridge UR1 includes diodes D4, D5, D6, and D7; The anode of diode D4 is connected to the anode of diode D5, and one pin is led out from this connection point; the cathode of diode D6 is connected to the cathode of diode D7, and four pins are led out from this connection point; the cathode of diode D4 is connected to the anode of diode D7, and two pins are led out from this connection point; the cathode of diode D5 is connected to the anode of diode D6, and three pins are led out from this connection point.

7. An adaptive operating condition bus voltage discharge circuit for an inverter according to claim 2 or 5, characterized in that: Resistors R1, R2, R3, R4, and R6 are all ceramic chip resistors, while resistor R5 is a cement resistor.

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