Multimodal signal recording device
By combining an FPGA with an ARM processor, a multimodal signal recording device was constructed, which solved the problem of insufficient multimodal data processing capabilities in existing technologies, realized the recording of multimodal data, and adapted to different application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HENGYANG NORTH OPTICAL-ELECTRICAL INFORMATION TECH CO LTD
- Filing Date
- 2025-08-29
- Publication Date
- 2026-07-10
AI Technical Summary
Existing missile-borne data recording devices can only record data in a single mode, which cannot adapt to multiple usage scenarios and has insufficient multimodal data processing capabilities.
The system adopts an architecture combining FPGA and ARM processor. The video recording channel is formed by CML transceiver chip, FPGA and storage module, and the analog-to-digital recording channel is formed by signal conditioning module, ARM processor and storage module, so as to realize the recording of multimodal data.
It improves multimodal data processing capabilities, enabling it to adapt to different usage scenarios and record multimodal data.
Smart Images
Figure CN224481713U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal processing technology, and in particular to a multimodal signal recording device. Background Technology
[0002] Onboard data recorders are crucial for acquiring missile status data during ignition, flight, and impact. Currently, existing onboard data recording devices have a single data recording channel, allowing them to record only single-modal data. This results in insufficient multi-modal data processing capabilities to adapt to different usage scenarios. Utility Model Content
[0003] The main purpose of this application is to provide a multimodal signal recording device, which aims to solve the technical problem that the existing technology has insufficient multimodal data processing capabilities and cannot adapt to different application scenarios.
[0004] To achieve the above objectives, this application proposes a multimodal signal recording device, which includes: a data receiving module, an FPGA, an ARM processor, and a storage module;
[0005] The data receiving module includes: a CML transceiver chip for receiving video signals and a signal conditioning module for receiving analog-to-digital signals;
[0006] The FPGA is connected to the CML transceiver chip and the storage module respectively, and the data transmission path formed by the CML transceiver chip, the FPGA and the storage module constitutes a video recording channel;
[0007] The ARM processor is connected to the signal conditioning module and the storage module respectively, and the data transmission path formed by the signal conditioning module, the ARM processor and the storage module constitutes an analog-to-digital recording channel.
[0008] In one embodiment, the signal conditioning module includes: a first operational amplifier chip for receiving high-speed analog signals, a second operational amplifier chip for receiving low-speed analog signals, a first AD acquisition chip, and a second AD acquisition chip;
[0009] The first AD acquisition chip is connected to the first operational amplifier chip and the FPGA respectively;
[0010] The second AD acquisition chip is connected to the second operational amplifier chip and the ARM processor, respectively.
[0011] In one embodiment, the CML transceiver chip is model TLK2711;
[0012] Both the first operational amplifier chip and the second operational amplifier chip are model OPA4277.
[0013] In one embodiment, the signal conditioning module further includes: an RS422 isolated transceiver chip for receiving RS422 signals, a protocol conversion chip, and a CAN isolated transceiver chip for receiving CAN signals;
[0014] The protocol conversion chip is connected to the RS422 isolated transceiver chip and the ARM processor, respectively.
[0015] The CAN isolation transceiver chip is connected to the ARM processor.
[0016] In one embodiment, the RS422 isolated transceiver chip is model ADM2582;
[0017] The CAN isolation transceiver chip is model ADM3053;
[0018] The first AD acquisition chip is model ADS8661;
[0019] The second AD acquisition chip is model ADS8688;
[0020] The protocol conversion chip 66 is model CH438.
[0021] In one embodiment, the storage module includes: a DDR3 cache and an eMMC array;
[0022] Both the DDR3 cache and the eMMC array are connected to the FPGA.
[0023] The data transmission path formed by the CML transceiver chip, the FPGA, the DDR3, and the eMMC array constitutes the video recording channel.
[0024] In one embodiment, the FPGA internally includes a FIFO buffer;
[0025] The data transmission path formed by the first operational amplifier chip, the first AD acquisition chip, the FPGA buffer, the FIFO, and the eMMC array constitutes a high-speed analog data recording channel.
[0026] In one embodiment, the storage module further includes an eMMC single chip;
[0027] The ARM processor internally includes: RAM cache;
[0028] The eMMC single chip is connected to the ARM processor;
[0029] The data transmission path formed by the second operational amplifier chip, the second AD acquisition chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes a low-speed analog data recording channel;
[0030] The data transmission path formed by the RS422 isolation transceiver chip, the protocol conversion chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes the RS422 data recording channel.
[0031] The data transmission path formed by the CAN isolation transceiver chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes the CAN data recording channel.
[0032] In one embodiment, the multimodal signal recording device further includes: a data export module;
[0033] The data export module includes: a network interface and an RS485 isolation chip;
[0034] The network interface is connected to the FPGA and the ARM processor, respectively;
[0035] The RS485 isolation chip is connected to both the FPGA and the ARM processor.
[0036] In one embodiment, the network interface includes: a first network PHY, a second network PHY, and a network switch;
[0037] The network switch is connected to the first network PHY and the second network PHY respectively;
[0038] The first network PHY is connected to the FPGA, and the second network PHY is connected to the ARM processor.
[0039] One or more technical solutions proposed in this application have at least the following technical effects:
[0040] The multimodal signal recording device provided in this application includes a data receiving module, an FPGA, an ARM processor, and a storage module. The data receiving module includes a CML transceiver chip for receiving video signals and a signal conditioning module for receiving analog-to-digital signals. The FPGA is connected to both the CML transceiver chip and the storage module; the ARM processor is connected to both the signal conditioning module and the storage module. This multimodal signal recording device adopts an architecture combining an FPGA and an ARM processor. The CML transceiver chip, the FPGA, and the storage module form a video recording channel, while the signal conditioning module, the ARM processor, and the storage module form an analog-to-digital recording channel. This achieves multimodal data recording, effectively improves multimodal data processing capabilities, and can adapt to different application scenarios. Attached Figure Description
[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a schematic diagram of the structure of the first embodiment of the multimodal signal recording device of this application;
[0044] Figure 2 This is a schematic diagram of the structure of the second embodiment of the multimodal signal recording device of this application.
[0045] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0046] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.
[0047] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0048] The main solution of this application embodiment is as follows: the provided multimodal signal recording device includes a data receiving module, an FPGA, an ARM processor, and a storage module; the data receiving module includes a CML transceiver chip for receiving video signals and a signal conditioning module for receiving analog-to-digital signals. The FPGA is connected to both the CML transceiver chip and the storage module; the ARM processor is connected to both the signal conditioning module and the storage module.
[0049] Existing technologies lack the capability to process multimodal data and cannot adapt to different application scenarios.
[0050] This application provides a solution in which a multimodal signal recording device adopts an architecture combining FPGA and ARM processor. The video recording channel is formed by CML transceiver chip, FPGA and storage module, and the analog-to-digital recording channel is formed by signal conditioning module, ARM processor and storage module. This realizes the recording of multimodal data, effectively improves the multimodal data processing capability and can adapt to different application scenarios.
[0051] Based on this, embodiments of this application provide a multimodal signal recording device, referring to... Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the multimodal signal recording device of this application.
[0052] In this embodiment, the multimodal signal recording device includes: a data receiving module 10, a field-programmable gate array (FPGA) 20, an advanced RISC machine (ARM) processor 30, and a storage module 40.
[0053] The data receiving module 10 includes: a current-mode logic (CML) transceiver chip 50 for receiving video signals and a signal conditioning module 60 for receiving analog-to-digital signals.
[0054] The FPGA 20 is connected to the CML transceiver chip 50 and the storage module 40 respectively. The data transmission path formed by the CML transceiver chip 50, the FPGA 20 and the storage module 40 constitutes a video recording channel.
[0055] The ARM processor 30 is connected to the signal conditioning module 60 and the storage module 40 respectively, and the data transmission path formed by the signal conditioning module 60, the ARM processor 30 and the storage module 40 constitutes an analog-to-digital recording channel.
[0056] The CML transceiver chip 50 is model TLK2711.
[0057] It should be noted that the data receiving module 10 mentioned above can be a module for receiving signals or data.
[0058] Understandably, the aforementioned FPGA 10 is a programmable hardware device containing numerous logic units, programmable interconnects, and other functional modules, capable of processing video signals and high-speed analog signals. These high-speed analog signals can be analog signals with frequencies reaching a set value, such as 100kHz.
[0059] It should be noted that the aforementioned ARM processor 30 may be a microprocessor based on a reduced instruction set, which can be used to process low-speed analog signals and digital signals. The low-speed analog signals may be analog signals with a frequency lower than a set frequency, such as 1kHz.
[0060] Understandably, the aforementioned storage module 40 can be used to store data or signals processed by the FPGA 20 and the ARM processor 30.
[0061] It should be noted that the aforementioned analog-to-digital signals may include the aforementioned low-speed analog signals and digital signals.
[0062] In the specific implementation, the data transmission path formed by the CML transceiver chip 50, FPGA 20 and storage module 40 constitutes the video recording channel, and the data transmission path formed by the signal conditioning module 60, ARM processor 30 and storage module 50 constitutes the analog-to-digital recording channel.
[0063] In the video recording channel, FPGA 20 is the main controller. The video signal is deserialized by CML transceiver chip 50, converted into a parallel signal, and then output to FPGA 20 for data decoding. The decoded video signal is then output to storage module 40 for storage.
[0064] In the analog-to-digital recording channel, the ARM processor 30 is the main controller. The analog-to-digital signal is processed by the signal conditioning module 60 and then output to the ARM 30 for further processing. The processed signal is then output to the storage module 40 for storage.
[0065] The multimodal signal recording device provided in this embodiment includes a data receiving module, an FPGA, an ARM processor, and a storage module. The data receiving module includes a CML transceiver chip for receiving video signals and a signal conditioning module for receiving analog-to-digital signals. The FPGA is connected to both the CML transceiver chip and the storage module; the ARM processor is connected to both the signal conditioning module and the storage module. This multimodal signal recording device adopts an architecture combining an FPGA and an ARM processor. The CML transceiver chip, the FPGA, and the storage module form a video recording channel, while the signal conditioning module, the ARM processor, and the storage module form an analog-to-digital recording channel. This enables the recording of multimodal data, effectively improving multimodal data processing capabilities and adapting to different application scenarios.
[0066] Based on the first embodiment of this application, a second embodiment of this application is proposed. In the second embodiment, content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the multimodal signal recording device of this application.
[0067] In this embodiment, the signal conditioning module 60 includes: a first operational amplifier chip 61 that receives high-speed analog signals, a second operational amplifier chip 62 that receives low-speed analog signals, a first AD acquisition chip 63, and a second AD acquisition chip 64.
[0068] The first AD acquisition chip 63 is connected to the first operational amplifier chip 61 and the FPGA 20 respectively.
[0069] The second AD acquisition chip 64 is connected to the second operational amplifier chip 62 and the ARM processor 30 respectively.
[0070] The first operational amplifier chip 61 and the second operational amplifier chip 62 are both of model OPA4277.
[0071] The first AD acquisition chip 63 is model ADS8661.
[0072] The second AD acquisition chip 64 is model ADS8688.
[0073] It should be noted that the first operational amplifier chip 61 mentioned above can be a chip that receives high-speed analog signals and processes them.
[0074] Accordingly, the second operational amplifier chip 62 can be a chip that receives low-speed analog signals and processes them.
[0075] It is understandable that the first AD acquisition chip 63 mentioned above can be a chip that converts the signal output by the first operational amplifier chip 61 into a digital signal.
[0076] Accordingly, the second AD acquisition chip 64 can be a chip that converts the signal output by the second operational amplifier chip 62 into a digital signal.
[0077] In a specific implementation, the first operational amplifier chip 61 can receive high-speed analog signals and condition them. Conditioning includes amplification, filtering, and rectification of the signals. The conditioned signal is then output to the first AD acquisition chip 63. The first AD acquisition chip 63 converts the conditioned signal output by the first operational amplifier chip 61 into a digital signal and outputs it to the FPGA 20. The FPGA 20 processes the digital signal output by the first AD acquisition chip 63 and outputs it to the storage module 40 for storage.
[0078] The second operational amplifier chip 62 can receive low-speed analog signals and condition them. Conditioning includes signal amplification, filtering, and rectification. The conditioned signal is then output to the second AD acquisition chip 64. The second AD acquisition chip 64 converts the conditioned signal output by the second operational amplifier chip 62 into a digital signal and outputs it to the ARM processor 30. The ARM processor 30 processes the digital signal output by the second AD acquisition chip 64 and outputs it to the storage module 40 for storage.
[0079] In this embodiment, the signal conditioning module 60 further includes: an RS422 isolated transceiver chip 65 for receiving RS422 signals, a protocol conversion chip 66, and a CAN isolated transceiver chip 67 for receiving Controller Area Network (CAN) signals.
[0080] The protocol conversion chip 66 is connected to the RS422 isolated transceiver chip 65 and the ARM processor 30, respectively.
[0081] The CAN isolation transceiver chip 67 is connected to the ARM processor 30.
[0082] The RS422 isolated transceiver chip 65 is model ADM2582.
[0083] The CAN isolation transceiver chip 67 is model ADM3053.
[0084] The protocol conversion chip 66 is model CH438.
[0085] It should be noted that the RS422 isolation transceiver chip 65 mentioned above can be a chip with isolation function and used to receive RS422 signals.
[0086] Understandably, the aforementioned protocol conversion chip 66 can be a chip that converts the protocol of a signal.
[0087] It should be noted that the aforementioned CAN isolation transceiver chip 67 can be a chip with isolation function that is used to receive CAN signals.
[0088] In its implementation, the RS422 isolation transceiver chip 65, upon receiving an RS422 signal, converts the signal level to a Transistor-Transistor Logic (TTL) level and then outputs the processed signal to the protocol conversion chip 66. The RS422 signal uses the Serial Peripheral Interface (SPI) protocol. The protocol conversion chip 66 converts the received signal to the Universal Asynchronous Receiver / Transmitter (UART) protocol and outputs it to the ARM processor 30 for processing. The ARM processor 30 processes the signal from the protocol conversion chip 66 and then outputs it to the storage module 40 for storage.
[0089] After receiving a CAN signal, the aforementioned CAN isolation transceiver chip 67 can convert the CAN signal level to a TTL level and then output the processed signal to the ARM processor 30 for processing. The ARM processor 30 processes the signal from the protocol conversion chip 66 and then outputs it to the storage module 40 for storage.
[0090] It should be understood that the above-mentioned multimodal signal recording device uses different devices to process signals of different modes, realizing different recording strategies for different signals and effectively improving the versatility of data recording.
[0091] Based on the first and second embodiments of this application, a third embodiment of this application is proposed. In this third embodiment, content that is the same as or similar to the first and second embodiments described above can be referred to the above description and will not be repeated hereafter. Please continue to refer to... Figure 2 .
[0092] In this embodiment, the storage module 40 includes: a Double Data Rate 3 (DDR3) cache 41 and an embedded Multi-Media Card (eMMC) array 42.
[0093] Both the DDR3 cache 41 and the eMMC array 42 are connected to the FPGA 20.
[0094] The data transmission path formed by the CML transceiver chip 50, the FPGA 20, the DDR3 cache 41, and the eMMC array 42 constitutes the video recording channel.
[0095] It should be noted that the aforementioned DDR3 cache 41 can be used to temporarily store data written by FPGA 20.
[0096] Understandably, the eMMC array 42 consists of multiple eMMC single chips 45 used to store data output from the FPGA 20. Multiple eMMC single chips 45 in the eMMC array 42 can perform read and write operations simultaneously, significantly improving data read and write speed and enhancing system performance. The eMMC single chips are used to store data output from the ARM memory 30.
[0097] In the specific implementation, the data transmission path formed by the CML transceiver chip 50, FPGA 20, DDR3 cache 41 and eMMC array 42 constitutes the video recording channel. In the video recording channel, the video signal is processed by the CML transceiver chip 50 and FPGA 20, and then written by FPGA 20 to DDR3 cache 41 for caching. After the cached data reaches the set data amount, it is quickly written to eMMC array 42 in HS200 mode.
[0098] In this embodiment, the FPGA 20 internally includes a First-In-First-Out (FIFO) buffer 43.
[0099] The data transmission path formed by the first operational amplifier chip 61, the first AD acquisition chip 63, the FPGA 20, the FIFO buffer 43, and the eMMC array 42 constitutes a high-speed analog data recording channel.
[0100] It should be noted that the aforementioned FIFO buffer 43 can be used to temporarily store data written by FPGA 20.
[0101] In the specific implementation, the data transmission path formed by the first operational amplifier chip 61, the first AD acquisition chip 63, the FPGA 20, the FIFO buffer 43, and the eMMC array 42 constitutes a high-speed analog data recording channel. In the high-speed analog data recording channel, the high-speed analog signal is processed by the first operational amplifier chip 61, the first AD acquisition chip 63, and the FPGA 20, and then written by the FPGA 20 into the FIFO buffer 43 for buffering. After the amount of buffered data reaches the set amount of data, it is quickly written into the eMMC array 42 in HS200 analog-to-digital format.
[0102] In this embodiment, the storage module 40 further includes an eMMC single chip 45.
[0103] The ARM processor 30 has an internal random access memory (RAM) cache 44;
[0104] The eMMC single chip 45 is connected to the ARM processor 30.
[0105] The data transmission path formed by the second operational amplifier chip 62, the second AD acquisition chip 64, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes a low-speed analog data recording channel.
[0106] The data transmission path formed by the RS422 isolation transceiver chip 65, the protocol conversion chip 66, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes an RS422 data recording channel.
[0107] The data transmission path formed by the CAN isolation transceiver chip 67, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes the CAN data recording channel.
[0108] It should be noted that the aforementioned RAM cache 44 can be used to temporarily store data written by the ARM processor 30.
[0109] In the specific implementation, the data transmission path formed by the second operational amplifier chip 62, the second AD acquisition chip 64, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes a low-speed analog data recording channel. In the low-speed analog data recording channel, the low-speed analog signal is processed by the second operational amplifier chip 62, the second AD acquisition chip 64, and the ARM processor 30, and then written by the ARM processor 30 to the RAM cache 44 for caching. After the cached data reaches the set data amount, it is written to the eMMC single chip 45.
[0110] The data transmission path formed by the RS422 isolation transceiver chip 65, the protocol conversion chip 66, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes the RS422 data recording channel. In the RS422 data recording channel, the RS422 signal is processed by the RS422 isolation transceiver chip 65, the protocol conversion chip 66, and the ARM processor 30, and then written by the ARM processor 30 to the RAM cache 44 for caching. After the cached data reaches the set data amount, it is written to the eMMC single chip 45.
[0111] The data transmission path formed by the CAN isolation transceiver chip 67, the ARM processor 30, the RAM cache 44, and the eMMC single chip 45 constitutes the CAN data recording channel. In the CAN data recording channel, after the CAN signal passes through the CAN isolation transceiver chip 67 and the ARM processor 30, it is written by the ARM processor 30 into the RAM cache 44 for caching. After the cached data reaches the set data amount, it is written into the eMMC single chip 45.
[0112] It should be understood that the aforementioned multimodal signal recording device has a video recording channel, a high-speed analog data recording channel, a low-speed analog data recording channel, an RS422 data recording channel, and a CAN data recording channel. Different data recording channels can be used for different signals, which effectively improves data recording efficiency.
[0113] In this embodiment, the multimodal signal recording device further includes a data export module.
[0114] The data export module includes a network interface and an RS485 isolation chip 51.
[0115] The network interface is connected to the FPGA 20 and the ARM processor 30, respectively.
[0116] The RS485 isolation chip 51 is connected to the FPGA 20 and the ARM processor 30 respectively.
[0117] The network interface includes: a first network physical layer (PHY) 52, a second network PHY 53, and a network switch 54.
[0118] The network switch is connected to the first network PHY and the second network PHY respectively;
[0119] The first network PHY is connected to the FPGA, and the second network PHY is connected to the ARM processor.
[0120] It should be noted that the first network PHY 52, the second network PHY 53, and the network switch 54 constitute a network interface that can be used as a high-speed output interface, while the RS485 isolation chip 51 can be used as a low-speed output interface.
[0121] In a specific implementation, when the multimodal signal recording device is connected to a host computer, the FPGA 20 and the ARM processor 30 can export the stored data to the host computer via a network interface or an RS485 isolation chip 51 according to the received export command. For example, upon receiving a high-speed export command, the FPGA 20 can read the data in the eMMC array 42 and output it to the network switch 54 through the first network PHY 52; the ARM processor 30 can read the data in the eMMC single chip 45 and output it to the network switch 54 through the second network PHY 53. The network switch 54 then exports the received data to the host computer. Upon receiving a low-speed export command, the FPGA 20 can read the data in the eMMC array 42 and export it to the host computer via the RS485 isolation chip 51; the ARM processor 30 can read the data in the eMMC single chip 45 and export it to the host computer via the RS485 isolation chip 51.
[0122] The data export channels for video signals, analog signals, and digital signals are completely independent. For video signal data export, FPGA 20 transmits the data to the host computer using the User Datagram Protocol (UDP) at gigabit bandwidth. For analog and digital signal data export, ARM processor 30 transmits the data to the host computer using the Transmission Control Protocol (TCP) at 100 Mbps bandwidth.
[0123] It should be understood that the data export module of the aforementioned multimodal signal recording device includes a network interface and an RS485 isolation chip 51, supporting both high-speed and low-speed export interfaces. During debugging, the network interface is used to export data at high speed. In complex environments where the network interface cannot be used, the RS485 isolation chip 51 can be used to export data at low speed, expanding the application scenarios and effectively improving the flexibility of data export.
[0124] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.
Claims
1. A multimodal signal recording device, characterized in that, The multimodal signal recording device includes: a data receiving module, an FPGA, an ARM processor, and a storage module; The data receiving module includes: a CML transceiver chip for receiving video signals and a signal conditioning module for receiving analog-to-digital signals; The FPGA is connected to the CML transceiver chip and the storage module respectively, and the data transmission path formed by the CML transceiver chip, the FPGA and the storage module constitutes a video recording channel; The ARM processor is connected to the signal conditioning module and the storage module respectively, and the data transmission path formed by the signal conditioning module, the ARM processor and the storage module constitutes an analog-to-digital recording channel.
2. The multimodal signal recording device as described in claim 1, characterized in that, The signal conditioning module includes: a first operational amplifier chip for receiving high-speed analog signals, a second operational amplifier chip for receiving low-speed analog signals, a first AD acquisition chip, and a second AD acquisition chip; The first AD acquisition chip is connected to the first operational amplifier chip and the FPGA respectively; The second AD acquisition chip is connected to the second operational amplifier chip and the ARM processor respectively.
3. The multimodal signal recording device as described in claim 2, characterized in that, The CML transceiver chip is model TLK2711; Both the first operational amplifier chip and the second operational amplifier chip are of the OPA4277 model.
4. The multimodal signal recording device as described in claim 2, characterized in that, The signal conditioning module further includes: an RS422 isolated transceiver chip for receiving RS422 signals, a protocol conversion chip, and a CAN isolated transceiver chip for receiving CAN signals; The protocol conversion chip is connected to the RS422 isolated transceiver chip and the ARM processor, respectively. The CAN isolation transceiver chip is connected to the ARM processor.
5. The multimodal signal recording device as described in claim 4, characterized in that, The RS422 isolated transceiver chip is model ADM2582; The CAN isolation transceiver chip is model ADM3053; The first AD acquisition chip is model ADS8661; The second AD acquisition chip is model ADS8688; The protocol conversion chip is model CH438.
6. The multimodal signal recording device as described in claim 4, characterized in that, The storage module includes: a DDR3 cache and an eMMC array; Both the DDR3 cache and the eMMC array are connected to the FPGA. The data transmission path formed by the CML transceiver chip, the FPGA, the DDR3, and the eMMC array constitutes the video recording channel.
7. The multimodal signal recording device as described in claim 6, characterized in that, The FPGA internally includes: a FIFO buffer; The data transmission path formed by the first operational amplifier chip, the first AD acquisition chip, the FPGA buffer, the FIFO, and the eMMC array constitutes a high-speed analog data recording channel.
8. The multimodal signal recording device as described in claim 7, characterized in that, The storage module also includes: an eMMC single chip; The ARM processor internally includes: RAM cache; The eMMC single chip is connected to the ARM processor; The data transmission path formed by the second operational amplifier chip, the second AD acquisition chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes a low-speed analog data recording channel; The data transmission path formed by the RS422 isolation transceiver chip, the protocol conversion chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes the RS422 data recording channel. The data transmission path formed by the CAN isolation transceiver chip, the ARM processor, the RAM cache, and the eMMC single chip constitutes the CAN data recording channel.
9. The multimodal signal recording device as described in claim 8, characterized in that, The multimodal signal recording device further includes: a data export module; The data export module includes: a network interface and an RS485 isolation chip; The network interface is connected to the FPGA and the ARM processor, respectively; The RS485 isolation chip is connected to both the FPGA and the ARM processor.
10. The multimodal signal recording device as described in claim 9, characterized in that, The network interface includes: a first network PHY, a second network PHY, and a network switch; The network switch is connected to the first network PHY and the second network PHY respectively; The first network PHY is connected to the FPGA, and the second network PHY is connected to the ARM processor.