A double-sided packaged semiconductor plastic package structure

By optimizing the double-sided packaging structure and advanced processes, the problem of inconsistent soldering parameters between solder balls and chip solder caps was solved, improving packaging stability and the number of I/O pins, and achieving efficient semiconductor molding and packaging.

CN224482072UActive Publication Date: 2026-07-10FARACONIX TECH CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
FARACONIX TECH CO LTD
Filing Date
2025-06-27
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In existing technologies, the different soldering parameters required for solder balls and chip solder caps are difficult to meet simultaneously, which can easily lead to poor soldering. Furthermore, the flux cleaning process can damage or cause solder balls to fall off.

Method used

The semiconductor molding compound structure employs double-sided packaging, including molding compound, packaging substrate, chip assembly, pre-fabricated copper pillars, sputtered metal shielding layer, and solder bumps. Through advanced Fan-out wafer reconstruction and bumping processes, the soldering process is optimized to form stable solder ball connections.

Benefits of technology

It improves the stability and efficiency of the packaging process, increases the number of I/O pins and integration, reduces solder ball damage, and achieves more efficient product processing and integration.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model relates to the technical field of semiconductor plastic package, concretely relates to a kind of semiconductor plastic package structure of double-sided packaging, including plastic seal material, package substrate, multiple chip components and multiple prefabricated copper columns, each chip component includes multiple bumps and chip body, package substrate is set on plastic seal material, chip body is fixedly connected with two bumps, multiple bumps are respectively set on the side of package substrate.Make product packaging procedure more simple and efficient, and the processing of product will be more stable mature, and can provide higher IO pin number, the space of double-sided available is larger, product integration is higher, and advanced Fan-out wafer reconstruction process is used, multiple chips and IO copper column are integrated into reconstructed wafer, then according to existing bumping process, processing is carried out, the packaging of rear end is moved to middle process, and the efficiency and integration of processing are improved.
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Description

Technical Field

[0001] This utility model relates to the field of semiconductor molding technology, and in particular to a double-sided semiconductor molding structure. Background Technology

[0002] Semiconductor molding is one of the core processes in semiconductor packaging. By isolating the chip from the external environment, it provides mechanical protection, electrical connection and heat dissipation functions for the chip, directly affecting the reliability, performance and lifespan of semiconductor devices.

[0003] Current technologies also employ double-sided packaging. These technologies require the development of high-precision fixtures to complete double-sided ball placement. Ball placement and chip flip mounting are completed in the same process, which can easily lead to soldering defects during reflow soldering, such as interconnection between solder balls and chip functional areas.

[0004] However, existing technology cannot solve the different requirements of solder balls and chip solder caps for soldering parameters, which can easily lead to poor soldering; moreover, the subsequent flux cleaning process can damage the solder balls or cause them to fall off due to high-pressure water cleaning. Utility Model Content

[0005] The purpose of this invention is to provide a double-sided packaged semiconductor plastic encapsulation structure, which solves the problem in the prior art that cannot address the different requirements of solder balls and chip solder caps for welding parameters, which easily leads to poor solder joints; and the subsequent flux cleaning process can cause damage to the solder balls or cause the solder balls to fall off due to high-pressure water cleaning.

[0006] To achieve the above objectives, this utility model provides a double-sided packaged semiconductor molding structure, including molding compound, packaging substrate, multiple chip components and multiple pre-fabricated copper pillars. Each chip component includes multiple bumps and a chip body. The packaging substrate is disposed on the molding compound. The chip body is fixedly connected to two of the bumps. The multiple bumps are respectively disposed on the side of the packaging substrate.

[0007] The double-sided packaged semiconductor molding structure further includes a sputtered metal shielding layer, which is disposed on the molding compound.

[0008] The double-sided packaged semiconductor molding structure further includes multiple tin bumps, which are respectively disposed on the corresponding prefabricated copper pillars.

[0009] The double-sided encapsulated semiconductor molding structure further includes resin, which is disposed on the molding compound.

[0010] The resin is located at the lower end of the plurality of prefabricated copper pillars, and the plurality of chip components are symmetrically arranged on the packaging substrate.

[0011] This invention discloses a double-sided semiconductor molding compound structure. The top side of the package is completed, with the chip body and SMD soldered to the packaging substrate via reflow. Top-side molding is then completed. Next, bottom-side mounting is performed: the chip body and pre-formed copper pillars are mounted onto a temporary bonding film, and the package is molded into a circular wafer or a square block. Nickel and tin caps are electroplated, and solder balls are formed via reflow. The reconstructed chip modules are cut into individual chips and then taped for later use. These reconstructed chip modules are then mounted onto the back of the top-side molded substrate and soldered to the back of the substrate via reflow. Finally, molding is completed. This device simplifies and improves the product packaging process, resulting in more stable and mature product processing. It can provide a higher number of I / O pins, utilizes more space on both sides, and achieves higher product integration. Furthermore, it employs an advanced fan-out wafer reconstruction process, integrating multiple chips and I / O pillars into the reconstructed wafer. Then, it is processed using the existing bumping process, moving the back-end packaging to the mid-process, thus improving processing efficiency and integration. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0013] Figure 1 This is a schematic diagram of the overall structure of this utility model.

[0014] Figure 2 This is a flowchart of the overall 1-3 steps of this utility model.

[0015] Figure 3 This is a 4-5 step flowchart of the entire utility model.

[0016] 1- Molding compound, 2- Packaging substrate, 3- Pre-formed copper pillar, 4- Bump, 5- Chip body, 6- Sputtered metal shielding layer, 7- Tin bump, 8- Resin. Detailed Implementation

[0017] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0018] Please see Figures 1-3 ,in, Figure 1 This is a schematic diagram of the overall structure of this utility model. Figure 2 This is a flowchart of the entire utility model in steps 1-3. Figure 3 This is a 4-5 step flowchart of the entire utility model.

[0019] This utility model provides a double-sided packaged semiconductor molding compound structure, including molding compound 1, packaging substrate 2, multiple chip components and multiple pre-fabricated copper pillars 3. Each chip component includes multiple bumps 4 and a chip body 5. The packaging substrate 2 is disposed on the molding compound 1. The chip body 5 is fixedly connected to two of the bumps 4. The multiple bumps 4 are respectively disposed on the side of the packaging substrate 2. The double-sided packaged semiconductor molding compound structure also includes a sputtered metal shielding layer 6, which is disposed on the molding compound 1. The double-sided packaged semiconductor molding compound structure also includes multiple tin bumps 7, which are respectively disposed on the corresponding pre-fabricated copper pillars 3.

[0020] In this embodiment, after the top side is packaged, the chip body 5 and SMD are reflow soldered to the packaging substrate 2; top side molding is completed; then bottom side mounting is completed: the chip body 5 and the pre-made copper pillars 3 are mounted on a temporary bonding film, and molded into a circular wafer or a square block, and nickel and tin caps are electroplated, and reflow is used to form solder balls; after being cut into individual reconstructed chip modules, they are tapered for later use. The reconstructed chip modules are mounted on the back side of the substrate of the top side molded semi-finished product, and reflow soldered to the back side of the substrate; finally, molding is completed. This device makes the product packaging process simpler and more efficient, and the product processing is more stable and mature. It can provide a higher number of IO pins, more usable space on both sides, and higher product integration. It adopts an advanced Fan-out wafer reconstruction process to integrate multiple chips and IO copper pillars into the reconstructed wafer, and then processes it according to the existing bumping process, moving the back-end packaging to the middle process, improving processing efficiency and integration.

[0021] Furthermore, the double-sided packaged semiconductor molding structure also includes resin 8, which is disposed on the molding compound 1. The resin 8 is located at the lower end of the plurality of prefabricated copper pillars 3, and the plurality of chip components are symmetrically disposed on the packaging substrate 2.

[0022] In this embodiment, the process employed can be selected based on the product's integration density. Advanced processes can be chosen for multi-chip reconstruction and bumping; mature processes can also be selected for low-density multi-chip reconstruction. Furthermore, the process in this application is flexible, highly compatible, and suitable for advanced high-density packaging and mature packaging. It requires fewer packaging fixtures and has low development costs. Additionally, during molding, the thickness of the bottom surface is reduced; typically, the thickness of the ground bottom surface is 100-150µm, exposing the back of the chip and the pre-fabricated copper pillars 3. Solder paste is printed on the exposed surface of the pre-fabricated copper pillars 3, followed by reflow to generate solder bumps 7. The chip is then cut into individual packaged ICs; an EMI electromagnetic shielding metal layer is sputtered; the chip and pre-fabricated copper pillars are mounted onto a temporary bonding film, and then encapsulated into a circular wafer or a square panel block. Nickel plating and solder cap plating are completed, followed by reflow to form solder balls; the chip is cut into individual fan-out reconstructed chip modules and then taped for later use; the fan-out chip modules are then packaged into individual fan-out reconstructed chip modules. The reconstructed chip module is mounted onto the back of the substrate of the semi-finished product completed in step 2, and soldered to the back of the substrate through reflow; the bottom side is then encapsulated.

[0023] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A double-sided packaged semiconductor molding compound structure, characterized in that, Includes molding compound, packaging substrate, multiple chip components and multiple prefabricated copper pillars; Each of the chip components includes multiple bumps and a chip body. The packaging substrate is disposed on the molding compound. The chip body is fixedly connected to two of the bumps. The multiple bumps are respectively disposed on the side of the packaging substrate.

2. The double-sided packaged semiconductor molding structure as described in claim 1, characterized in that, The double-sided packaged semiconductor molding structure further includes a sputtered metal shielding layer, which is disposed on the molding compound.

3. The double-sided packaged semiconductor molding structure as described in claim 2, characterized in that, The double-sided packaged semiconductor molding structure also includes multiple tin bumps, which are respectively disposed on the corresponding prefabricated copper pillars.

4. The double-sided packaged semiconductor molding structure as described in claim 3, characterized in that, The double-sided packaged semiconductor molding structure also includes a resin, which is disposed on the molding compound.

5. The double-sided packaged semiconductor molding structure as described in claim 4, characterized in that, The resin is located at the lower end of the plurality of prefabricated copper pillars, and the plurality of chip components are symmetrically arranged on the packaging substrate.