Switched filter bank based signal amplitude equalization circuit

Abstract

A signal amplitude equalization circuit based on a switch filter bank is characterized by being provided with a switch filter bank, the signal transceiver end of the switch filter bank being connected to a controller, the switch filter bank being provided with a radio frequency input switch, N filters and a radio frequency output switch; the input end of the radio frequency input switch acquires an original data signal, the radio frequency input switch being provided with N output ends, one output end of the radio frequency input switch being connected to one input end of the radio frequency output switch via one filter, and the output end of the radio frequency output switch outputting a data signal after in-band fluctuation optimization. Effect: The optimization of filter in-band fluctuation can be quickly realized at extremely low cost, which is flexible and efficient, and has extremely high economic benefits and practical value.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency filter technology, and in particular to a signal amplitude equalization circuit based on a switching filter bank. Background Technology

[0002] In the existing technology, the bandwidth requirements of radio frequency filters are becoming wider and wider as the usage environment changes, from tens of megabits to hundreds of megabits. As the bandwidth increases, the difference in gain between the left and right sidebands of the filter becomes larger and larger, and the in-band fluctuation of the filter becomes larger and larger.

[0003] The drawbacks of existing technologies are that it is difficult to further reduce the in-band ripple range of filters using previous technical solutions, and huge costs are required to meet the performance requirements. Utility Model Content

[0004] This invention provides a signal amplitude equalization circuit based on a switched filter bank, which can quickly and at extremely low cost optimize the in-band ripple of the filter and reduce the in-band ripple range of the filter.

[0005] To achieve the above objectives, this utility model provides a signal amplitude equalization circuit based on a switching filter bank, the key of which is: a switching filter bank is provided, the signal transceiver terminals of the switching filter bank are connected to a controller, and the switching filter bank is provided with an RF input switch, N filters and an RF output switch;

[0006] The input terminal of the radio frequency input switch acquires the raw data signal. The radio frequency input switch is provided with N output terminals. One output terminal of the radio frequency input switch is connected to one input terminal of the radio frequency output switch via a filter. The output terminal of the radio frequency output switch outputs the data signal with in-band ripple optimization.

[0007] Through the above design, the controller selects amplitude equalization filters with various tilt levels in the switching filter bank according to the in-band fluctuation of the original waveform. Then, by superimposing the original waveform with the output waveform of the amplitude equalization filter, the original waveform is optimized, the in-band fluctuation range of the filter is reduced, and the in-band fluctuation of the product is optimized to meet the target requirements.

[0008] Preferably, the N filters include one pass-through filter and N-1 amplitude equalization filters, wherein the amplitude equalization filters include M left-high and right-low filters and K left-low and right-high filters, N = 1 + M + K, and M, K, and N are all positive integers;

[0009] Among them, the left cutoff frequency gain of the left-high and right-low filter is greater than the right cutoff frequency gain; the left cutoff frequency gain of the left-low and right-high filter is less than the right cutoff frequency gain.

[0010] The pass-through filter is used to output the original waveform. The left-high-right-low filter and the left-low-right-high filter are used to achieve amplitude equalization processing of waveforms with different tilt levels by using left and right cutoff frequency gains of different magnitudes. Then, by superimposing the original waveform output by the RF output switch pass-through filter with the amplitude equalization waveform output by the corresponding amplitude equalization filter, the in-band ripple of the product is optimized.

[0011] Preferably, all the filters have a bandwidth of 500MHz, the left cutoff frequency gain range of the left high and right low filter is (0, 10)dB higher than the right cutoff frequency gain range, and the left cutoff frequency gain range of the left low and right high filter is (0, 10)dB lower than the right cutoff frequency gain range.

[0012] Preferably, the pass-through filter is provided with a capacitor C56. The front end of the capacitor C56 is connected to the RF input switch, and the rear end of the capacitor C56 is connected to the RF output switch in series with a resistor R11 and a capacitor C57. The two ends of the resistor R11 are also connected in series with a resistor R12 and a resistor R13 respectively and then grounded.

[0013] Preferably, the left-high-right-low filter includes a capacitor C47. The front end of capacitor C47 is connected to the RF input switch, and the rear end of capacitor C47 is connected to the front end of resistor R8. A resistor R15 is connected in series with the rear end of capacitor C47 before grounding. The rear end of resistor R8 is connected to the front end of inductor L13. A resistor R16, a capacitor C51, and a capacitor C52 are connected in series with the rear end of resistor R8 before grounding. The rear end of inductor L13 is connected in series with capacitor C48 before connecting to the RF output switch. A capacitor C53 and a capacitor C54 are connected in series with the rear end of inductor L13 before grounding.

[0014] Preferably, the left-high-right-low filter includes a capacitor C49. The front end of the capacitor C49 is connected to the RF input switch, and the rear end of the capacitor C49 is connected to the front end of the inductor L18. The rear end of the capacitor C49 is also connected in series with capacitors C64 and C66 before being grounded. The rear end of the inductor L18 is connected in series with capacitor C50 before being connected to the RF output switch. The rear end of the inductor L18 is also connected in series with capacitors C67 and C68 before being grounded.

[0015] Preferably, the left low and right high filter is provided with a capacitor C45. The front end of the capacitor C45 is connected to the RF input switch, and the rear end of the capacitor C45 is connected to the front end of the capacitor C11. The rear end of the capacitor C11 is connected in series with capacitors C14 and C46 and then connected to the RF output switch. The rear end of the capacitor C11 is also connected to ground via an inductor L9.

[0016] Preferably, the first signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R2 and R6. The common terminal of resistors R2 and R6 is also connected in series with resistor R59 and then grounded. The first signal transceiver terminal of the RF input switch is also connected in series with capacitor C4 and then grounded. The second signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R4 and R5. The common terminal of resistors R4 and R5 is also connected in series with resistor R57 and then grounded. The second signal transceiver terminal of the RF input switch is also connected in series with capacitor C6 and then grounded.

[0017] The power supply terminal of the RF input switch is connected to the front end of the inductor L4. The power supply terminal of the RF input switch is also connected to ground after a capacitor C10 is connected in series. The rear end of the inductor L4 is connected to the power supply after a resistor R27 is connected in series. The rear end of the inductor L4 is also connected to ground after a capacitor C32 is connected in series. The rear end of the inductor L4 is also connected to ground after a resistor R29 is connected in series.

[0018] Preferably, the first signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R1, and the first signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C3; the second signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R3 and a resistor R50, and the common terminal of the resistors R3 and R50 is also connected to ground after a series resistor R56, and the second signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C5.

[0019] The power supply terminal of the RF output switch is connected to the front end of the inductor L3. The power supply terminal of the RF output switch is also connected to ground via capacitors C8 and C42. The rear end of the inductor L3 is connected to the power supply via resistor R27. The rear end of the inductor L3 is also connected to ground via capacitor C34. The rear end of the inductor L4 is also connected to ground via resistor R29. The output terminal of the RF output switch outputs the data signal with in-band ripple optimization via capacitor C21.

[0020] The beneficial effects of this invention are: it can quickly optimize the in-band ripple of a filter at extremely low cost, reduce the in-band ripple range of the filter, and is flexible and efficient, with extremely high economic benefits and practical value. Attached Figure Description

[0021] Figure 1 This is a block diagram of the switching filter bank circuit structure in the embodiment;

[0022] Figure 2 This is a circuit diagram of the switching filter bank in the embodiment;

[0023] Figure 3 Figure a shows a comparison of the original waveform, the amplitude-equalized waveform, and the superimposed waveform in the embodiment.

[0024] Figure 4 Figure b shows a comparison of the original waveform, the amplitude-equalized waveform, and the superimposed waveform in the embodiment. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific examples. The following embodiments or drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0026] like Figure 1 As shown, a signal amplitude equalization circuit based on a switching filter bank is provided, wherein a switching filter bank is provided, the signal transceiver terminals of the switching filter bank are connected to a controller, and the switching filter bank is provided with an RF input switch, N filters and an RF output switch.

[0027] The input terminal of the radio frequency input switch acquires the raw data signal. The radio frequency input switch is provided with N output terminals. One output terminal of the radio frequency input switch is connected to one input terminal of the radio frequency output switch via a filter. The output terminal of the radio frequency output switch outputs the data signal with in-band ripple optimization.

[0028] The controller selects amplitude equalizers with various tilt levels from the switching filter bank based on the in-band fluctuations of the original waveform. Then, by superimposing the original waveform with the output waveform of the amplitude equalizer, the original waveform is optimized, reducing the in-band fluctuation range of the filter to meet the required specifications. The waveform changes during this process are shown below. Figure 3 , Figure 4 As shown.

[0029] All of the filters have a bandwidth of 500MHz. The left cutoff frequency gain range of the left high and right low filter is (0, 10)dB higher than that of the right cutoff frequency gain range; the left cutoff frequency gain range of the left low and right high filter is (0, 10)dB lower than that of the right cutoff frequency gain range.

[0030] like Figure 2 As shown, the switching filter bank is configured with one pass-through filter and three amplitude equalizer filters. The three amplitude equalizer filters include two left-high and right-low filters and one left-low and right-high filter.

[0031] Among them, the left cutoff frequency gain of the left-high and right-low filter is greater than the right cutoff frequency gain; the left cutoff frequency gain of the left-low and right-high filter is less than the right cutoff frequency gain.

[0032] In this embodiment, the gain range of one left-high right-low filter is 1.8dB, that is, the gain range of the left cutoff frequency is 1.8dB higher than the gain range of the right cutoff frequency; the gain range of another left-high right-low filter is 3.5dB; and the gain range of one left-low right-high filter is 3.5dB.

[0033] If the in-band ripple of the overall filter is in the range of 1-2dB (left high, right low), the corresponding amplitude equalizer is 1.8dB (left high, right low; this left high, right low filter will become left low, right high after passing through the cepstral circuit). If the in-band ripple of the overall filter is in the range of 2-4dB (left high, right low), the corresponding amplitude equalizer is 3.5dB (left high, right low). If the in-band ripple of the overall filter is in the range of 2-4dB (left low, right high), the corresponding amplitude equalizer is 2dB (left low, right high).

[0034] The pass-through filter is equipped with a capacitor C56. The front end of the capacitor C56 is connected to the RF input switch. The rear end of the capacitor C56 is connected in series with a resistor R11 and a capacitor C57, and then connected to the RF output switch. The two ends of the resistor R11 are also connected in series with a resistor R12 and a resistor R13, and then grounded.

[0035] The left-high-right-low filter includes a capacitor C47. The front end of capacitor C47 is connected to the RF input switch, and the rear end of capacitor C47 is connected to the front end of resistor R8. Resistor R15 is connected in series with the rear end of capacitor C47 before grounding. The rear end of resistor R8 is connected to the front end of inductor L13. Resistor R16, capacitor C51, and capacitor C52 are connected in series with the rear end of resistor R8 before grounding. The rear end of inductor L13 is connected in series with capacitor C48 before connecting to the RF output switch. Capacitors C53 and C54 are connected in series with the rear end of inductor L13 before grounding.

[0036] The left-high-right-low filter is equipped with a capacitor C49. The front end of the capacitor C49 is connected to the RF input switch, and the rear end of the capacitor C49 is connected to the front end of the inductor L18. The rear end of the capacitor C49 is also connected in series with capacitors C64 and C66 before being grounded. The rear end of the inductor L18 is connected in series with capacitor C50 before being connected to the RF output switch. The rear end of the inductor L18 is also connected in series with capacitors C67 and C68 before being grounded.

[0037] The left-low, right-high filter is equipped with a capacitor C45. The front end of the capacitor C45 is connected to the RF input switch, and the rear end of the capacitor C45 is connected to the front end of the capacitor C11. The rear end of the capacitor C11 is connected in series with capacitors C14 and C46 and then connected to the RF output switch. The rear end of the capacitor C11 is also connected to ground via an inductor L9.

[0038] The first signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R2 and R6. The common terminal of resistors R2 and R6 is also connected in series with resistor R59 and then grounded. The first signal transceiver terminal of the RF input switch is also connected in series with capacitor C4 and then grounded. The second signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R4 and R5. The common terminal of resistors R4 and R5 is also connected in series with resistor R57 and then grounded. The second signal transceiver terminal of the RF input switch is also connected in series with capacitor C6 and then grounded.

[0039] The power supply terminal of the RF input switch is connected to the front end of the inductor L4. The power supply terminal of the RF input switch is also connected to ground after a capacitor C10 is connected in series. The rear end of the inductor L4 is connected to the power supply after a resistor R27 is connected in series. The rear end of the inductor L4 is also connected to ground after a capacitor C32 is connected in series. The rear end of the inductor L4 is also connected to ground after a resistor R29 is connected in series.

[0040] The first signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R1. The first signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C3. The second signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R3 and a resistor R50. The common terminal of the resistors R3 and R50 is also connected to ground after a series resistor R56. The second signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C5.

[0041] The power supply terminal of the RF output switch is connected to the front end of the inductor L3. The power supply terminal of the RF output switch is also connected to ground via capacitors C8 and C42. The rear end of the inductor L3 is connected to the power supply via resistor R27. The rear end of the inductor L3 is also connected to ground via capacitor C34. The rear end of the inductor L4 is also connected to ground via resistor R29. The output terminal of the RF output switch outputs the data signal with in-band ripple optimization via capacitor C21.

[0042] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A signal amplitude equalization circuit based on a switched filter bank, characterized in that: A switching filter bank is provided, and the signal transceiver of the switching filter bank is connected to the controller. The switching filter bank is provided with an RF input switch, N filters and an RF output switch. The input terminal of the radio frequency input switch acquires the raw data signal. The radio frequency input switch is provided with N output terminals. One output terminal of the radio frequency input switch is connected to one input terminal of the radio frequency output switch via a filter. The output terminal of the radio frequency output switch outputs the data signal with in-band ripple optimization.

2. The signal amplitude equalization circuit based on a switched filter bank according to claim 1, characterized in that: The N filters include one pass-through filter and N-1 amplitude equalization filters, wherein the amplitude equalization filters include M left-high and right-low filters and K left-low and right-high filters, and N = 1 + M + K; Among them, the left cutoff frequency gain of the left-high and right-low filter is greater than the right cutoff frequency gain; the left cutoff frequency gain of the left-low and right-high filter is less than the right cutoff frequency gain.

3. The signal amplitude equalization circuit based on a switched filter bank according to claim 2, characterized in that: All of the filters have a bandwidth of 500MHz. The left cutoff frequency gain range of the left high and right low filter is (0, 10)dB higher than that of the right cutoff frequency gain range; the left cutoff frequency gain range of the left low and right high filter is (0, 10)dB lower than that of the right cutoff frequency gain range.

4. The signal amplitude equalization circuit based on a switched filter bank according to claim 2, characterized in that: The pass-through filter is equipped with a capacitor C56. The front end of the capacitor C56 is connected to the RF input switch. The rear end of the capacitor C56 is connected in series with a resistor R11 and a capacitor C57, and then connected to the RF output switch. The two ends of the resistor R11 are also connected in series with a resistor R12 and a resistor R13, and then grounded.

5. The signal amplitude equalization circuit based on a switched filter bank according to claim 2, characterized in that: The left-high-right-low filter includes a capacitor C47. The front end of capacitor C47 is connected to the RF input switch, and the rear end of capacitor C47 is connected to the front end of resistor R8. Resistor R15 is connected in series with the rear end of capacitor C47 before grounding. The rear end of resistor R8 is connected to the front end of inductor L13. Resistor R16, capacitor C51, and capacitor C52 are connected in series with the rear end of resistor R8 before grounding. The rear end of inductor L13 is connected in series with capacitor C48 before connecting to the RF output switch. Capacitors C53 and C54 are connected in series with the rear end of inductor L13 before grounding.

6. The signal amplitude equalization circuit based on a switched filter bank according to claim 2, characterized in that: The left-high-right-low filter is equipped with a capacitor C49. The front end of the capacitor C49 is connected to the RF input switch, and the rear end of the capacitor C49 is connected to the front end of the inductor L18. The rear end of the capacitor C49 is also connected in series with capacitors C64 and C66 before being grounded. The rear end of the inductor L18 is connected in series with capacitor C50 before being connected to the RF output switch. The rear end of the inductor L18 is also connected in series with capacitors C67 and C68 before being grounded.

7. The signal amplitude equalization circuit based on a switched filter bank according to claim 2, characterized in that: The left-low, right-high filter is equipped with a capacitor C45. The front end of the capacitor C45 is connected to the RF input switch, and the rear end of the capacitor C45 is connected to the front end of the capacitor C11. The rear end of the capacitor C11 is connected in series with capacitors C14 and C46 and then connected to the RF output switch. The rear end of the capacitor C11 is also connected to ground via an inductor L9.

8. The signal amplitude equalization circuit based on a switched filter bank according to claim 1, characterized in that: The first signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R2 and R6. The common terminal of resistors R2 and R6 is also connected in series with resistor R59 and then grounded. The first signal transceiver terminal of the RF input switch is also connected in series with capacitor C4 and then grounded. The second signal transceiver terminal of the RF input switch is connected to the controller after being connected in series with resistors R4 and R5. The common terminal of resistors R4 and R5 is also connected in series with resistor R57 and then grounded. The second signal transceiver terminal of the RF input switch is also connected in series with capacitor C6 and then grounded. The power supply terminal of the RF input switch is connected to the front end of the inductor L4. The power supply terminal of the RF input switch is also connected to ground after a capacitor C10 is connected in series. The rear end of the inductor L4 is connected to the power supply after a resistor R27 is connected in series. The rear end of the inductor L4 is also connected to ground after a capacitor C32 is connected in series. The rear end of the inductor L4 is also connected to ground after a resistor R29 is connected in series.

9. The signal amplitude equalization circuit based on a switched filter bank according to claim 1, characterized in that: The first signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R1. The first signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C3. The second signal transceiver terminal of the RF output switch is connected to the controller after a series resistor R3 and a resistor R50. The common terminal of the resistors R3 and R50 is also connected to ground after a series resistor R56. The second signal transceiver terminal of the RF output switch is also connected to ground after a series capacitor C5. The power supply terminal of the RF output switch is connected to the front end of the inductor L3. The power supply terminal of the RF output switch is also connected to ground via capacitors C8 and C42. The rear end of the inductor L3 is connected to the power supply via resistor R27. The rear end of the inductor L3 is also connected to ground via capacitor C34. The rear end of the inductor L4 is also connected to ground via resistor R29. The output terminal of the RF output switch outputs the data signal with in-band ripple optimization via capacitor C21.

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