Single-inductor multi-output voltage converter and power supply device

Abstract

The application discloses a single-inductor multi-output voltage converter and a power supply device. The single-inductor multi-output voltage converter comprises a voltage conversion topology, a current collection module, a feedback adjustment module and a branch gating module. The voltage conversion topology comprises a main switch module, an inductor and a plurality of output branches. The feedback adjustment module is configured to input output voltages corresponding to the output branches respectively and a first reference voltage, output branch errors corresponding to the output branches respectively, and output an adjustment signal corresponding to an inductor current collected by the current collection module and a total error to the main switch module, wherein the total error is a sum of the branch errors. The branch gating module is configured to sequentially turn on the output switches, and the on time of each output switch is proportional to the corresponding branch error. In this way, the performance of the single-inductor multi-output voltage converter can be improved.

Description

Technical Field

[0001] This application relates to the field of power management technology, and in particular to a single-inductor multi-output voltage converter and power supply device. Background Technology

[0002] The single-inductor multi-output voltage converter is a novel multi-output switching converter structure that provides multiple output voltages using only a single inductor, enabling simultaneous power supply to multiple loads. Compared to multiple single-inductor single-output voltage converters, the single-inductor multi-output voltage converter reduces the number of inductors required in the circuit, thus reducing PCB space footprint. It is suitable for power management, communication equipment, consumer electronics, and other scenarios requiring miniaturization.

[0003] However, since a single inductor multi-output voltage converter shares a single inductor to transfer energy, in Continuous Conduction Mode (CCM), when the load corresponding to one output branch changes, the load of other output branches will also be affected, thus introducing intermodulation problems and resulting in lower performance of the single inductor multi-output voltage converter.

[0004] Therefore, improving the performance of single-inductor multi-output voltage converters has become an urgent technical problem to be solved. Utility Model Content

[0005] The main technical problem solved by this application is to provide a single-inductor multi-output voltage converter and power supply device, which can improve the performance of the single-inductor multi-output voltage converter.

[0006] To solve the above-mentioned technical problems, this application adopts the following technical solution: A single-inductor multi-output voltage converter is provided. The single-inductor multi-output voltage converter includes: a voltage conversion topology, including a main switch module, an inductor, and multiple output branches, each output branch including an output switch, and each output branch is used to provide a corresponding output voltage; a current acquisition module, the input terminal of which is connected to the inductor for acquiring the inductor current; a feedback adjustment module, connected to the output terminal of the current acquisition module, each output branch, and the main switch module, configured to input the output voltage and a first reference voltage corresponding to each output branch, and output the branch error corresponding to each output branch, and output an adjustment signal corresponding to the inductor current and the total error to the main switch module to adjust the inductor current; wherein the total error is the sum of the errors of each branch; and a branch selection module, connected to the feedback adjustment module and connected to the control terminal of each output switch, configured to sequentially turn on each output switch; wherein the conduction time of each output switch is proportional to the corresponding branch error.

[0007] Optionally, the feedback adjustment module includes branch error output terminals for outputting the errors of each branch; the branch gating module includes: a signal providing unit configured to provide a first signal; multiple gating switches, each with its first terminal connected to a branch error output terminal; a comparison unit, with its first input terminal connected to the output terminal of the signal providing unit, its second input terminal connected to the second terminal of each gating switch, and its output terminal connected to the configuration terminal of the signal providing unit; and a gating unit, including an input terminal and multiple output terminals, the input terminal of the gating unit connected to the output terminal of the comparison unit, for selecting... Each output terminal of the pass unit is connected to the control terminal of an output switch through the first drive module. Each output terminal of the select unit is also connected to the control terminal of a corresponding select switch. Each output terminal of the select unit is connected to an output switch and a select switch, which together form a switch combination. When the current switch combination is turned on, the signal value of the first signal increases from a preset value. When the signal value of the first signal increases to the current branch error, the comparison unit outputs a switching signal, causing the signal value of the first signal to decrease to the preset value. The select unit is then configured to turn off the current switch combination and turn on the next switch combination.

[0008] Optionally, the gating unit includes multiple first flip-flops, the data output terminal of the i-th first flip-flop is connected to the data input terminal of the (i+1)-th first flip-flop, the data output terminal of the last first flip-flop is connected to the data input terminal of the first first flip-flop, the clock input terminal of each first flip-flop is connected and serves as the input terminal of the gating unit, and the data output terminal of each first flip-flop is an output terminal of the gating unit; where i is greater than or equal to 1.

[0009] Optionally, the first signal is a sawtooth wave signal; and the comparison unit includes a first comparator, wherein the first input terminal, the second input terminal, and the output terminal of the first comparator are, in sequence, the first input terminal, the second input terminal, and the output terminal of the comparison unit.

[0010] Optionally, the signal providing unit includes a first power supply, a first capacitor, and a first configuration switch. The first end of the first capacitor is connected to the output end of the first power supply and the first end of the first configuration switch. The second end of the first capacitor and the second end of the first configuration switch are both grounded. The first end of the first capacitor is the output end of the signal providing unit, and the control end of the first configuration switch is the configuration end of the signal providing unit.

[0011] Optionally, the signal providing unit has multiple output terminals. The signal providing unit is used to count the clock, and the first signal is a digital signal. The comparison unit includes an analog-to-digital converter circuit and a digital comparison circuit. The analog-to-digital converter circuit includes an input terminal and multiple output terminals. The digital comparison circuit includes multiple first input terminals and multiple second input terminals. Each output terminal of the signal providing unit is connected to a first input terminal of the digital comparison circuit, and each output terminal of the analog-to-digital converter circuit is connected to a second input terminal of the digital comparison circuit. The multiple first input terminals of the digital comparison circuit, the input terminal of the analog-to-digital converter circuit, and the output terminal of the digital comparison circuit are, in sequence, the first input terminal, the second input terminal, and the output terminal of the comparison unit.

[0012] Optionally, the signal providing unit includes multiple trigger circuits. The output of the j-th trigger circuit is connected to the input of the (j+1)-th trigger circuit, and the input of the first trigger circuit is used to receive a clock signal; where j is greater than or equal to 1. For each trigger circuit, the trigger circuit includes a second flip-flop and an inverter. The data output of the second flip-flop is connected to the input of the inverter, and the output of the inverter is connected to the data input of the second flip-flop. The clock input of the second flip-flop and the output of the inverter are, in turn, the input and output of the trigger circuit. The data output of the second flip-flop is an output of the signal providing unit. The reset terminal of each second flip-flop is the configuration terminal of the signal providing unit.

[0013] Optionally, the digital comparison circuit includes multiple XNOR gates and AND gates. The first input terminal of each XNOR gate is a first input terminal of the digital comparison circuit, the second input terminal of each XNOR gate is a second input terminal of the digital comparison circuit, the output terminal of each XNOR gate is connected to the input terminal of the AND gate, and the output terminal of the AND gate is the output terminal of the digital comparison circuit.

[0014] Optionally, the feedback adjustment module includes an error feedback unit and an adjustment unit. The error feedback unit includes multiple feedback input terminals, a first reference input terminal corresponding to each feedback input terminal, a branch error output terminal corresponding to each feedback input terminal, and a total error output terminal. Each feedback input terminal is connected to the output terminal of the corresponding output branch. Each first reference input terminal is used to connect to the corresponding first reference voltage. Each branch error output terminal is used to output the branch error corresponding to the corresponding output branch. The total error output terminal is used to output the total error. The adjustment unit includes a data acquisition input terminal, a total error input terminal, and an adjustment output terminal. The data acquisition input terminal is connected to the output terminal of the current acquisition module. The total error input terminal is connected to the total error output terminal. The adjustment output terminal is connected to the control terminal of each main switch in the main switch module through the second drive module to output an adjustment signal to the main switch module.

[0015] Optionally, the error feedback unit includes multiple first amplifier circuits and summing circuits. The first input terminal and the second input terminal of each first amplifier circuit correspond to a feedback input terminal and a first reference input terminal corresponding to the feedback input terminal, respectively. The output terminal of each first amplifier circuit is connected to the input terminal of the summing circuit. The output terminal of each first amplifier circuit is the error output terminal of each branch, and the output terminal of the summing circuit is the total error output terminal.

[0016] Optionally, the adjustment unit includes a second comparator, wherein the first input terminal, the second input terminal, and the output terminal of the second comparator are, in sequence, a data acquisition input terminal, a total error input terminal, and an adjustment output terminal; or, the adjustment unit includes a second amplifier circuit, a signal generation circuit, a third comparator, and a fourth comparator, wherein the first input terminal and the second input terminal of the second amplifier circuit are, in sequence, a data acquisition input terminal and a total error input terminal, the output terminal of the second amplifier circuit is connected to the first input terminal of the third comparator, the output terminal of the signal generation circuit is connected to the second input terminal of the third comparator and the first input terminal of the fourth comparator, the output terminal of the third comparator is the adjustment output terminal, the second input terminal of the fourth comparator is used to connect to a second reference voltage, and the output terminal of the fourth comparator is connected to the configuration terminal of the signal generation circuit.

[0017] Optionally, the main switch module includes a first main switch and a second main switch. The first terminal of the first main switch is used to connect to the power supply. The second terminal of the first main switch is connected to the first terminal of the second main switch and the first terminal of the inductor. The second terminal of the second main switch is grounded. The second terminal of the inductor is connected to the first terminal of each output switch. The second terminal of each output switch is the output terminal of the corresponding output branch.

[0018] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a power supply device, the power supply device comprising: a power supply for providing power supply voltage; a single-inductor multi-output voltage converter as described above, wherein the input terminal of the single-inductor multi-output voltage converter is connected to the power supply, and the multiple output terminals of the single-inductor multi-output voltage converter are used to provide multiple output voltages; and multiple loads, wherein the power supply terminal of each load is respectively connected to one output terminal of the single-inductor multi-output voltage converter.

[0019] The above scheme, a single-inductor multi-output voltage converter, includes a voltage conversion topology, a current acquisition module, a feedback adjustment module, and a branch selection module. The voltage conversion topology includes a main switch module, an inductor, and multiple output branches. Each output branch includes an output switch and provides a corresponding output voltage. The input terminal of the current acquisition module is connected to the inductor to acquire the inductor current. The feedback adjustment module is connected to the output terminal of the current acquisition module, each output branch, and the main switch module. The feedback adjustment module is configured to input the corresponding output voltage and a first reference voltage for each output branch, and output the corresponding branch error for each output branch. It also outputs an adjustment signal corresponding to the inductor current and the total error to the main switch module to adjust the inductor current. The branch selection module is connected to the feedback adjustment module and to the control terminal of each output switch. The branch selection module is configured to sequentially activate each output switch. In this method, since the total error is the sum of the errors of each branch, and the conduction time of the output switch of each output branch is proportional to the corresponding branch error, the duty cycle of each output branch can be calculated as the ratio of the corresponding branch error to the total error. Furthermore, since the total error reflects the total demand current of all output branches, and the average inductor current always remains consistent with the total demand current of all output branches, the average inductor current is also proportional to the total error. Therefore, the average current of each output branch (i.e., the product of the duty cycle of each output branch and the average inductor current) is only related to the branch error of that corresponding output branch and is independent of the branch errors of other output branches. When the load of one output branch changes, it only affects the branch error of that output branch and does not affect the branch errors of other output branches. Therefore, the average current and average voltage of other output branches will not change, thus avoiding intermodulation problems and improving the performance of the single-inductor multi-output voltage converter. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the single-inductor multi-output voltage converter provided in this application;

[0021] Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the single-inductor multi-output voltage converter provided in this application;

[0022] Figure 3 This is a schematic diagram of the circuit structure of one embodiment of the error feedback unit provided in this application;

[0023] Figure 4 This is a schematic diagram of the circuit structure of one embodiment of the adjustment unit provided in this application;

[0024] Figure 5 This is a circuit structure diagram of another embodiment of the adjustment unit provided in this application;

[0025] Figure 6 This is a schematic diagram of the circuit structure of one embodiment of the branch selection module provided in this application;

[0026] Figure 7 This is a circuit structure diagram of another embodiment of the branch selection module provided in this application;

[0027] Figure 8 This is a schematic diagram of the loop waveform of the single-inductor multi-output voltage converter provided in this application;

[0028] Figure 9 This is a schematic diagram of an embodiment of the power supply device provided in this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The term "multiple" in this application means at least two, such as two, three, etc. Furthermore, the terms "first," "second," etc., in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the single-inductor multi-output voltage converter provided in this application. Figure 1 As shown, the single-inductor multi-output voltage converter includes a voltage conversion topology 10, a current acquisition module 20, a feedback adjustment module 30, and a branch selection module 40.

[0032] The voltage conversion topology 10 includes a main switch module 11, an inductor 12, and multiple output branches 13. The number of output branches 13 is at least two, each output branch 13 includes an output switch, and each output branch 13 is used to provide a corresponding output voltage. Specifically, the voltage conversion topology 10 includes n output branches 13. The first output branch 13 includes an output switch S1, and the corresponding output voltage is V1; the nth output branch 13 includes an output switch Sn, and the corresponding output voltage is Vn. Here, n is an integer greater than 1. The output terminals of each output branch 13 are used to connect to the power supply terminals of different loads (…). Figure 1 The connections of the loads (not shown) are used to supply power to different loads.

[0033] The voltage conversion topology 10 can be a buck topology, used to reduce the input power supply voltage (VCC) to different output voltages. In the buck topology, the main switch module 11 includes a first main switch 11a and a second main switch 11b. The first terminal of the first main switch 11a is used to connect to the power supply (VCC). Figure 1 (The power supply is not shown in the diagram) is connected to the input power supply voltage. The second terminal of the first main switch 11a is connected to the first terminal of the second main switch 11b and the first terminal of the inductor 12. The second terminal of the second main switch 11b is grounded. The second terminal of the inductor 12 is connected to the first terminal of each output switch. The second terminal of each output switch is the output terminal of the corresponding output branch 13. The on / off logic of the first main switch 11a and the second main switch 11b is opposite. Specifically, when the first main switch 11a is configured to be in the on state, the second main switch 11b is configured to be in the off state; when the first main switch 11a is configured to be in the off state, the second main switch 11b is configured to be in the on state.

[0034] For example, the first main switch 11a is a PMOS transistor, the second main switch 11b is an NMOS transistor, and all output switches are NMOS transistors.

[0035] It should be noted that this embodiment only uses a buck converter topology 10 as an example. In other embodiments, the voltage conversion topology 10 can be a boost converter topology, used to boost the input power supply voltage to different levels of output voltage; or, the voltage conversion topology 10 can be a buck-boost converter topology, used to simultaneously provide at least one output voltage lower than the power supply voltage and at least one output voltage higher than the power supply voltage. The specific circuit structures of the boost converter topology and the buck-boost converter topology can be found in the prior art and will not be explained further here.

[0036] The input terminal of the current acquisition module 20 is connected to the inductor 12 for acquiring the inductor current. For example, the input terminal of the current acquisition module 20 is connected to the first terminal of the inductor 12. It should be noted that the current acquisition module 20 can directly acquire the inductor current. Alternatively, the current acquisition module 20 outputs an acquisition voltage, the magnitude of which can indirectly characterize the magnitude of the inductor current. The specific implementation of the current acquisition module 20 can be found in existing technology and will not be explained further here.

[0037] The feedback adjustment module 30 is connected to the output terminal of the current acquisition module 20, each output branch 13, and the main switch module 11. Specifically, the feedback adjustment module 30 is connected to the second terminal of the output switch in each output branch 13. Figure 1(The connection lines between the feedback adjustment module 30 and the second terminals of each output switch are omitted.) Furthermore, to ensure the correct configuration logic of each main switch in the main switch module 11 and to improve the driving capability of each main switch in the main switch module 11, the feedback adjustment module 30 is further connected to the control terminals of each main switch in the main switch module 11 through the second drive module 60.

[0038] The feedback adjustment module 30 is configured to input the output voltage and the first reference voltage corresponding to each output branch 13, and output the branch error corresponding to each output branch 13. Specifically, the output voltage, the first reference voltage, and the branch error corresponding to the first output branch 13 are V1, Vref1, and EA1, respectively; the output voltage, the first reference voltage, and the branch error corresponding to the nth output branch 13 are Vn, Vrefn, and EAn, respectively. The branch error of the output branch 13 can reflect the deviation between the corresponding output voltage and the corresponding first reference voltage, and can also reflect the required current of the output branch 13.

[0039] The feedback adjustment module 30 is also configured to output an adjustment signal corresponding to the inductor current and the total error to the main switch module 11 to adjust the inductor current. The total error is the sum of the errors of each branch, and the total error can reflect the total demand current of all output branches 13.

[0040] Branch selection module 40 is connected to feedback adjustment module 30 and to the control terminals of each output switch. Specifically, branch selection module 40 is connected to the error output terminals of each branch of feedback adjustment module 30. Furthermore, to ensure the correct configuration logic of each output switch and to improve the driving capability of the output switches, branch selection module 40 is further connected to the control terminals of each output switch through first drive module 50. Figure 1 The connection lines between the output terminal of the first drive module 50 and the control terminals of each output switch are omitted.

[0041] The branch selection module 40 is configured to sequentially turn on each output switch. Only one output switch is turned on at a time, and the on-time of each output switch is proportional to the branch error of the corresponding output branch 13. Specifically, the on-time of output switch Sn in the first output branch 13 is proportional to the branch error EA1; the on-time of output switch Sn in the nth output branch 13 is proportional to the branch error EAN.

[0042] In this embodiment, the single-inductor multi-output voltage converter includes a voltage conversion topology, a current acquisition module, a feedback adjustment module, and a branch selection module. The voltage conversion topology includes a main switch module, an inductor, and multiple output branches. Each output branch includes an output switch and is used to provide a corresponding output voltage. The input terminal of the current acquisition module is connected to the inductor to acquire the inductor current. The feedback adjustment module is connected to the output terminal of the current acquisition module, each output branch, and the main switch module. The feedback adjustment module is configured to input the output voltage and a first reference voltage corresponding to each output branch, output the branch error corresponding to each output branch, and output an adjustment signal corresponding to the inductor current and the total error to the main switch module to adjust the inductor current. The branch selection module is connected to the feedback adjustment module and to the control terminal of each output switch. The branch selection module is configured to sequentially turn on each output switch. In this method, since the total error is the sum of the errors of each branch, and the conduction time of the output switch of each output branch is proportional to the corresponding branch error, the duty cycle of each output branch can be calculated as the ratio of the corresponding branch error to the total error. Furthermore, since the total error reflects the total demand current of all output branches, and the average inductor current always remains consistent with the total demand current of all output branches, the average inductor current is also proportional to the total error. Therefore, the average current of each output branch (i.e., the product of the duty cycle of each output branch and the average inductor current) is only related to the branch error of that corresponding output branch and is independent of the branch errors of other output branches. When the load of one output branch changes, it only affects the branch error of that output branch and does not affect the branch errors of other output branches. Therefore, the average current and average voltage of other output branches will not change, thus avoiding intermodulation problems and improving the performance of the single-inductor multi-output voltage converter.

[0043] Please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the single-inductor multi-output voltage converter provided in this application. Figure 2 As shown, the single-inductor multi-output voltage converter includes a voltage conversion topology 10, a current acquisition module 20, a feedback adjustment module 30, a branch selection module 40, a first drive module 50, and a second drive module 60.

[0044] Figure 2 In the voltage conversion topology 10, a main switch module 11, an inductor 12, and multiple output branches 13 are included. The output terminals of each output branch 13 are respectively used to connect to the power supply terminals of different loads. Figure 2 (The connections of each load are not shown in the diagram.) Optionally, the output terminal of each output branch 13 is also used to connect to the first terminal of a capacitor and to the input terminal of a current source, and the second terminal of each first capacitor and the second terminal of each current source are grounded.

[0045] Figure 2 In the middle, the feedback adjustment module 30 further includes an error feedback unit 31 and an adjustment unit 32.

[0046] The error feedback unit 31 includes multiple feedback input terminals, a first reference input terminal corresponding to each feedback input terminal, a branch error output terminal corresponding to each feedback input terminal, and a total error output terminal. Each feedback input terminal is connected to the output terminal of the corresponding output branch 13 to input the output voltage (corresponding to V1 to Vn) of each output branch 13. Each first reference input terminal is used to connect to the corresponding first reference voltage (corresponding to input Vref1 to Vrefn). Each branch error output terminal is used to output the branch error corresponding to the corresponding output branch 13 (corresponding to output EA1 to EAn). The total error output terminal is used to output the total error (corresponding to output EASUM).

[0047] In some implementations, each first reference voltage can be designed according to the voltage required by the corresponding output branch 13. For example, the first reference voltage can be provided to each output branch 13 through different reference voltage sources. Alternatively, the first reference voltage corresponding to each output branch 13 can be obtained by dividing the voltage provided by the same reference voltage source.

[0048] In one embodiment, the error feedback unit 31 can be implemented by an amplifier circuit and a summing circuit 312.

[0049] Figure 3 This is a schematic diagram of the circuit structure of one embodiment of the error feedback unit provided in this application. Figure 3 As shown, the error feedback unit 31 includes a plurality of first amplifier circuits 311 (the first first amplifier circuit 311 to the nth first amplifier circuit 311) and a summing circuit 312.

[0050] Each first amplifier circuit 311 has a first input terminal and a second input terminal corresponding to a feedback input terminal and a first reference input terminal corresponding to the feedback input terminal, respectively. The output terminal of each first amplifier circuit 311 is the error output terminal of each branch. Each first amplifier circuit 311 is used to amplify the difference between the output voltage of the corresponding input and the first reference voltage of the corresponding input to obtain the corresponding branch error.

[0051] The input terminal of the summing circuit 312 is connected to the output terminal of each of the first amplifier circuits 311, and the output terminal of the summing circuit 312 is the total error output terminal. The summing circuit 312 is used to add the branch errors of all output branches 13 to obtain the total error.

[0052] Figure 2In this configuration, the adjustment unit 32 includes a data acquisition input terminal, a total error input terminal, and an adjustment output terminal. The data acquisition input terminal is connected to the output terminal of the current acquisition module 20, the total error input terminal is connected to the total error output terminal, and the adjustment output terminal is connected to the control terminals of each main switch in the main switch module 11 via the second drive module 60 to output adjustment signals to the main switch module 11.

[0053] In one embodiment, the adjustment unit 32 adjusts the inductor current by peak current mode control (i.e., comparing the peak inductor current with the total demand current of all output branches 13).

[0054] Figure 4 This is a schematic diagram of the circuit structure of one embodiment of the adjustment unit provided in this application. Figure 4 As shown, the adjustment unit 32 includes a second comparator 321. The first input terminal, the second input terminal, and the output terminal of the second comparator 321 are, respectively, the acquisition input terminal, the total error input terminal, and the adjustment output terminal of the adjustment unit 32.

[0055] In this embodiment, the first input terminal of the second comparator 321 is a positive input terminal and receives the inductor current, while the second input terminal is a negative input terminal and receives the total error. When the inductor current is less than the total error, the second comparator 321 outputs a low-level adjustment signal, causing the first main switch 11a to turn on and the second main switch 11b to turn off, increasing the inductor current. When the inductor current increases to the total error, the second comparator 321 outputs a high-level adjustment signal, causing the first main switch 11a to turn off and the second main switch 11b to turn on, decreasing the inductor current. Therefore, the inductor current is controlled near the total error, and the average current of inductor 12 remains consistent with the total error.

[0056] It should be noted that in this embodiment, since the moment the first main switch 11a is turned off and the second main switch 11b is turned on is exactly when the inductor current equals the total error, and the inductor current decreases when the first main switch 11a is turned off, the inductor current will be less than the total error at the next instant, causing the level of the output adjustment signal to flip again, and the second main switch 11b is instantly configured to be off again. To avoid this phenomenon, the second main switch 11b can be configured to be turned on for a set time before being turned off. The length of the set time can be designed according to actual needs.

[0057] In another embodiment, the adjustment unit 32 adjusts the inductor current through valley current mode control (i.e., the minimum current of the comparison inductor 12 is equal to the total demand current of all output branches 13). In this embodiment, the first input terminal of the second comparator 321 is a negative input terminal and receives the inductor current, while the second input terminal of the second comparator 321 is a positive input terminal and receives the total error. The specific principle is similar to the previous embodiment and will not be explained in detail here.

[0058] In another embodiment, the adjustment unit 32 adjusts the inductor current by means of average current mode control (i.e., comparing the average current of inductor 12 with the total demand current of all output branches 13).

[0059] Figure 5 This is a circuit structure diagram of another embodiment of the adjustment unit provided in this application. For example... Figure 5 As shown, the adjustment unit 32 includes a second amplifier circuit 322, a signal generation circuit 323, a third comparator 324, and a fourth comparator 325. The first and second input terminals of the second amplifier circuit 322 are, respectively, the acquisition input terminal and the total error input terminal of the adjustment unit 32. The output terminal of the second amplifier circuit 322 is connected to the first input terminal (i.e., the positive input terminal) of the third comparator 324. The output terminal of the signal generation circuit 323 is connected to the second input terminal (i.e., the negative input terminal) of the third comparator 324 and the first input terminal (i.e., the positive input terminal) of the fourth comparator 325. The output terminal of the third comparator 324 is the adjustment output terminal of the adjustment unit 32. The second input terminal (i.e., the negative input terminal) of the fourth comparator 325 is used to connect to the second reference voltage. The output terminal of the fourth comparator 325 is connected to the configuration terminal of the signal generation circuit 323.

[0060] The second amplifier circuit 322 is used to amplify the difference between the input inductor current and the total error, and output the amplified error.

[0061] The signal generation circuit 323 generates a second signal, which is a sawtooth wave signal. The signal generation circuit 323 may further include a second power supply 323a, a second capacitor 323b, and a second configuration switch 323c. The first terminal of the second power supply 323a is connected to the first terminal of the second capacitor 323b and the first terminal of the second configuration switch 323c. The second terminal of the second capacitor 323b and the second terminal of the second configuration switch 323c are grounded. The control terminal of the second configuration switch 323c is the configuration terminal of the signal generation circuit 323. For example, the second power supply 323a is a current source. When the second configuration switch 323c is off, the second power supply 323a charges the second capacitor 323b, causing the signal value of the second signal to increase; when the second configuration switch 323c is on, the second capacitor 323b discharges, causing the signal value of the second signal to decrease. In this way, a sawtooth wave form of the second signal can be generated.

[0062] The fourth comparator 325 is used to configure the second configuration switch 323c in the signal generation circuit 323 to be turned on and off. Specifically, the fourth comparator 325 compares the signal value of the second signal with the second reference voltage. When the signal value of the second signal is less than the second reference voltage, the fourth comparator 325 outputs a low-level signal, causing the second configuration switch 323c to be turned off. When the signal value of the second signal reaches the second reference voltage, the fourth comparator 325 outputs a high-level signal, causing the second configuration switch 323c to be turned on. For example, the second reference voltage can be provided by an additional reference voltage source.

[0063] The third comparator 324 is used to compare the signal value of the second signal with the amplification error output by the second amplifier circuit 322. When the signal value of the second signal is less than the amplification error, the third comparator 324 outputs a low-level adjustment signal. When the signal value of the second signal reaches the amplification error, the third comparator 324 outputs a high-level adjustment signal.

[0064] Please refer to it again. Figure 2 , Figure 2 In the single-inductor multi-output voltage converter shown, the branch selection module 40 further includes a signal providing unit 41, multiple selection switches (K1~Kn), a comparison unit 42, and a selection unit 43.

[0065] The signal providing unit 41 has its output connected to the first input of the comparison unit 42, and is configured to provide a first signal. The first terminal of each gating switch is connected to a branch error output terminal, and the second terminal of each gating switch is connected to the second input of the comparison unit 42. The output of the comparison unit 42 is connected to the configuration terminal of the signal providing unit 41. The gating unit 43 includes an input terminal and multiple output terminals. The input terminal of the gating unit 43 is connected to the output of the comparison unit 42. Each output terminal of the gating unit 43 is connected to the control terminal of an output switch via the first driving module 50. Each output terminal of the gating unit 43 is also connected to the control terminal of a corresponding gating switch. Figure 2 The connection lines between the output terminal of the gating unit 43 and the control terminals of each gating switch are omitted.

[0066] It should be noted that, for ease of description later, each output terminal of the gating unit 43 is defined as a switch combination by connecting an output switch and a gating switch respectively. Specifically, output switch S1 and gating switch K1 are considered as one switch combination, and output switch Sn and gating switch Kn are considered as another switch combination.

[0067] In this embodiment, when the current switch combination (such as output switch S1 and gating switch K1) is turned on, the signal value of the first signal increases from a preset value. The comparison unit 42 compares the signal value of the first signal with the current branch error, and outputs a switching signal when the signal value of the first signal increases to the current branch error. The switching signal configures the signal providing unit 41 so that the signal value of the first signal generated by the signal providing unit 41 decreases to the preset value. The switching signal also configures the gating unit 43 to turn off the current switch combination and turn on the next switch combination (such as output switch S2 and gating switch K2). In this way, each output switch can be turned on sequentially, and the on-time of each output switch is proportional to the corresponding branch error. For example, the preset value is 0.

[0068] In one embodiment, a sawtooth wave signal is generated, and the signal value of the sawtooth wave signal is compared with the branch error of the current output branch. When the signal value of the sawtooth wave signal reaches the branch error of the current output branch, the branch error of the next output branch is switched and the output switch of the next output branch is turned on. This process is repeated so that the on-time of each output switch is proportional to the corresponding branch error.

[0069] Figure 6 This is a schematic diagram of the circuit structure of one embodiment of the branch selection module 40 provided in this application. Figure 6 In the branch selection module 40 shown, the first signal provided by the signal providing unit 41 is a sawtooth wave signal. The signal providing unit 41 further includes a first power supply 411, a first capacitor 412, and a first configuration switch 413. The first terminal of the first capacitor 412 is connected to the output terminal of the first power supply 411 and the first terminal of the first configuration switch 413. The second terminal of the first capacitor 412 and the second terminal of the first configuration switch 413 are both grounded. The first terminal of the first capacitor 412 is the output terminal of the signal providing unit 41, and the control terminal of the first configuration switch 413 is the configuration terminal of the signal providing unit 41. For example, the first power supply 411 is a current source. When the first configuration switch 413 is off, the first power supply 411 charges the first capacitor 412, causing the signal value of the first signal to increase; when the second configuration switch is on, the first capacitor 412 discharges, causing the signal value of the first signal to decrease. In this way, a sawtooth wave form of the first signal can be generated.

[0070] The comparison unit 42 further includes a first comparator 421, and the first input terminal (i.e., the positive input terminal of the first comparator 421), the second input terminal (i.e., the negative input terminal of the first comparator 421) and the output terminal of the first comparator 421 are the first input terminal, the second input terminal and the output terminal of the comparison unit 42, respectively.

[0071] The gating unit 43 further includes a plurality of first flip-flops 431. The data output terminal of the i-th first flip-flop 431 is connected to the data input terminal of the (i+1)-th first flip-flop 431, and the data output terminal of the last first flip-flop 431 is connected to the data input terminal of the first first flip-flop 431. The clock input terminal of each first flip-flop 431 is connected and serves as the input terminal of the gating unit 43, and the data output terminal of each first flip-flop 431 is an output terminal of the gating unit 43. Where i is greater than or equal to 1, and i is less than the total number of the plurality of first flip-flops 431.

[0072] The data output terminal of each first trigger 431 is connected to the control terminal of an output switch and the control terminal of a corresponding gating switch via the first driving module 50. Specifically, the data output terminal of the first first trigger 431 is connected to the control terminal of output switch S1 and the control terminal of gating switch K1 via the first driving module 50; the data output terminal of the nth first trigger 431 is connected to the control terminal of output switch Sn and the control terminal of gating switch Kn via the first driving module 50. It should be noted that... Figure 6 The connection lines between each first trigger 431 and the corresponding output switch and gating switch are omitted.

[0073] For example, each of the first flip-flops 431 is a D flip-flop, and the trigger type of each of the first flip-flops 431 is clock rising edge triggered. The data input terminal, data output terminal, and clock input terminal of each of the first flip-flops 431 correspond to each other in sequence. Figure 6 The D, Q, and clk terminals in the code.

[0074] The working principle of the branch selection module 40 in this embodiment is briefly explained below:

[0075] Assuming that upon initial power-up, the first configuration switch 413 is off, the data output of the first first flip-flop 431 is high (this can be achieved by setting the data output of the first first flip-flop 431 to high level via its set input), and the data outputs of the other first flip-flops 431 are low. At this time, the output switch S1 and the gating switch K1 are on, the branch error EA1 is connected to the first comparator 421, and the first power supply 411 charges the first capacitor 412, causing the sawtooth wave signal value to increase from 0. When the sawtooth wave signal value is less than the branch error EA1, the output of the first comparator 421 is low. When the sawtooth wave signal value reaches the branch error EA1, the output of the first comparator 421 flips to high level (i.e., generating the aforementioned switching signal). When the output of the first comparator 421 flips to a high level, the first configuration switch 413 is turned on, and the first capacitor 412 discharges, causing the sawtooth wave signal value to drop to 0 in a very short time. Then, because the sawtooth wave signal value is less than EA1, the output of the first comparator 421 flips to a low level again, and the first configuration switch 413 is configured to be turned off. Furthermore, the flipping of the output of the first comparator 421 to a high level simultaneously generates a valid rising edge of the clock, causing the data output of the first first flip-flop 431 to go low and the data output of the second first flip-flop 431 to go high. The data outputs of the other first flip-flops 431, except for the first and second first flip-flops, remain low. This turns off the output switch S1 and the gating switch K1, and turns on the output switch S2 and the gating switch K2, connecting the switching branch error EA2 to the first comparator 421. Afterwards, the sawtooth wave signal starts increasing again from 0. When the signal value of the sawtooth wave signal reaches EA2, the output of the first comparator 421 flips to a high level again, the first configuration switch 413 turns on, the first capacitor 412 discharges, and the signal value of the sawtooth wave signal drops to 0 again. The generated valid rising edge of the clock causes the output of the second first flip-flop 431 to go low, the output of the third first flip-flop 431 to go high, and the data outputs of the other first flip-flops 431 (excluding the second and third flip-flops) remain low. This turns off output switch S2 and gating switch K2, and turns on output switch S3 and gating switch K3, connecting the switching branch error EA3 to the first comparator 421. This process continues, with each output switch turning on sequentially. The on-time of each output switch is the time it takes for the sawtooth wave signal value to increase from 0 to the corresponding branch error, making the on-time of each output switch proportional to the corresponding branch error.

[0076] In another embodiment, by performing the same clock count on the branch error of the current output branch, when the clock count reaches the branch error of the current output branch, the branch error of the next output branch is switched and the output switch of the next output branch is turned on, and so on, so that the on-time of each output switch is proportional to the corresponding branch error.

[0077] Figure 7 This is a circuit structure diagram of another embodiment of the branch selection module 40 provided in this application. Figure 7 In the branch selection module 40 shown, the signal providing unit 41 has multiple output terminals. The comparison unit 42 includes an analog-to-digital converter circuit 422 and a digital comparison circuit 423. The analog-to-digital converter circuit 422 includes an input terminal and multiple output terminals. The digital comparison circuit 423 includes multiple first input terminals (corresponding to inputs A1 to An) and multiple second input terminals (corresponding to inputs B1 to Bn). Each output terminal of the signal providing unit 41 is connected to one of the first input terminals of the digital comparison circuit 423, and each output terminal of the analog-to-digital converter circuit 422 is connected to one of the second input terminals of the digital comparison circuit 423. The multiple first input terminals of the digital comparison circuit 423, the input terminals of the analog-to-digital converter circuit 422, and the output terminals of the digital comparison circuit 423 are, in sequence, the first input terminal, the second input terminal, and the output terminal of the comparison unit 422.

[0078] The signal providing unit 41 is used to count the clock, and the first signal generated by the signal providing unit 41 is a digital signal. The signal value output by each output terminal of the signal providing unit 41 corresponds to one bit of the clock count.

[0079] Figure 7 In this circuit, the signal providing unit 41 further includes multiple trigger circuits 414. The output terminal of the j-th trigger circuit 414 is connected to the input terminal of the (j+1)-th trigger circuit 414. The input terminal of the first trigger circuit 414 is used to input a clock signal. Here, j is greater than or equal to 1 and less than the total number of trigger circuits 414. The clock signal can be provided by a clock signal source. For each trigger circuit 414, the trigger circuit 414 further includes a second flip-flop 414a and an inverter 414b. The data output terminal of the second flip-flop 414a is connected to the input terminal of the inverter 414b, and the output terminal of the inverter 414b is connected to the data input terminal of the second flip-flop 414a. The clock input terminal of the second flip-flop 414a and the output terminal of the inverter 414b are, respectively, the input and output terminals of the trigger circuit 414. The data output terminal of the second flip-flop 414a is an output terminal of the signal providing unit 41, and the reset terminal of each second flip-flop 414a is the configuration terminal of the signal providing unit 41.

[0080] For example, each of the second flip-flops 414a is a D flip-flop, and the trigger type of each of the second flip-flops 414a is clock rising edge triggered. The data input terminal, data output terminal, and clock input terminal of each of the second flip-flops 414a correspond to each other in sequence. Figure 7 The D, Q, and clk terminals in the code.

[0081] The following example, using the signal providing unit 41 comprising three trigger circuits 414 (corresponding to three second flip-flops 414a and three inverters 414b), briefly illustrates the principle of clock counting by the signal providing unit 41:

[0082] Assuming that upon initial power-up, the data outputs of all second flip-flops 414a are low, and correspondingly, the outputs of all inverters 414b are high, the clock count output by the signal providing unit 41 can be represented as 000. When the first rising edge of the clock signal arrives, the data output of the first second flip-flop 414a will become high, the output of the first inverter 414b will become low, the data outputs of the other second flip-flops 414a will remain low, and the outputs of the other inverters 414b will remain high, the clock count output by the signal providing unit 41 can be represented as 001. Furthermore, when the second rising edge of the clock signal arrives, the data output of the first second flip-flop 414a will become low, and the output of the first inverter 414b will become high. At this time, the output of the first inverter 414b is equivalent to generating a valid rising edge of the clock, causing the data output of the second second flip-flop 414a to become high, the output of the second inverter 414b to become low, the data output of the third second flip-flop 414a to remain low, and the output of the third inverter 414b to remain high. At this time, the clock count output by the signal providing unit 41 can be represented as 010. Furthermore, when the third rising edge of the clock signal arrives, the data output of the first second flip-flop 414a goes high, the output of the first inverter 414b goes low, the data output of the second second flip-flop 414a remains high, the output of the second inverter 414b remains low, the data output of the third second flip-flop 414a remains low, and the output of the third inverter 414b remains high. At this time, the clock count output by the signal providing unit 41 can be represented as 110. Similarly, the signal providing unit 41 can implement clock counting within the range of 000 to 111.

[0083] The analog-to-digital converter circuit 422 is used to sample the input branch error, and the signal value output by each output terminal of the analog-to-digital converter circuit 422 corresponds to one bit of the branch error sample value.

[0084] The digital comparator circuit 423 is used to compare the clock count output by the signal providing unit 41 with the branch error sampling value output by the analog-to-digital converter circuit 422, and outputs a switching signal when the clock count reaches the branch error sampling value.

[0085] Figure 7 In the digital comparison circuit 423, multiple XNOR gates 423a and AND gates 423b are further included. The first input terminal of each XNOR gate 423a is a first input terminal of the digital comparison circuit 423, and the second input terminal of each XNOR gate 423a is a second input terminal of the digital comparison circuit 423. The output terminal of each XNOR gate 423a is connected to the input terminal of the AND gate 423b, and the output terminal of the AND gate 423b is the output terminal of the digital comparison circuit 423. The principle of the XNOR gate 423a is: when the inputs are the same, the output is high; when the inputs are different, the output is low. The principle of the AND gate 423b is: when all inputs are high, the output is high; when at least one input is low, the output is low. It can be understood that when the clock count output by the signal providing unit 41 does not reach the branch error sampling value output by the analog-to-digital conversion circuit 422, at least one of the outputs of each XNOR gate 423a will be low, causing the AND gate 423b to output a low level. When the clock count output by the signal providing unit 41 is the same as the branch error sampling value output by the analog-to-digital conversion circuit 422, the outputs of each XOR gate 423a are all high level, causing the AND gate 423b to output a high level (i.e., generating a switching signal).

[0086] Figure 7 In the middle, the gating unit 43 further includes a plurality of first flip-flops 431, which can be referred to in detail. Figure 6 The details of the embodiments shown are omitted here.

[0087] The working principle of the branch selection module 40 in this embodiment is briefly explained below:

[0088] Assuming that upon initial power-up, the data output of the first flip-flop 431 is high (this can be achieved by setting the data output of the first flip-flop 431 to high level), while the data outputs of the other first flip-flops 431 are low. At this time, output switch S1 and gating switch K1 are turned on, the branch error EA1 is connected, the analog-to-digital converter circuit 422 outputs the sampled value of the branch error EA1, and the signal providing unit 41 begins counting the input clock signal. When the clock count is less than the sampled value of the branch error EA1, the digital comparator circuit 423 outputs a low level. When the clock count reaches the sampled value of the branch error EA1, the output of the digital comparator circuit 423 flips to high level (i.e., generates the aforementioned switching signal). When the output of the digital comparator circuit 423 flips to high level, it can reset the data outputs of each second flip-flop 414a in the signal providing unit 41, causing the data outputs of each second flip-flop 414a to become low, and the output of the digital comparator circuit 423 to become low again. Furthermore, as the output of the digital comparator circuit 423 flips to a high level, a valid rising edge of the clock is generated, causing the data output of the first flip-flop 431 to become low and the data output of the second flip-flop 431 to become high. The data outputs of the other flip-flops 431 besides the first and second flip-flops remain low, thereby turning off the output switch S1 and the gating switch K1, and turning on the output switch S2 and the gating switch K2, thus connecting the switching branch error EA2. Afterwards, the signal providing unit 41 restarts counting the input clock signal. The analog-to-digital converter circuit 422 outputs the sampled value of the branch error EA2. The digital comparator circuit 423 compares the new clock count with the sampled value of the branch error EA2. When the new clock count reaches the sampled value of the branch error EA2, the output of the digital comparator circuit 423 flips to a high level again, and the signal providing unit 41 is reset again. At the same time, the output of the second first flip-flop 431 becomes low, the output of the third first flip-flop 431 becomes high, and the data outputs of the other first flip-flops 431 except for the second and third first flip-flops remain low. As a result, the output switch S2 and the gating switch K2 are turned off, and the output switch S3 and the gating switch K3 are turned on, switching the branch error EA3 to the input. In this way, each output switch is turned on in sequence, and the on-time of each output switch is the time it takes for the clock count to reach the corresponding branch error from 0, so that the on-time of each output switch is proportional to the corresponding branch error.

[0089] Please see Figure 8 , Figure 8 This is a schematic diagram of the loop waveform of the single-inductor multi-output voltage converter provided in this application. Figure 8The following example illustrates the use of a single-inductor multi-output voltage converter, which includes two output branches, an adjustment unit that controls the adjustment of the inductor current in peak current mode, and a branch selection module 40 that sequentially matches the sawtooth wave signal with the branch error of each output branch. Figure 8 In this diagram, IL represents the inductor current, V1 and V2 represent the output voltages of the first and second output branches, respectively, EA1 and EA2 are the branch errors of the two output branches, EASUM represents the sum of EA1 and EA2 (i.e., the total error of the two output branches), and SAW represents the sawtooth wave signal. It should be noted that... Figure 8 The slope of the sawtooth wave signal is fixed. In other examples, the slope of the sawtooth wave signal can also vary. For example, the higher the supply voltage, the higher the slope of the sawtooth wave signal. As another example, the higher the inductor current, the higher the slope of the sawtooth wave signal.

[0090] Before IL reaches EASUM, the first main switch 11a is turned on, and IL continuously increases. After IL reaches EASUM, the second main switch 11b is turned on, and IL decreases. Therefore, IL will eventually be controlled near EASUM. Any change in load will affect the value of EASUM, and IL will change accordingly, as shown in the figure where EASUM increases and IL also increases. However, when the load changes, a change in one load only affects the branch error of the corresponding output branch, not the branch errors of other output branches. For example, at time t1, the load current of the second output branch increases (i.e., the load current jumps instantaneously), EA2 becomes higher while EA1 remains unchanged. This will cause the conduction time of the first output branch (the conduction time of the output switch in the first output branch) to remain unchanged, while the conduction time of the second output branch (the conduction time of the output switch in the second output branch) to become longer. Since the total period is the sum of the conduction time of the first output branch and the conduction time of the second output branch, the total period will increase as the conduction time of the second output branch increases. Therefore, although the conduction time of the first output branch remains unchanged, its duty cycle (i.e., the ratio of the conduction time of the first output branch to the total period) has decreased. At this time, the average current of inductor 12 also increases by the same proportion, so that the average current of the first output branch does not change, and thus the average voltage of the first output branch does not change, and therefore there is no intermodulation problem.

[0091] In related technologies, the inductor current (inductor energy) and the distribution relationship of each output branch in a single-inductor multi-output voltage converter will change. When the load of one output branch changes, the other output branches will be disturbed, resulting in unavoidable intermodulation. Furthermore, since all output branches of a single-inductor multi-output voltage converter share a single inductor, the output performance (including ripple, transient response, efficiency, etc.) of each output branch is inferior to that of a single-output converter. Therefore, the performance of a single-inductor multi-output voltage converter is relatively low.

[0092] In this embodiment, since the total error is the sum of the errors of each branch, and the conduction time of the output switch of each output branch is proportional to the corresponding branch error, the duty cycle of each output branch can be obtained as the ratio of the corresponding branch error to the total error (i.e., Dn = EAn / EASUM, where Dn, EAn, and EASUM represent the duty cycle of output branch n, the branch error of output branch n, and the total error of all output branches, respectively). Furthermore, since the total error reflects the total demand current of all output branches, and the average inductor current is always consistent with the total demand current of all output branches, the average inductor current is also proportional to the total error (i.e., EASUM = R*IL, where R is a proportionality coefficient). Therefore, the average current of each output branch (i.e., the product of the duty cycle of each output branch and the average inductor current, EAn / R) is only related to the branch error of the corresponding output branch and is independent of the branch errors of other output branches. When the load of one of the output branches changes, it only affects the branch error of that output branch and does not affect the branch errors of other output branches. Therefore, the average current and average voltage of other output branches will not change, thus avoiding intermodulation problems and improving the performance of the single-inductor multi-output voltage converter.

[0093] In this embodiment, the branch error of each output branch is not directly used to control the current of each output branch separately; that is, each output branch is not directly controlled in current mode. However, the branch error of each output branch controls the time when the inductor current is distributed to each output branch. By performing current mode control on the total inductor current and using a proportional distribution method to accurately distribute the current of each output branch, each output branch is equivalent to using current mode control, thereby making the performance of the single-inductor multi-output voltage converter close to that of a single-output converter.

[0094] In summary, the single-inductor multi-output voltage converter in this embodiment has performance close to that of a single-output converter, improved transient response speed, significantly suppressed intermodulation, and operates in continuous conduction mode, resulting in high load capacity and efficiency.

[0095] Please see Figure 9 , Figure 9This is a schematic diagram of an embodiment of the power supply device provided in this application. Figure 9 As shown, the power supply unit includes a power supply, a single-inductor multi-output voltage converter, and multiple loads. Figure 9 (Loads 1 to n in the load range).

[0096] The power supply provides the power voltage. The input of the single-inductor multi-output voltage converter is connected to the power supply, and its multiple outputs provide multiple output voltages. Each load's power supply is connected to one output of the single-inductor multi-output voltage converter.

[0097] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A single-inductor multiple-output voltage converter, characterized by, The single-inductor multi-output voltage converter includes: The voltage conversion topology includes a main switch module, an inductor, and multiple output branches. Each output branch includes an output switch, and each output branch is used to provide a corresponding output voltage. A current acquisition module, wherein the input terminal of the current acquisition module is connected to the inductor and is used to acquire the inductor current; A feedback adjustment module is connected to the output terminal of the current acquisition module, each of the output branches, and the main switch module. The feedback adjustment module is configured to input the output voltage and the first reference voltage corresponding to each of the output branches, output the branch error corresponding to each of the output branches, and output the adjustment signal corresponding to the inductor current and the total error to the main switch module to adjust the inductor current; wherein, the total error is the sum of the errors of each branch. A branch selection module is connected to the feedback adjustment module and to the control terminal of each of the output switches. The branch selection module is configured to sequentially turn on each of the output switches; wherein the conduction time of each output switch is proportional to the error of the corresponding branch.

2. The single-inductor multi-output voltage converter of claim 1, wherein, The feedback adjustment module includes branch error output terminals for outputting the errors of each branch; the branch gating module includes: A signal providing unit is configured to provide a first signal; Multiple gating switches, with the first terminal of each gating switch connected to one of the branch error output terminals; The comparison unit has a first input terminal connected to the output terminal of the signal providing unit, a second input terminal connected to the second terminal of each of the selection switches, and an output terminal connected to the configuration terminal of the signal providing unit. A gating unit includes an input terminal and multiple output terminals. The input terminal of the gating unit is connected to the output terminal of the comparison unit. Each output terminal of the gating unit is connected to the control terminal of an output switch through a first driving module. Each output terminal of the gating unit is also connected to the control terminal of a corresponding gating switch. The output switch and the gating switch connected to each output terminal of the gating unit respectively constitute a switch combination. When the current switch combination is turned on, the signal value of the first signal increases from a preset value. When the signal value of the first signal increases to the current branch error, the comparison unit outputs a switching signal, causing the signal value of the first signal to decrease to the preset value. The selection unit is configured to turn off the current switch combination and turn on the next switch combination.

3. The single-inductor multi-output voltage converter of claim 2, wherein, The gating unit includes multiple first flip-flops. The data output terminal of the i-th first flip-flop is connected to the data input terminal of the (i+1)-th first flip-flop. The data output terminal of the last first flip-flop is connected to the data input terminal of the first first flip-flop. The clock input terminal of each first flip-flop is connected and serves as the input terminal of the gating unit. The data output terminal of each first flip-flop is also an output terminal of the gating unit. Wherein, i is greater than or equal to 1.

4. The single-inductor multi-output voltage converter according to claim 2, characterized in that, The first signal is a sawtooth wave signal; and, The comparison unit includes a first comparator, and the first input terminal, the second input terminal, and the output terminal of the first comparator are, in sequence, the first input terminal, the second input terminal, and the output terminal of the comparison unit.

5. The single-inductor multi-output voltage converter of claim 4, wherein, The signal providing unit includes a first power supply, a first capacitor, and a first configuration switch. The first end of the first capacitor is connected to the output end of the first power supply and the first end of the first configuration switch. The second end of the first capacitor and the second end of the first configuration switch are both grounded. The first end of the first capacitor is the output end of the signal providing unit, and the control end of the first configuration switch is the configuration end of the signal providing unit.

6. The single-inductor multi-output voltage converter of claim 2, wherein, The signal providing unit has multiple output terminals, and the signal providing unit is used to count the clock, and the first signal is a digital signal; The comparison unit includes an analog-to-digital converter circuit and a digital comparison circuit. The analog-to-digital converter circuit includes an input terminal and multiple output terminals. The digital comparison circuit includes multiple first input terminals and multiple second input terminals. Each output terminal of the signal providing unit is connected to a first input terminal of the digital comparison circuit, and each output terminal of the analog-to-digital conversion circuit is connected to a second input terminal of the digital comparison circuit. The plurality of first input terminals of the digital comparison circuit, the input terminal of the analog-to-digital conversion circuit, and the output terminal of the digital comparison circuit are, in sequence, the first input terminal, the second input terminal, and the output terminal of the comparison unit.

7. The single-inductor multi-output voltage converter of claim 6, wherein, The signal providing unit includes multiple trigger circuits, the output terminal of the j-th trigger circuit is connected to the input terminal of the (j+1)-th trigger circuit, and the input terminal of the first trigger circuit is used to receive a clock signal; where j is greater than or equal to 1; For each of the aforementioned trigger circuits, the trigger circuit includes a second flip-flop and an inverter. The data output terminal of the second flip-flop is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the data input terminal of the second flip-flop. The clock input terminal of the second flip-flop and the output terminal of the inverter are, in sequence, the input terminal and the output terminal of the trigger circuit. The data output terminal of the second flip-flop is one output terminal of the signal providing unit. The reset terminal of each second flip-flop is the configuration terminal of the signal providing unit.

8. The single-inductor multi-output voltage converter of claim 6, wherein, The digital comparison circuit includes multiple XNOR gates and AND gates. The first input terminal of each XNOR gate is a first input terminal of the digital comparison circuit, and the second input terminal of each XNOR gate is a second input terminal of the digital comparison circuit. The output terminal of each XNOR gate is connected to the input terminal of the AND gate, and the output terminal of the AND gate is the output terminal of the digital comparison circuit.

9. The single-inductor multi-output voltage converter of claim 1, wherein, The feedback adjustment module includes an error feedback unit and an adjustment unit; The error feedback unit includes multiple feedback input terminals, a first reference input terminal corresponding to each feedback input terminal, a branch error output terminal corresponding to each feedback input terminal, and a total error output terminal. Each feedback input terminal is connected to the output terminal of the corresponding output branch. Each first reference input terminal is used to connect to the corresponding first reference voltage. Each branch error output terminal is used to output the branch error corresponding to the corresponding output branch. The total error output terminal is used to output the total error. The adjustment unit includes a data acquisition input terminal, a total error input terminal, and an adjustment output terminal. The data acquisition input terminal is connected to the output terminal of the current acquisition module, the total error input terminal is connected to the total error output terminal, and the adjustment output terminal is connected to the control terminal of each main switch in the main switch module through the second drive module to output the adjustment signal to the main switch module.

10. The single-inductor multi-output voltage converter of claim 9, wherein, The error feedback unit includes multiple first amplifier circuits and summing circuits. The first input terminal and the second input terminal of each first amplifier circuit correspond to a feedback input terminal and a first reference input terminal corresponding to the feedback input terminal. The output terminal of each first amplifier circuit is connected to the input terminal of the summing circuit. The output terminal of each first amplifier circuit is the error output terminal of each branch, and the output terminal of the summing circuit is the total error output terminal.

11. The single-inductor multi-output voltage converter according to claim 9, characterized in that, The adjustment unit includes a second comparator, wherein the first input terminal, the second input terminal, and the output terminal of the second comparator are, in sequence, the acquisition input terminal, the total error input terminal, and the adjustment output terminal; Alternatively, the adjustment unit includes a second amplifier circuit, a signal generation circuit, a third comparator, and a fourth comparator. The first and second input terminals of the second amplifier circuit are, in sequence, the acquisition input terminal and the total error input terminal. The output terminal of the second amplifier circuit is connected to the first input terminal of the third comparator. The output terminal of the signal generation circuit is connected to the second input terminal of the third comparator and the first input terminal of the fourth comparator. The output terminal of the third comparator is the adjustment output terminal. The second input terminal of the fourth comparator is used to connect to a second reference voltage. The output terminal of the fourth comparator is connected to the configuration terminal of the signal generation circuit.

12. The single-inductor multi-output voltage converter of claim 1, wherein, The main switch module includes a first main switch and a second main switch. The first end of the first main switch is used to connect to the power supply. The second end of the first main switch is connected to the first end of the second main switch and the first end of the inductor. The second end of the second main switch is grounded. The second end of the inductor is connected to the first end of each of the output switches. The second end of each of the output switches is the output end of the corresponding output branch.

13. A power supply device, characterized by comprising: The power supply device includes: Power supply, used to provide power voltage; The single-inductor multi-output voltage converter according to any one of claims 1 to 12, wherein the input terminal of the single-inductor multi-output voltage converter is connected to the power supply, and the plurality of output terminals of the single-inductor multi-output voltage converter are used to provide a plurality of output voltages; Multiple loads, each of which has its power supply terminal connected to one of the output terminals of the single-inductor multi-output voltage converter.

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