Switching control circuit and radio frequency device

Abstract

The embodiment of the application provides a kind of switch control circuit and radio frequency device, belong to electronic technical field.The switch control circuit and radio frequency device are detected by voltage detection circuit in real time the bias voltage that bias voltage generation circuit outputs, and by voltage regulating signal generation circuit when the detection signal that voltage detection circuit outputs represents that bias voltage does not satisfy preset condition in time output voltage regulating signal in active level state, so that bias voltage generation circuit adjusts bias voltage in time, and when bias voltage is switched from not satisfying preset condition to satisfying preset condition, the level state of the voltage regulating signal generated by voltage regulating signal generation circuit is not immediately switched to inactive level state, but is switched to inactive level state after preset time, so that the bias voltage generation circuit still continues to adjust bias voltage in the time period, so as to ensure that the condition for stabilizing bias voltage is to satisfy preset condition, effectively improve the working stability of switch.

Description

Technical Field

[0001] The embodiments in this application relate to the field of electronic technology, specifically to switch control circuits and radio frequency devices. Background Technology

[0002] As a crucial component of wireless communication systems, radio frequency (RF) switches allocate multiple RF channels during signal transmission and reception, enabling switching between different RF paths. They are an essential part of RF devices. In recent years, with the rapid development of wireless communication technology, the increasing market demand in fields such as mobile communication, and the continuous evolution of communication modes and frequency bands, RF devices have been widely applied.

[0003] In radio frequency (RF) devices, a bias voltage that meets preset conditions is required for the RF switch to turn on or off normally. Therefore, providing a stable bias voltage that meets preset conditions is crucial to the switching performance of the RF switch. Utility Model Content

[0004] In view of this, this application provides a switch control circuit and radio frequency device that can provide a stable bias voltage for the switch.

[0005] In a first aspect, embodiments of this application provide a switch control circuit, including:

[0006] A bias voltage generating circuit is used to output a bias voltage to the switch to control the switching state of the switch;

[0007] A voltage detection circuit, connected to the bias voltage generation circuit, is used to detect the bias voltage and obtain a detection signal characterizing whether the bias voltage meets a preset condition.

[0008] A voltage regulation signal generation circuit is connected to both the voltage detection circuit and the bias voltage generation circuit, and is used to output a voltage regulation signal to the bias voltage generation circuit according to the detection signal; wherein, when the detection signal indicates that the bias voltage does not meet the preset condition, the voltage regulation signal is in an effective level state until the detection signal indicates that the bias voltage meets the preset condition for a preset time; wherein, the bias voltage generation circuit adjusts the bias voltage to meet the preset condition according to the voltage regulation signal in the effective level state.

[0009] In some embodiments, the bias voltage includes a first bias voltage greater than 0 and a second bias voltage less than 0;

[0010] The voltage detection circuit includes a positive voltage detection circuit and a negative voltage detection circuit. The positive voltage detection circuit is used to detect the first bias voltage and output a first detection signal indicating whether the first bias voltage meets a first preset condition. The negative voltage detection circuit is used to detect the second bias voltage and output a second detection signal indicating whether the second bias voltage meets a second preset condition.

[0011] The detection signal includes a first detection signal and a second detection signal; if the first detection signal indicates that the first bias voltage does not meet the first preset condition and / or the second detection signal indicates that the second bias voltage does not meet the second preset condition, the detection signal indicates that the bias voltage does not meet the preset condition; if the first detection signal indicates that the first bias voltage meets the first preset condition and the second detection signal indicates that the second bias voltage meets the second preset condition, the detection signal indicates that the bias voltage meets the preset condition.

[0012] In some embodiments, the voltage regulation signal generation circuit includes:

[0013] A first logic circuit is connected to the output terminals of the positive pressure detection circuit and the negative pressure detection circuit, respectively, for receiving the first detection signal and the second detection signal, and outputting a first logic signal; wherein, when the first detection signal indicates that the first bias voltage does not meet the first preset condition or the second detection signal indicates that the second bias voltage does not meet the second preset condition, the level of the first logic signal is a first level; if the first detection signal indicates that the first bias voltage meets the first preset condition and the second detection signal indicates that the second bias voltage meets the second preset condition, the level of the first logic signal is a second level;

[0014] A delay feedback circuit, connected to the first logic circuit, is used to receive the first logic signal and a time signal representing the preset time, and output the voltage regulation signal; wherein, when the level of the first logic signal is a first level, the voltage regulation signal switches from an invalid level state to an active level state, and when the time after the level of the first logic signal switches from the first level to the second level reaches the preset time, the voltage regulation signal switches from an active level state to an invalid level state.

[0015] In some embodiments, the delay feedback circuit includes:

[0016] A delay generation circuit is used to receive the first logic signal and a time signal representing the preset time, and output a delay signal; wherein, within the preset time after the level of the first logic signal switches from a first level to a second level, the level of the delay signal is the first level, and when the preset time is reached after the level of the first logic signal switches from the first level to the second level, the level of the delay signal switches from the first level to the second level.

[0017] The second logic circuit is connected to the first logic circuit and the delay generation circuit respectively, and is used to receive the first logic signal and the delay signal respectively, and output the voltage regulation signal; wherein, when the level of the first logic signal is the first level, the voltage regulation signal is in the effective level state, and when the first logic signal is the second level and the delay signal is the second level, the voltage regulation signal is in the ineffective level state.

[0018] In some embodiments, the delay generation circuit includes:

[0019] The voltage divider circuit includes multiple voltage divider branches connected in series between a first potential terminal and a second potential terminal, and a capacitor connected between the second potential terminal and the ground terminal. The first potential terminal is used to receive the first logic signal, the second potential terminal is used to output the voltage to be quantized, and the connection node between two adjacent voltage divider branches is a voltage divider node.

[0020] The quantization encoding circuit includes a Schmitt trigger and a first inverter. The Schmitt trigger is connected to the second potential terminal and is used to quantize the voltage to be quantized into a digital signal. The input terminal of the first inverter is connected to the output terminal of the Schmitt trigger, and the output terminal of the first inverter outputs the delay signal.

[0021] A voltage divider adjustment circuit is used to receive the time signal and connect to at least some of the voltage divider nodes, so as to short-circuit the output node with the corresponding voltage divider node within a preset time according to the level change of the time signal, so that when the time after the level of the first logic signal switches from the first level to the second level reaches the preset time, the level of the delay signal switches from the first level to the second level.

[0022] In some embodiments, the voltage divider branch includes a first voltage divider branch, a second voltage divider branch, a third voltage divider branch, and a fourth voltage divider branch connected in sequence, and the voltage divider adjustment circuit includes a second inverter, a third inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first transmission gate, a second transmission gate, and a third transmission gate.

[0023] The first voltage divider branch is connected to the second potential terminal and is connected to the second voltage divider branch at the first voltage divider node. The second voltage divider branch is connected to the third voltage divider branch at the second voltage divider node, and the third voltage divider branch is connected to the fourth voltage divider branch at the third voltage divider node.

[0024] The time signal includes a first time signal and a second time signal. The input of the second inverter receives the first time signal, and the output of the second inverter outputs a first inverted signal. The input of the third inverter receives the second time signal, and the output of the third inverter outputs a second inverted signal. The first NAND gate receives the first inverted signal and the second time signal, and outputs a first enable signal. The second NAND gate receives the first time signal and the second inverted signal, and outputs a second enable signal. The third NAND gate receives the first time signal and the second time signal, and outputs a third enable signal.

[0025] The first transmission gate receives the first enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the third voltage divider node; the second transmission gate receives the second enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the second voltage divider node; the third transmission gate receives the third enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the first voltage divider node.

[0026] In some embodiments, the first logic circuit includes a fourth NAND gate, wherein the two input terminals of the fourth NAND gate are respectively input to the first detection signal and the second detection signal, and the output terminal outputs the first logic signal.

[0027] In some embodiments, the second logic circuit includes a NOR gate and a fourth inverter. The input terminals of the NOR gate receive the first logic signal and the delayed signal, respectively, and the output terminal is connected to the input of the fourth inverter. The output terminal of the fourth inverter outputs the voltage regulation signal.

[0028] In some embodiments, the bias voltage generating circuit includes:

[0029] An oscillator, connected to the output of the delay feedback circuit, is used to adjust the oscillation frequency according to the voltage regulation signal;

[0030] A charge pump, connected to the oscillator, is used to generate a bias voltage of a corresponding magnitude according to the oscillation frequency of the oscillator.

[0031] Secondly, embodiments of this application provide a radio frequency switch device, including a radio frequency switch and a switch control circuit as described in any one of the foregoing, wherein the switch control circuit is used to control the switching state of the radio frequency switch.

[0032] In several embodiments provided in this application, the bias voltage output by the bias voltage generation circuit is detected in real time by a voltage detection circuit. When the bias voltage does not meet the preset conditions, the voltage regulation signal generation circuit outputs a voltage regulation signal in a timely manner, which is in an effective level state. This allows the bias voltage generation circuit to adjust the bias voltage in a timely manner. When the bias voltage changes from not meeting the preset conditions to meeting the preset conditions, the voltage regulation signal generated by the voltage regulation signal generation circuit does not immediately switch to an invalid level state, but only switches to an invalid level state after a preset time. This allows the bias voltage generation circuit to continue adjusting the bias voltage during this time period, thereby ensuring that the condition for stabilizing the bias voltage is met, effectively improving the working stability of the switch. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a switch control circuit provided according to some embodiments of this application.

[0035] Figure 2 This is a schematic diagram of the structure of a voltage regulation signal generation circuit provided according to some embodiments of this application.

[0036] Figure 3 This is a schematic diagram of the delay generation circuit provided according to some embodiments of this application.

[0037] Figure label:

[0038] Switch control circuit 10, switch 20, voltage detection circuit 1, voltage regulation signal generation circuit 2, bias voltage generation circuit 3;

[0039] Positive pressure detection circuit 11, negative pressure detection circuit 12, delay feedback circuit 21, first logic circuit 22, oscillator 31, charge pump 32, delay generation circuit 210, second logic circuit 214, voltage divider circuit 211, quantization encoding circuit 212, voltage divider adjustment circuit 213;

[0040] First voltage divider branch 2111, second voltage divider branch 2112, third voltage divider branch 2113, fourth voltage divider branch 2114, first Schmitt trigger 2121, first inverter 2122, second inverter 2131, third inverter 2132, second NAND gate 2133, third NAND gate 2134, fourth NAND gate 2135, first transmission gate 2136, second transmission gate 2137, third transmission gate 2138, NOR gate 2141, fourth inverter 2142. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0043] To provide a bias voltage that meets preset conditions for an RF switch, the control method in related technologies typically involves detecting the bias voltage. If the bias voltage does not meet the preset conditions, the bias voltage is adjusted; if it does, the adjustment is stopped. However, due to process variations and inherent delays in the circuit, this type of RF switch control circuit struggles to provide a stable bias voltage that meets the preset conditions, thus failing to ensure the stability of the RF switch's operation. Therefore, this application provides a method where, after detecting that the bias voltage meets the preset conditions, the feedback to the bias voltage generation circuit is delayed for a preset time before being sent. This ensures that the voltage adjustment time of the bias voltage generation circuit ends after the preset delay, guaranteeing the stability of the bias voltage output. The following description uses providing a bias voltage for an RF switch as an example to illustrate the switch control circuits provided in various embodiments of this application. However, the switch control circuits provided in this application are not limited to providing bias voltages for RF switches; they can also be applied to providing bias voltages for other types of switches.

[0044] Please see Figure 1The diagram shows a schematic of a switch control circuit provided in some embodiments of this application. In some embodiments, the switch control circuit 10 includes a voltage detection circuit 1, a voltage regulation signal generation circuit 2, and a bias voltage generation circuit 3. The bias voltage generation circuit 3 outputs a bias voltage to the switch 20 to control the switching state of the switch 20. In this embodiment, the switch 20 is an RF switch. The voltage detection circuit 1 is connected to the bias voltage generation circuit 3 and is used to detect the bias voltage output by the bias voltage generation circuit 3 to obtain a detection signal characterizing whether the bias voltage meets a preset condition. The voltage regulation signal generation circuit 2 is connected to both the voltage detection circuit 1 and the bias voltage generation circuit 3 and is used to output a voltage regulation signal VSPEEDUP to the bias voltage generation circuit 3 according to the detection signal. When the detection signal characterizes that the bias voltage does not meet the preset condition, the voltage regulation signal VSPEEDUP is at an effective level until the detection signal characterizes that the bias voltage meets the preset condition for a preset time. The bias voltage generation circuit 3 adjusts the bias voltage to meet the preset condition according to the voltage regulation signal VSPEEDUP at an effective level.

[0045] The bias voltage meeting the preset condition refers to the condition that the bias voltage required for switch 20 to be normally turned off or on must meet. When the voltage regulation signal VSPEEDUP is at an active level, the bias voltage generation circuit 3 adjusts the magnitude of the output bias voltage to ensure that the bias voltage meets the corresponding preset condition. When the voltage regulation signal VSPEEDUP is at an inactive level, the bias voltage generation circuit 3 does not adjust the bias voltage, i.e., it maintains the current output bias voltage magnitude.

[0046] An effective level state refers to a level state that can indicate and trigger the bias voltage generation circuit 3 to adjust the bias voltage, while an invalid level state refers to the opposite state. In some embodiments, the effective level state is a high level state and the invalid level state is a low level state. In other embodiments, the effective level state is a low level state and the invalid level state is a high level state.

[0047] The voltage detection circuit 1 outputs a detection signal with a first state and a second state. When the detection signal is in the first state, it indicates that the current bias voltage meets the corresponding preset condition, meaning that there is no need to adjust the magnitude of the bias voltage. When the detection signal is in the second state, it indicates that the current bias voltage does not meet the corresponding preset condition, meaning that the magnitude of the bias voltage needs to be adjusted.

[0048] Voltage detection circuit 1 detects whether the bias voltage output by bias voltage generation circuit 3 meets preset conditions. If the bias voltage does not meet the preset conditions, voltage regulation signal generation circuit 2 outputs a voltage regulation signal VSPEEDUP at an effective level, causing bias voltage generation circuit 3 to adjust the magnitude of the bias voltage to meet the preset conditions. During the adjustment process by bias voltage generation circuit 3, voltage detection circuit 1 continues to detect the magnitude of the bias voltage. When voltage detection circuit 1 detects that the bias voltage has switched from a state that does not meet the preset conditions to a state that meets the preset conditions, the voltage regulation signal VSPEEDUP generated by voltage regulation signal generation circuit 2 does not immediately switch to an invalid level, but only switches to an invalid level after a preset time. Therefore, within a preset time period after the voltage detection circuit 1 detects that the bias voltage has switched from a state that does not meet the preset conditions to a state that meets the preset conditions, the voltage regulation signal VSPEEDUP remains at an effective level, so that the bias voltage generation circuit 3 continues to adjust the bias voltage during this time period, thereby ensuring that the condition for stabilizing the bias voltage is met, effectively improving the working stability of the switch 20.

[0049] In some embodiments, switch 20 is an RF switch. To ensure stable on / off switching of the RF switch, the bias voltage output by bias voltage generation circuit 3 includes a first bias voltage VPOS for providing gate bias to the RF switch and a second bias voltage VNEG for providing body bias to the RF switch. The first bias voltage is greater than 0, and the second bias voltage is less than 0. Bias voltage generation circuit 3 has a first output terminal and a second output terminal; the first output terminal is used to output the first bias voltage VPOS, and the second output terminal is used to output the second bias voltage VNEG.

[0050] In this embodiment, the voltage detection circuit 1 includes a positive voltage detection circuit 11 and a negative voltage detection circuit 12. The positive voltage detection circuit 11 is connected to the first output terminal of the bias voltage generation circuit and is used to receive a first bias voltage VPOS, thereby detecting the first bias voltage VPOS to obtain a first detection signal VYPOS characterizing whether the first bias voltage VPOS meets a first preset condition. The negative voltage detection circuit 12 is connected to the second output terminal of the bias voltage generation circuit and is used to receive a second bias voltage VNEG, thereby detecting the second bias voltage VNEG to obtain a second detection signal VYNEG characterizing whether the second bias voltage VNEG meets a second preset condition.

[0051] The voltage detection circuit 1 outputs detection signals including a first detection signal VYPOS and a second detection signal VYNEG. In this embodiment, the voltage regulation signal generation circuit 2 is connected to the output terminals of the positive voltage detection circuit 11 and the negative voltage detection circuit 12, respectively, to receive the first detection signal VYPOS and the second detection signal VYNEG, and determines whether the bias voltage meets a preset condition based on the current state of the first detection signal VYPOS and the second detection signal VYNEG. If the first detection signal VYPOS indicates that the first bias voltage VYPOS does not meet the first preset condition and / or the second detection signal VYNEG indicates that the second bias voltage VYNEG does not meet the second preset condition, then the detection signal indicates that the bias voltage does not meet the preset condition. If the first detection signal VYPOS indicates that the first bias voltage VYPOS meets the first preset condition and the second detection signal VYNEG indicates that the second bias voltage VYNEG meets the second preset condition, then the detection signal indicates that the bias voltage meets the preset condition.

[0052] In this embodiment, the positive pressure detection circuit 11, the voltage regulation signal generation circuit 2, and the bias voltage generation circuit 3 together constitute the first voltage regulation circuit for the first bias voltage VPOS, and the negative pressure detection circuit 12, the voltage regulation signal generation circuit 2, and the bias voltage generation circuit 3 together constitute the second voltage regulation circuit for the second bias voltage VNEG. The first and second voltage regulation circuits share the voltage regulation signal generation circuit 2. If either the first bias voltage VPOS or the second bias voltage VNEG fails to meet the corresponding preset condition, the voltage regulation signal generation circuit 2 outputs a voltage regulation signal at an effective level to instruct the bias voltage generation circuit 3 to adjust the voltage. Only when both the first bias voltage VPOS and the second bias voltage VNEG meet the corresponding preset conditions does the voltage regulation signal VSPEEDUP become in an ineffective level, and the bias voltage generation circuit 3 maintains the current bias voltage magnitude. Therefore, the switch control circuit 10 provided in this application embodiment can provide the switch 20 with a stable first bias voltage that meets the first preset condition and a stable second bias voltage that meets the second preset condition. The first voltage regulation circuit and the second voltage regulation circuit share the voltage regulation signal generation circuit 2. The circuit structure is simple and easy to implement.

[0053] Please continue reading. Figure 1As shown, in some embodiments, the voltage regulation signal generation circuit 2 includes a delay circuit 21 and a first logic circuit 22. The first logic circuit 22 is connected to the output terminals of the positive voltage detection circuit 11 and the negative voltage detection circuit 12, respectively, and is used to receive the first detection signal VYPOS and the second detection signal VYNEG, and output the first logic signal V1 to the delay circuit 22. Specifically, when the first detection signal VYPOS indicates that the first bias voltage VPOS does not meet the first preset condition or the second detection signal VYNEG indicates that the second bias voltage VNEG does not meet the second preset condition, the level of the first logic signal V1 is the first level; when the first detection signal VYPOS indicates that the first bias voltage VPOS meets the first preset condition and the second detection signal VYNEG indicates that the second bias voltage VNEG meets the second preset condition, the level of the first logic signal V1 is the second level. That is, in this embodiment, the level of the first logic signal V1 output by the first logic circuit 22 can determine whether the bias voltage output by the bias voltage generation circuit 3 meets the corresponding preset condition.

[0054] The delay feedback circuit 21 is connected to the first logic circuit 22 and is used to receive the first logic signal V1 and the time signal representing the preset time, and output the voltage-adjusted signal VSPEEDUP. The time signal may include, but is not limited to, the first time signal TD1 and the second time signal TD2. The first time signal TD1 and the second time signal TD2 are both level signals, that is, they have high level and low level respectively. Therefore, the first time signal TD1 and the second time signal TD2 combined together have four level combination states, namely 00, 01, 10 and 11. That is, the level states of the time signal composed of the first time signal TD1 and the second time signal TD2 in each time period are 00, 01, 10 and 11 respectively, and the time period corresponding to the time period is the preset time.

[0055] When the level of the first logic signal V1 is at the first level, the voltage regulation signal VSPEEDUP switches from an invalid level to an active level. When the time after the level of the first logic signal V1 switches from the first level to the second level reaches a preset time, the voltage regulation signal VSPEEDUP switches from an active level to an invalid level. In this embodiment, the first logic circuit 22 first merges the detection results of the positive voltage detection circuit 11 and the negative voltage detection circuit 12 into a first logic signal V1 that can characterize whether the bias voltage meets the preset conditions. Then, the delay feedback circuit 21, based on the first logic signal V1, promptly feeds back the detection result that the bias voltage does not meet the preset conditions to the bias voltage generation circuit 3, and delays the detection result that the first bias voltage switches from not meeting the preset conditions to meeting the preset conditions for a preset time before feeding it back to the bias voltage generation circuit 3, so as to ensure that the bias voltage stably meets the preset conditions, and the circuit structure is simple. In this embodiment, the first level is a high level and the second level is a low level. In other embodiments, the first level is a low level and the second level is a high level.

[0056] Please see Figure 2 The diagram shows a schematic of a voltage regulation signal generation circuit 2 provided according to some embodiments of this application. In some embodiments, the delay feedback circuit 21 includes a delay generation circuit 210 and a second logic circuit 214. The delay generation circuit 210 receives a first logic signal V1 and a time signal representing a preset time (such as a first time signal TD1 and a second time signal TD2), and outputs a delay signal V2. Within a preset time after the level of the first logic signal V1 switches from a first level to a second level, the level of the delay signal V2 is at the first level. When the time after the level of the first logic signal V1 switches from the first level to the second level reaches the preset time, the level of the delay signal V2 switches from the first level to the second level. In this embodiment, the first level is a high level, and the second level is a low level. The delay generation circuit 210 generates a delay signal V2 that is in the first level state when the first logic signal V1 switches from the first level to the second level, and switches from the first level state to the second level state when the time after the first logic signal V1 switches from the first level to the second level reaches the preset time.

[0057] The second logic circuit 214 is connected to the first logic circuit 22 and the delay generation circuit 210, respectively, and is used to receive the first logic signal V1 and the delay signal V2, and output the voltage regulation signal VSPEEDUP. When the level of the first logic signal V1 is the first level, the voltage regulation signal VSPEEDUP is in an active level state; when the first logic signal V1 is at the second level and the delay signal V2 is at the second level, the voltage regulation signal VSPEEDUP is in an inactive level state. In this embodiment, the delay generation circuit 210 switches the first logic signal V1 from the first level to the second level state for a preset time and then feeds it back to the second logic circuit 214. That is, the second logic circuit 214 determines the time when the voltage regulation signal VSPEEDUP switches from the inactive level state to the active level state based on the time when the first logic signal V1 switches from the second level to the first level state, and determines the time when the voltage regulation signal VSPEEDUP switches from the active level state to the inactive level state based on the level states of the first logic signal V1 and the delay signal V2. The voltage regulation signal generation circuit provided in this embodiment has a simple circuit structure and is easy to implement.

[0058] Please see Figure 3 The diagram shows a schematic of a delay generation circuit 210 provided according to some embodiments of this application. In some embodiments, the delay generation circuit 210 includes a voltage divider circuit 211, a quantization encoding circuit 212, and a voltage divider adjustment circuit 213. The voltage divider circuit 211 includes multiple voltage divider branches connected in series between a first potential terminal VIN and a second potential terminal D1, and a capacitor C1 connected between the second potential terminal D1 and a ground terminal GND. The first potential terminal VIN is connected to the output terminal of the first logic circuit 22 and is used to receive a first logic signal V1. The second potential terminal D1 is used to output the voltage to be quantized, and the connection node between two adjacent voltage divider branches is a voltage divider node. In this embodiment, the multiple voltage divider branches may include, but are not limited to, a first voltage divider branch 2111, a second voltage divider branch 2112, a third voltage divider branch 2113, and a fourth voltage divider branch 2114. The number of voltage divider branches is related to the number of time signals corresponding to a preset time.

[0059] In this embodiment, the time signals include two signals: a first time signal TD1 and a second time signal TD2, resulting in a total of 4 voltage divider branches. In other embodiments, if there are 3 time signals, the number of voltage divider branches can be 8. The voltage divider devices for each voltage divider branch can be of the same or different types, and the resistance values ​​of each voltage divider branch can be the same or different. In this embodiment, the voltage divider devices for each voltage divider branch are resistors, such as the first voltage divider branch 2111 including a first resistor R1, the second voltage divider branch 2112 including a second resistor R2, the third voltage divider branch 2113 including a second resistor R3, and the fourth voltage divider branch 2114 including a fourth resistor R4. The first resistor R1 to the fourth resistor R4 are connected in series. The first voltage divider branch 2111 is connected to the second potential terminal D1, and the node connecting it to the second voltage divider branch 2112 is the first voltage divider node X1. The node connected to the second voltage divider branch 2112 and the third voltage divider branch 2113 is the second voltage divider node X2, and the node connected to the third voltage divider branch 2113 and the fourth voltage divider branch 2114 is the third voltage divider node X3.

[0060] The quantization encoding circuit 212 includes a Schmitt trigger 2121 and a first inverter 2122. The Schmitt trigger 2121 is connected to the second potential terminal D1 and is used to quantize the voltage to be quantized into a digital signal. The input terminal of the first inverter 2122 is connected to the output terminal of the Schmitt trigger 2121, and the output terminal of the first inverter 2122 outputs a delayed signal V2.

[0061] The voltage divider adjustment circuit 213 is used to receive time signals (such as the first time signal TD1 and the second time signal TD2) and is connected to at least some of the voltage divider nodes. According to the change in the level of the time signal, the output node is short-circuited with the corresponding voltage divider node (such as the first voltage divider node X1, the second voltage divider node X2 and the third voltage divider node X3) within a preset time, so that when the time after the level of the first logic signal V1 switches from the first level to the second level reaches the preset time, the level of the delay signal V2 switches from the first level to the second level.

[0062] The delay feedback circuit 210 provided in this application embodiment adjusts the voltage to be quantized at the second potential terminal D1 by setting a voltage divider circuit 211 corresponding to a preset time, and then short-circuiting the second potential terminal D1 with each voltage divider node in the voltage divider circuit by a voltage divider adjustment circuit 213. The voltage to be quantized is then quantized into a digital signal by a quantization encoding unit to obtain a digitized delay signal V2. The circuit structure is simple and easy to implement.

[0063] Please continue reading. Figure 3As shown, in some embodiments, the voltage divider regulation circuit 213 includes a second inverter 2131, a third inverter 2132, a first NAND gate 2133, a second NAND gate 2134, a third NAND gate 2135, a first transmission gate 2136, a second transmission gate 2137, and a third transmission gate 2138.

[0064] The time signals include a first time signal TD1 and a second time signal TD2. The input of the second inverter 2131 receives the first time signal TD1, and the output outputs a first inverted signal TD1N. The input of the third inverter 2132 receives the second time signal TD2, and the output outputs a second inverted signal TD2N. A first NAND gate 2133 receives the first inverted signal TD1N and the second time signal TD2, and outputs a first enable signal EN1. A second NAND gate 2134 receives the first time signal TD1 and the second inverted signal TD2N, and outputs a second enable signal EN2. A third NAND gate 2135 receives the first time signal TD1 and the second time signal TD2, and outputs a third enable signal EN3.

[0065] The enable terminal EN of the first transmission gate 2136 receives the first enable signal EN1, and one of its input terminal IN and output terminal OUT is connected to the second potential terminal D1, while the other is connected to the third voltage divider node X3; the enable terminal EN of the second transmission gate 2137 receives the second enable signal EN2, and one of its input terminal IN and output terminal OUT is connected to the second potential terminal D1, while the other is connected to the second voltage divider node X2; the enable terminal EN of the third transmission gate 2138 receives the third enable signal EN3, and one of its input terminal IN and output terminal OUT is connected to the second potential terminal D1, while the other is connected to the first voltage divider node X1.

[0066] Please see Figure 1 As shown, in some embodiments, the first logic circuit 22 includes a fourth NAND gate. The two inputs of the fourth NAND gate are respectively input to a first detection signal VYPOS and a second detection signal VYNEG, and the output is the first logic signal V. Please refer to [link to relevant documentation]. Figure 2 or Figure 3 As shown, in some embodiments, the second logic circuit 214 includes a NOR gate 2141 and a fourth inverter 2142. The input terminal of the NOR gate 2141 receives a first logic signal V1 and a delay signal V2, respectively, and the output terminal is connected to the input of the fourth inverter 2142. The output terminal of the fourth inverter 2142 outputs a voltage regulation signal VSPEEDUP.

[0067] In some embodiments, when the first detection signal VYPOS is at a first level, it indicates that the first bias voltage VPOS meets a first preset condition; when the first detection signal VYPOS is at a second level, it indicates that the first bias voltage VPOS does not meet the first preset condition. The first bias voltage VPOS meeting the first preset condition can be that the first bias voltage VPOS is greater than or equal to a first threshold, where the first threshold is a value greater than 0. When the second detection signal VYNEG is at a first level, it indicates that the second bias voltage VNEG meets a second preset condition; when the second detection signal VYNEG is at a second level, it indicates that the second bias voltage VNEG does not meet the second preset condition. The second bias voltage VNEG meeting the second preset condition can be that the second bias voltage VNEG is less than or equal to a second threshold, where the second threshold is a value less than 0.

[0068] In some embodiments, the first level is high and the second level is low. When the first detection signal VYPOS is high and the second detection signal VYNEG is also high, the first logic signal V1 output by the fourth NAND gate is low, and the signal input to the first potential terminal VIN of the delay feedback circuit 21 is low. When the first detection signal VYPOS is low or the second detection signal VYNEG is low, the first logic signal V1 output by the fourth NAND gate is high, and the signal input to the first potential terminal VIN of the delay feedback circuit 21 is high.

[0069] When the first time signal TD1 and the second time signal TD2 are both low, the enable terminals of the first transmission gate 2136, the second transmission gate 2137 and the third transmission gate 2138 are respectively input with high-level signals, so that the first transmission gate 2136, the second transmission gate 2137 and the third transmission gate 2138 are respectively turned on. Then the voltage to be quantized at the second potential terminal D1 is approximately equal to the voltage at the first voltage divider node X1, the second voltage divider node X2 and the third voltage divider node X3.

[0070] When the first time signal TD1 is high and the second time signal TD2 is low, the signal levels input to the enable terminals of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are low, high, and high, respectively, so that the states of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are closed, open, and open, respectively. Then, the voltage to be quantized at the second potential terminal D1 is approximately equal to the voltage at the second voltage divider node X2 and the third voltage divider node X3, respectively.

[0071] When the first time signal TD1 is low and the second time signal TD2 is high, the signal levels input to the enable terminals of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are high, low, and high, respectively, so that the states of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are open, closed, and open, respectively. Then, the voltage to be quantized at the second potential terminal D1 is approximately equal to the voltages at the first voltage divider node X1 and the third voltage divider node X3, respectively.

[0072] When the first time signal TD1 is high and the second time signal TD2 is high, the signal levels input to the enable terminals of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are high, high, and low, respectively, so that the states of the first transmission gate 2136, the second transmission gate 2137, and the third transmission gate 2138 are open, open, and closed, respectively. Then, the voltage to be quantized at the second potential terminal D1 is approximately equal to the voltage at the first voltage divider node X1 and the second voltage divider node X2.

[0073] When the first logic signal V1 input at the first potential terminal VIN is high or the delay signal V2 output by the first inverter 2122 is high, the voltage regulation signal VSPEEDUP output by the fourth inverter 2142 is high (active level). When the first logic signal V1 input at the first potential terminal VIN is low and the delay signal V2 output by the first inverter 2122 is low, the voltage regulation signal VSPEEDUP output by the fourth inverter 2142 is low (inactive level).

[0074] Therefore, based on Figure 1 The delay circuit 22 shown outputs a high-level voltage regulation signal VSPEEDUP when it detects that either the first bias voltage VPOS or the second bias voltage VNEG does not meet the corresponding preset condition. This causes the bias voltage generation circuit 3 to perform corresponding boost regulation on the bias voltage. During the boost regulation, if the first bias voltage VPOS and the second bias voltage VNEG respectively meet the corresponding preset conditions, the voltage regulation signal VSPEEDUP does not immediately flip to a low level, but flips to a low level after a preset time. This ensures that the bias voltage can be boosted to meet the corresponding preset conditions, effectively improving the switching stability of the switch 20.

[0075] In some embodiments, the detection signal output by voltage detection circuit 1 is a digitized detection signal. Both positive voltage detection circuit 11 and negative voltage detection circuit 12 may include corresponding voltage divider sampling units and quantization encoding units. The voltage divider sampling unit is connected to the output of the corresponding bias voltage generation circuit 3 and is used to perform voltage divider sampling on the corresponding bias voltage to obtain an analog sampling signal. The quantization encoding unit includes a second Schmitt trigger and one or more inverters connected in series. The second Schmitt trigger is connected to the corresponding voltage divider sampling unit and is used to quantize the corresponding analog sampling signal. The one or more inverters connected in series are connected to the corresponding second Schmitt trigger and are used to perform logical conversion on the signal output by the second Schmitt trigger to obtain the corresponding digitized detection signal.

[0076] Please continue reading. Figure 1 As shown, in some embodiments, the bias voltage generating circuit 3 includes an oscillator 31 and a charge pump 32. The oscillator 31 outputs an oscillation signal to the charge pump 32, and the charge pump 32 generates a first bias voltage VPOS and a second bias voltage VNEG of corresponding magnitudes according to the frequency of the oscillation signal. In some embodiments, a level conversion circuit can also be provided between the charge pump 32 and the switch 20 to level-convert the bias voltage output by the charge pump 32 before outputting it to the switch 20.

[0077] The voltage regulation signal generation circuit 2 is connected to the oscillator 31 and is used to adjust the frequency of the oscillation signal of the oscillator 31 when the voltage regulation signal VSEEPDUP is at an active level, so that the charge pump 32 adjusts the bias voltage accordingly based on the change in the oscillation signal frequency. In some embodiments, when the voltage regulation signal VSEEPDUP is at an active level, the oscillation frequency of the oscillator 31 increases, and the bias voltage output by the charge pump 32 also increases accordingly, thereby adjusting the bias voltage to meet the corresponding preset conditions.

[0078] In some embodiments, this application also provides a radio frequency (RF) device, which includes a switch control circuit 10 and an RF switch according to any embodiment of this application. The switch control circuit 10 is used to control the switching state of the RF switch. The RF device can be an RF switch chip or an RF module containing an RF switch chip.

[0079] The radio frequency device provided in this application embodiment and the switch control circuit provided in this application embodiment can achieve essentially the same technical effect, and will not be described again here.

[0080] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0081] The above are merely specific embodiments of this application, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A switch control circuit, characterized in that, include: A bias voltage generating circuit is used to output a bias voltage to the switch to control the switching state of the switch; A voltage detection circuit, connected to the bias voltage generation circuit, is used to detect the bias voltage and obtain a detection signal characterizing whether the bias voltage meets a preset condition. A voltage regulation signal generation circuit is connected to both the voltage detection circuit and the bias voltage generation circuit, and is used to output a voltage regulation signal to the bias voltage generation circuit according to the detection signal; wherein, when the detection signal indicates that the bias voltage does not meet the preset condition, the voltage regulation signal is in an effective level state until the detection signal indicates that the bias voltage meets the preset condition for a preset time; wherein, the bias voltage generation circuit adjusts the bias voltage to meet the preset condition according to the voltage regulation signal in the effective level state.

2. The switch control circuit according to claim 1, characterized in that, The bias voltage includes a first bias voltage greater than 0 and a second bias voltage less than 0; The voltage detection circuit includes a positive voltage detection circuit and a negative voltage detection circuit. The positive voltage detection circuit is used to detect the first bias voltage and output a first detection signal characterizing whether the first bias voltage meets the first preset condition. The negative voltage detection circuit is used to detect the second bias voltage and output a second detection signal characterizing whether the second bias voltage meets the second preset condition; The detection signal includes a first detection signal and a second detection signal; If the first detection signal indicates that the first bias voltage does not meet the first preset condition and / or the second detection signal indicates that the second bias voltage does not meet the second preset condition, the detection signal indicates that the bias voltage does not meet the preset condition; If the first detection signal indicates that the first bias voltage meets the first preset condition and the second detection signal indicates that the second bias voltage meets the second preset condition, then the detection signal indicates that the bias voltage meets the preset condition.

3. The switch control circuit according to claim 2, characterized in that, The voltage regulation signal generation circuit includes: A first logic circuit is connected to the output terminals of the positive pressure detection circuit and the negative pressure detection circuit, respectively, for receiving the first detection signal and the second detection signal, and outputting a first logic signal; wherein, when the first detection signal indicates that the first bias voltage does not meet the first preset condition or the second detection signal indicates that the second bias voltage does not meet the second preset condition, the level of the first logic signal is a first level; if the first detection signal indicates that the first bias voltage meets the first preset condition and the second detection signal indicates that the second bias voltage meets the second preset condition, the level of the first logic signal is a second level; A delay feedback circuit, connected to the first logic circuit, is used to receive the first logic signal and a time signal representing the preset time, and output the voltage regulation signal; wherein, when the level of the first logic signal is a first level, the voltage regulation signal switches from an invalid level state to an active level state, and when the time after the level of the first logic signal switches from the first level to the second level reaches the preset time, the voltage regulation signal switches from an active level state to an invalid level state.

4. The switch control circuit according to claim 3, characterized in that, The delay feedback circuit includes: A delay generation circuit is used to receive the first logic signal and a time signal representing the preset time, and output a delay signal; wherein, within the preset time after the level of the first logic signal switches from a first level to a second level, the level of the delay signal is the first level, and when the preset time is reached after the level of the first logic signal switches from the first level to the second level, the level of the delay signal switches from the first level to the second level. The second logic circuit is connected to the first logic circuit and the delay generation circuit respectively, and is used to receive the first logic signal and the delay signal respectively, and output the voltage regulation signal; wherein, when the level of the first logic signal is the first level, the voltage regulation signal is in the effective level state, and when the first logic signal is the second level and the delay signal is the second level, the voltage regulation signal is in the ineffective level state.

5. The switch control circuit according to claim 4, characterized in that, The delay generation circuit includes: The voltage divider circuit includes multiple voltage divider branches connected in series between a first potential terminal and a second potential terminal, and a capacitor connected between the second potential terminal and the ground terminal. The first potential terminal is used to receive the first logic signal, the second potential terminal is used to output the voltage to be quantized, and the connection node between two adjacent voltage divider branches is a voltage divider node. The quantization encoding circuit includes a Schmitt trigger and a first inverter. The Schmitt trigger is connected to the second potential terminal and is used to quantize the voltage to be quantized into a digital signal. The input terminal of the first inverter is connected to the output terminal of the Schmitt trigger, and the output terminal of the first inverter outputs the delay signal. A voltage divider adjustment circuit is used to receive the time signal and connect to at least some of the voltage divider nodes, so as to short-circuit the output node with the corresponding voltage divider node within a preset time according to the level change of the time signal, so that when the time after the level of the first logic signal switches from the first level to the second level reaches the preset time, the level of the delay signal switches from the first level to the second level.

6. The switch control circuit according to claim 5, characterized in that, The voltage divider branch includes a first voltage divider branch, a second voltage divider branch, a third voltage divider branch, and a fourth voltage divider branch connected in sequence. The voltage divider adjustment circuit includes a second inverter, a third inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first transmission gate, a second transmission gate, and a third transmission gate. The first voltage divider branch is connected to the second potential terminal and is connected to the second voltage divider branch at the first voltage divider node. The second voltage divider branch is connected to the third voltage divider branch at the second voltage divider node, and the third voltage divider branch is connected to the fourth voltage divider branch at the third voltage divider node. The time signal includes a first time signal and a second time signal. The input terminal of the second inverter receives the first time signal, and the output terminal outputs a first inverted signal. The input terminal of the third inverter receives the second time signal, and the output terminal outputs a second inverted signal. The first NAND gate is used to receive the first inverted signal and the second time signal, and output a first enable signal; the second NAND gate is used to receive the first time signal and the second inverted signal, and output a second enable signal; the third NAND gate is used to receive the first time signal and the second time signal, and output a third enable signal. The first transmission gate receives the first enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the third voltage divider node; the second transmission gate receives the second enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the second voltage divider node; the third transmission gate receives the third enable signal at its enable terminal, and one of its input and output terminals is connected to the second potential terminal, while the other is connected to the first voltage divider node.

7. The switch control circuit according to claim 3, characterized in that, The first logic circuit includes a fourth NAND gate, the two input terminals of which are respectively input to the first detection signal and the second detection signal, and the output terminal outputs the first logic signal.

8. The switch control circuit according to claim 4, characterized in that, The second logic circuit includes a NOR gate and a fourth inverter. The input terminals of the NOR gate receive the first logic signal and the delay signal, respectively, and the output terminal is connected to the input of the fourth inverter. The output terminal of the fourth inverter outputs the voltage regulation signal.

9. The switch control circuit according to any one of claims 1 to 8, characterized in that, The bias voltage generating circuit includes: An oscillator, connected to the output of the delay feedback circuit, is used to adjust the oscillation frequency according to the voltage regulation signal; A charge pump, connected to the oscillator, is used to generate a bias voltage of a corresponding magnitude according to the oscillation frequency of the oscillator.

10. A radio frequency switching device, characterized in that, It includes a radio frequency switch and a switch control circuit as described in any one of claims 1 to 9, wherein the switch control circuit is used to control the switching state of the radio frequency switch.

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