Wafer burn-in test circuit and system
By introducing normally closed switching devices and protective resistors into the wafer aging test circuit, the problem of high leakage current in silicon carbide and gallium nitride power MOS wafer products is solved, current clamping and power consumption reduction are achieved, ensuring the accuracy and safety of aging tests.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- STELIGHT INSTR CO LTD
- Filing Date
- 2025-07-01
- Publication Date
- 2026-07-24
Smart Images
Figure CN224553411U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a wafer aging test circuit and system. Background Technology
[0002] In the semiconductor manufacturing industry, wafer-level aging testing is a crucial step in improving chip yield and reliability. Its core objective is to accelerate the exposure of potential internal defects such as dislocations in chip materials, process deviations, and oxide layer defects through methods such as high-temperature bias, thereby eliminating early-failure chips before packaging and reducing subsequent testing and packaging costs.
[0003] However, due to process issues, some silicon carbide and gallium nitride power MOS wafer products have a large leakage current problem. The high voltage leakage current of traditional wafer products is about 1uA, while the high voltage leakage current of current wafer products is about 10uA-10mA. Therefore, the existing wafer aging test circuit cannot play a protective role in aging tests. Utility Model Content
[0004] To address the aforementioned technical problems, this application provides a wafer aging test circuit and system.
[0005] In a first aspect, embodiments of this application disclose a wafer aging test circuit, including a power module, at least one test module, and at least one first protection module;
[0006] Each test module is connected to the corresponding power transistor under test on the wafer under test; the power supply module includes a high voltage source and a low voltage source; the high voltage source is used to provide a test signal to the drain of any power transistor under test, and the low voltage source is used to provide a reference power supply to the gate of any power transistor under test;
[0007] The first protection module includes a first normally closed switch device and a first protection resistor. The drain of the first normally closed switch device is connected to the source of the power transistor under test. The source of the first normally closed switch device is connected to the first end of the first protection resistor. The gate of the first normally closed switch device is connected to the second end of the first protection resistor. The second end of the first protection resistor is grounded.
[0008] In some possible embodiments, a second protection module is also included; the second protection module is disposed between the low-voltage source and the gate of the power transistor under test.
[0009] In some possible embodiments, the second protection module includes a second normally closed switch device and a second protection resistor; the drain of the second normally closed switch device is connected to the gate of the power transistor under test, the source of the second normally closed switch device is connected to the first end of the second protection resistor, the gate of the first normally closed switch device is connected to the second end of the second protection resistor, and the second end of the second protection resistor is connected to a low-voltage source.
[0010] In some possible embodiments, a control module is also included;
[0011] The first protection resistor is configured as a programmable resistor; the programmable resistor is communicatively connected to the control module, and its resistance value is adjusted based on the control signal from the control module.
[0012] In some possible embodiments, a circuit breaker module is also included; the second terminal of the first protective resistor is grounded through the circuit breaker module; the circuit breaker module is communicatively connected to the control module and disconnects the circuit based on the control signal from the control module.
[0013] In some possible embodiments, the circuit breaker module includes a first switching element and a current sensing element; a first terminal of the first switching element is connected to a second terminal of a first protective resistor, a second terminal of the first switching element is connected to a first terminal of the current sensing element, and a second terminal of the current sensing element is grounded;
[0014] The current sensing element is communicatively connected to the control module, detects and sends current signals to the control module; the first switching element is communicatively connected to the control module, receives and disconnects the circuit based on the control signals from the control module.
[0015] In some possible embodiments, the first switching element is configured as a high-voltage optocoupler relay.
[0016] In some possible embodiments, the first normally closed switching device is configured as a normally closed high-voltage metal-oxide-semiconductor field-effect transistor.
[0017] In some possible embodiments, the number of test modules is configured to be multiple, and the number of first protection modules is configured to be multiple;
[0018] Multiple test modules are connected in parallel and are all connected to the power supply module; each test module is connected in series with a corresponding first protection module.
[0019] Secondly, embodiments of this application disclose a wafer aging test system, including the wafer aging test circuit of any one of the above.
[0020] The technical solution provided in this application has the following technical effects:
[0021] The wafer aging test circuit of this application includes a power supply module, at least one test module, and at least one first protection module. Each test module is connected to a corresponding power transistor under test on the wafer under test. The power supply module includes a high-voltage source and a low-voltage source. The high-voltage source is used to provide a test signal to the drain of any power transistor under test, and the low-voltage source is used to provide a reference power supply to the gate of any power transistor under test. The first protection module includes a first normally closed switch device and a first protection resistor. The drain of the first normally closed switch device is connected to the source of the power transistor under test, the source of the first normally closed switch device is connected to the first end of the first protection resistor, the gate of the first normally closed switch device is connected to the second end of the first protection resistor, and the second end of the first protection resistor is grounded. In this embodiment, by setting a first protection module between the source and ground of the power transistor under test, when the power transistor under test ages and breaks down, the first protection resistor divides the voltage, thereby enabling the first normally closed switch device to clamp the current in the circuit within a set range, effectively protecting the devices in the circuit; by utilizing the characteristics of the first normally closed switch device to clamp the current, the first protection resistor with a lower resistance value can divide the voltage less, reducing power consumption, and also ensuring that the power transistor under test can be at a constant test voltage. Attached Figure Description
[0022] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 1 ;
[0024] Figure 2 This is a schematic diagram of the current flow of a wafer aging test circuit provided in an embodiment of this application;
[0025] Figure 3 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 2 ;
[0026] Figure 4 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 3 ;
[0027] Figure 5 This is a schematic diagram of the voltage waveform at a key point after a short circuit in channel one, provided in an embodiment of this application.
[0028] Figure label:
[0029] 1. Test module; 11. Power transistor under test; 12. Second switching device;
[0030] 2. Power supply module; 21. High voltage source; 22. Low voltage source;
[0031] 3. First protection module; 31. First normally closed switch device; 32. First protection resistor;
[0032] 4. Second protection module;
[0033] 5. Control module;
[0034] 6. Circuit breaker module; 61. First switching device; 62. Current detection device. Detailed Implementation
[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0036] It should be noted that the term "an embodiment" or "embodiment" in the specification of the embodiments of this application refers to a specific feature, structure, or characteristic that can be included in at least one implementation of this application. It should be understood that in the specification, claims, and accompanying drawings of the embodiments of this application, the terms "upper," "lower," "top," "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, in the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0037] It should be understood that when a device or component is referred to as being "on," "adjacent to," or "connected to" other devices or components, it may be directly on, adjacent to, or connected to other devices or components, or there may be intervening devices or components. Conversely, when a device or component is referred to as being "directly on," "directly adjacent to," or "directly connected to" other devices or components, there are no intervening devices or components. It should be understood that although the terms first, second, third, etc., may be used to describe various components, areas, layers, and / or parts, these components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one component, area, layer, or part from another component, area, layer, or part. Therefore, without departing from the teachings of this application, the first component, area, layer, or part discussed below may be referred to as the second component, area, layer, or part. And the discussion of the second component, area, layer, or part does not imply that the first component, area, layer, or part necessarily exists in this application.
[0038] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.
[0039] This application provides a wafer aging test circuit. Figure 1 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 1 The wafer aging test circuit includes at least one test module 1, a power supply module 2, and at least one first protection module 3.
[0040] like Figure 1 As shown, test module 1 is connected to the corresponding power transistor 11 of the wafer under test to perform aging tests on the power transistor 11. In this application, the power transistor 11 can be a silicon carbide (SiC) or gallium nitride (GaN) power MOS wafer product.
[0041] In this embodiment, the power module 2 includes a high-voltage source 21 and a low-voltage source 22. The high-voltage source 21 provides a test signal to the drain of the power transistor under test 11, and the low-voltage source 22 provides a low-voltage power supply to the gate of the power transistor under test 11. The wafer aging test in this application is a high-voltage reverse bias aging test. The high-voltage source 21 applies a high reverse voltage to the drain of the power transistor under test 11 to simulate the extreme voltage environment in the actual operation of the power transistor under test 11. The low-voltage source 22 applies a driving voltage to the gate of the power transistor under test 11 to determine the switching state of the power transistor under test 11.
[0042] In this embodiment of the application, the first protection module 3 includes a first normally closed switch device 31 and a first protection resistor 32. The drain of the first normally closed switch device 31 is connected to the source of the power transistor 11 under test. The source of the first normally closed switch device 31 is connected to the first end of the first protection resistor 32. The gate of the first normally closed switch device 31 is connected to the second end of the first protection resistor 32. The second end of the first protection resistor 32 is grounded.
[0043] Figure 2 This is a schematic diagram of the current flow in a wafer aging test circuit provided in an embodiment of this application, as shown below. Figure 2As shown, with the above settings, a first protection module 3 is set between the source and ground of the power transistor under test 11. When the power transistor under test 11 is aging normally, its impedance is relatively large, the first normally closed switch 31 is in the normally closed state, the first protection resistor 32 and the power transistor under test 11 divide the voltage, the current in the circuit is very small, and the first protection module 3 does not work. When the power transistor under test 11 is aging and breaking down, its impedance decreases, the current in the circuit increases, and the current flowing through the first protection resistor 32 forms a voltage drop, which is applied to the gate and source terminals of the first normally closed switch 31, forming a gate-source voltage Vgs. Vgs increases with the current. As the voltage increases, when Vgs reaches the threshold voltage Vth of the first normally closed switch device 31, the first normally closed switch device 31 stabilizes Vgs at Vth by adjusting its internal resistance, and the loop current also stabilizes at a fixed value, thereby clamping the current and effectively protecting the devices in the circuit. By using the characteristics of the first normally closed switch device 31 to clamp the current, it is possible to avoid setting the first protection resistor 32 to a large resistance, so that the first protection resistor 32 with a lower resistance value can achieve the protection function. The first protection resistor 32 with a lower resistance value can reduce the voltage drop and power consumption during normal aging, and can also ensure that the power transistor 11 under test can be at a constant test voltage.
[0044] Optionally, the first normally closed switching device 31 can be configured as a normally closed high-voltage metal-oxide-semiconductor field-effect transistor (MOS) or a normally closed high-voltage junction field-effect transistor (JFET), wherein the drain and source remain in a normally closed state when there is no gate drive voltage. In the embodiments of this application, the first normally closed switching device 31 is preferably configured as a normally closed high-voltage metal-oxide-semiconductor field-effect transistor.
[0045] In this embodiment of the application, the wafer aging test circuit further includes a second protection module 4, which is disposed between the low voltage source 22 and the gate of the power transistor 11 under test, and is used to protect the low voltage source 22 when the wafer is damaged by aging.
[0046] In one possible embodiment, the second protection module 4 includes a gate resistor to reduce the current in the circuit during wafer aging and breakdown, thereby preventing damage to the low-voltage source 22.
[0047] In another possible embodiment, similar to the first protection module 3, the second protection module 4 includes a second normally closed switch device and a second protection resistor. The drain of the second normally closed switch device is connected to the gate of the power transistor 11 under test, the source of the second normally closed switch device is connected to the first terminal of the first protection resistor 32, the gate of the second normally closed switch device is connected to the second terminal of the second protection resistor, and the second terminal of the second protection resistor is connected to the low-voltage source 22.
[0048] After the wafer ages and breaks down, the current flows through the second protection resistor to form a voltage drop, which is applied to the gate and source terminals of the second normally closed switching device to form a gate-source voltage Vgs. Vgs increases with the increase of current. When Vgs reaches the threshold voltage Vth of the second normally closed switching device, the second normally closed switching device stabilizes Vgs at Vth by adjusting its internal resistance. The loop current is also stabilized at a fixed value, thus clamping the current and effectively protecting the low-voltage source 22.
[0049] Figure 3 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 2 In one possible embodiment, the wafer aging test circuit further includes a control module 5, which can be configured as a microcontroller unit (MCU). The first protection resistor 32 is configured as a programmable resistor with adjustable resistance. The programmable resistor is communicatively connected to the control module 5, and its resistance value is adjusted based on the control signals from the control module 5.
[0050] Before starting the aging test, the resistance value of the first protection resistor 32 is determined according to the switching characteristics of the first normally closed switch device 31. The control module 5 sends a control signal to the programmable resistor so that after the power transistor under test 11 breaks down, the voltage drop formed by the current flowing through the first protection resistor 32 can clamp the current of the first normally closed switch device 31.
[0051] Similarly, the second protection resistor can also be configured as a programmable resistor with an adjustable resistance value, and communicate with the control module 5 to adjust the resistance value of the programmable resistor based on the control signal of the control module 5.
[0052] In the embodiments of this application, such as Figure 3 As shown, the wafer aging test circuit also includes a circuit breaker module 6, used to disconnect the circuit after the power transistor 11 under test breaks down. The second terminal of the first protection resistor 32 is grounded through the circuit breaker module 6; the circuit breaker module 6 is communicatively connected to the control module 5 and disconnects the circuit based on the control signal from the control module 5.
[0053] In one possible embodiment, the circuit breaker module 6 includes a first switch 61 and a current detection element 62. A first terminal of the first switch 61 is connected to a second terminal of the first protective resistor 32, and a second terminal of the first switch 61 is connected to a first terminal of the current detection element 62, with the second terminal of the current detection element 62 grounded.
[0054] The current detection element 62 is communicatively connected to the control module 5, detects and sends current signals to the control module 5; the first switch element 61 is communicatively connected to the control module 5, receives and disconnects the circuit based on the control signals of the control module 5.
[0055] In this embodiment, after receiving the current signal, the control module 5 compares it with the clamping current as a reference. When the current reaches the clamping current, it indicates that the power transistor 11 under test has aged and broken down. The control module 5 sends a control signal to the first switching device 61 to disconnect the circuit and reduce power consumption.
[0056] In one possible embodiment, the first switching element 61 is configured as a high-voltage optocoupler relay. The optocoupler of the high-voltage optocoupler relay illuminates upon receiving a control signal from the control module 5. Upon detecting the illumination of the optocoupler, the relay disconnects the circuit, achieving isolation while simultaneously shutting off the circuit.
[0057] Figure 4 This is a schematic diagram of a wafer aging test circuit provided in an embodiment of this application. Figure 3 In one possible embodiment, the number of test modules 1 is configured to be multiple, and the number of first protection modules 3 is also configured to be multiple accordingly. This application Figure 4 The image shows a wafer aging test circuit with three channels, from left to right: channel one, channel two, and channel three.
[0058] In some possible embodiments, the test module 1 of channel one further includes a second switch 12. The first terminal of the second switch 12 is connected to the drain of the power transistor 11 under test, and the second terminal of the second switch 12 is connected to the source of the power transistor 11 under test. The second switch 12 can also be configured as a high-voltage optocoupler relay, which is communicatively connected to the control module, receives and closes the circuit based on the control signal of the control module, and simulates the breakdown of the power transistor 11 under test in channel one.
[0059] In this embodiment, multiple test modules 1 are connected in parallel and are all connected to the power supply module 2, forming a multi-channel wafer aging test circuit. Each test module 1 is connected in series with a corresponding first protection module 3 to protect the power transistor 11 under test in each channel. The programmable resistor in each channel is communicatively connected to the control module 5 and can be adjusted to different resistance values by receiving control signals.
[0060] Figure 5 This is a schematic diagram of the voltage waveform at a key point after a short circuit in channel one, as provided in an embodiment of this application. Figure 5 As shown, Figure 5 The three waveforms shown, from top to bottom, are the voltage waveforms of the gate of the power transistor under test in channel 2, the front end of the current detection device 62 in channel 1, and the gate of the power transistor under test 11 in test channel 1.
[0061] During normal aging tests of the power transistors 11 in multiple channels, the second switch 12 of channel one is suddenly closed to simulate a short circuit of the power transistor 11 in channel one. The gate waveforms of the power transistor 11 in channel one, the front end of the current sensing element 62 in channel one, and the gate waveforms of the power transistor 11 in channel two are then tested. Figure 5 No abnormal surges were observed.
[0062] The above test shows that when the power transistor 11 under test in one channel is broken down, the corresponding channel is thermally cut off after the current channel is clamped. This will not cause voltage jitter and will not affect the power module 2. Therefore, it will not affect the normal aging channels of other common power modules 2.
[0063] This application also provides a wafer aging test system, which includes the wafer aging test circuit described above. By setting up the wafer aging test circuit, accurate and safe wafer aging tests can be achieved using the first protection module.
[0064] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0065] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0066] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0067] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A wafer aging test circuit, characterized in that, It includes a power supply module (2), at least one test module (1), and at least one first protection module (3); Each of the test modules (1) is connected to the corresponding power transistor (11) under test of the wafer under test; the power supply module (2) includes a high voltage source (21) and a low voltage source (22); the high voltage source (21) is used to provide a test signal to the drain of any of the power transistors under test (11), and the low voltage source (22) is used to provide a reference power supply to the gate of any of the power transistors under test (11); The first protection module (3) includes a first normally closed switch (31) and a first protection resistor (32). The drain of the first normally closed switch (31) is connected to the source of the power transistor under test (11). The source of the first normally closed switch (31) is connected to the first end of the first protection resistor (32). The gate of the first normally closed switch (31) is connected to the second end of the first protection resistor (32). The second end of the first protection resistor (32) is grounded.
2. The wafer aging test circuit according to claim 1, characterized in that, It also includes a second protection module (4); the second protection module (4) is disposed between the low voltage source (22) and the gate of the power transistor (11) under test.
3. The wafer aging test circuit according to claim 2, characterized in that, The second protection module (4) includes a second normally closed switch device and a second protection resistor; the drain of the second normally closed switch device is connected to the gate of the power transistor under test (11), the source of the second normally closed switch device is connected to the first end of the second protection resistor, the gate of the second normally closed switch device is connected to the second end of the second protection resistor, and the second end of the second protection resistor is connected to the low voltage source (22).
4. The wafer aging test circuit according to claim 1, characterized in that, It also includes a control module (5); The first protection resistor (32) is configured as a programmable resistor; the programmable resistor is communicatively connected to the control module (5), and the resistance value of the programmable resistor is adjusted based on the control signal of the control module (5).
5. A wafer aging test circuit according to claim 4, characterized in that, It also includes a circuit breaker module (6); the second end of the first protection resistor (32) is grounded through the circuit breaker module (6); the circuit breaker module (6) is communicatively connected to the control module (5) and disconnects the circuit based on the control signal of the control module (5).
6. A wafer aging test circuit according to claim 5, characterized in that, The circuit breaker module (6) includes a first switch (61) and a current detection element (62); the first end of the first switch (61) is connected to the second end of the first protection resistor (32), the second end of the first switch (61) is connected to the first end of the current detection element (62), and the second end of the current detection element (62) is grounded. The current detection element (62) is communicatively connected to the control module (5), detects and sends a current signal to the control module (5); the first switch element (61) is communicatively connected to the control module (5), receives and disconnects the circuit based on the control signal of the control module (5).
7. A wafer aging test circuit according to claim 6, characterized in that, The first switching element (61) is configured as a high-voltage optocoupler relay.
8. A wafer aging test circuit according to claim 1, characterized in that, The first normally closed switch device (31) is configured as a normally closed high voltage metal-oxide-semiconductor field-effect transistor.
9. A wafer aging test circuit according to claim 1, characterized in that, The number of test modules (1) is configured to be multiple, and the number of first protection modules (3) is configured to be multiple; Multiple test modules (1) are connected in parallel and are all connected to the power supply module (2); each test module (1) is connected in series with a corresponding first protection module (3).
10. A wafer aging test system, characterized in that, Includes the wafer aging test circuit as described in any one of claims 1-9.