1mw three-level power module test circuit

Abstract

The utility model discloses a kind of 1MW three-level power module test circuit, belong to power module test technical field.The test circuit includes power module, drive module, control module and fault feedback module, power module is powered for other module, control module is connected through drive module and communicates with host computer to be measured power module, fault feedback module is connected with the output end of to-be-tested power module through adapter seat and signal is fed back to control module.It has beneficial effect in that, realize fast board level test by modularization design, reduce cost, shorten development cycle;Reserved interface improves universality;Multi-stage isolation design inhibits interference, guarantee test stable and accurate;Fault feedback module real-time monitoring and block PWM output, protect measured module.The test circuit solves the problems, such as large volume, high cost, low function integration of traditional tooling, with good practicality and popularization value.

Description

Technical Field

[0001] This utility model relates to the field of power module testing technology, specifically to a 1MW three-level power module testing circuit. Background Technology

[0002] Three-level topology power modules are widely used in high-power energy conversion systems due to their high efficiency and reliability, and their core power devices mostly employ insulated-gate bipolar transistors (IGBTs). In actual operation, the high voltage and high switching frequency characteristics of high-power inverters, along with the switching action of power devices, can cause harmonics in the power module under high dv / dt conditions. Simultaneously, the three-level topology is prone to neutral point potential imbalance. These issues place higher demands on the testing of power modules.

[0003] Traditional power module test fixtures have significant drawbacks: First, they suffer from poor signal isolation, failing to effectively suppress harmonic and common-mode interference in high dv / dt environments, leading to distorted test data. Second, they are costly, with complex hardware structures and dedicated test equipment resulting in high R&D and testing costs. Third, they have low functional integration, making it difficult to achieve efficient testing of power modules at the board level and failing to meet the needs of harmonic interference suppression and control algorithm development. Specifically, traditional solutions are insufficient in signal control accuracy, real-time fault feedback, and electrical isolation performance, unable to simulate the operating state of power modules under complex working environments, severely restricting product development efficiency. Therefore, there is an urgent need for a compact test circuit solution based on modular design, featuring multi-level isolation protection and integrated real-time fault monitoring. Utility Model Content

[0004] This utility model aims to provide a 1MW three-level power module test circuit, which realizes rapid board-level testing of power modules through modular design, solves the problems of large size and high cost of traditional test fixtures, and meets the development requirements of harmonic interference suppression and control algorithms during the testing process.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A 1MW three-level power module test circuit includes a power supply module 1, a drive module 2, a control module 3, and a fault feedback module 4. The power supply module 1 supplies power to the drive module 2, the control module 3, and the fault feedback module 4. The output terminal of the control module 3 is connected to an external power module under test through the drive module 2 and communicates with an external host computer, and receives signals from the fault feedback module 4. The fault feedback module 4 is connected to the output terminal of the external power module under test through an adapter 5, and the output terminal of the fault feedback module 4 is connected to the input terminal of the control module 3.

[0006] Furthermore, the power module 1 includes: The reverse connection protection circuit 11 has its input terminal connected to an external input power supply and outputs an isolated 15V power supply through the PMOS transistor 111 to prevent the external input power supply from being reversed and to supply power to the drive module 2. The first power chip circuit 12 is connected to the output terminal of the reverse connection protection circuit 11 and is used to convert the isolated 15V power supply into a non-isolated 5V power supply for use by the non-isolated parts of the drive module 2, control module 3 and fault feedback module 4. The first linear regulator circuit 13 is connected to the output terminal of the reverse connection protection circuit 11 and is used to convert the isolated 15V power supply into an isolated 5V power supply for use by the circuits in the fault feedback module 4 that require electrical isolation. The second linear regulator circuit 14 is connected to the output terminal of the first power chip circuit 12 and is used to convert the non-isolated 5V power supply into a non-isolated 3.3V power supply to power the control module 3. The second power chip circuit 15 is connected to the output terminal of the first linear regulator circuit 13 and is used to convert the non-isolated 5V power supply into an isolated 1.5V power supply to realize anti-interference communication between the control module 3 and the external host computer.

[0007] Furthermore, the driving module 2 includes: The buffer chip 21 has its input terminal connected to the PWM signal output terminal of the control module, and is used to convert the PWM signal output by the control module into an intermediate level signal. Inverter 22, whose input is connected to the output of the buffer chip, is used to invert the intermediate level signal. The high-speed dual-channel optocoupler 23 has its input terminal connected to the output terminal of the inverter and its output terminal connected to the power module under test. It is used to electrically isolate the intermediate level signal after inversion and convert it into a drive level signal adapted to the power module under test.

[0008] Furthermore, the control module 3 includes: The main control chip circuit 31 includes a main control chip 311 of model XC6SLX9-2TQG144, which is used to output multiple PWM signals to the drive module 2 and receive fault feedback signals from the fault feedback module 4. The fiber optic transceiver circuit 32 includes a fiber optic transmitter 321, a fiber optic receiver 322, and a driver chip 323. The fiber optic transmitter 321 is connected to the transmitting interface of the main control chip 311 via the driver chip 323, and the fiber optic receiver 322 is connected to the receiving interface of the main control chip via the driver chip 323. This circuit enables high-speed optical communication between the control module 3 and an external host computer.

[0009] The isolation circuit 33 includes an isolation transceiver 331 connected to the main control chip 311, which is used to realize differential signal isolation communication between the control module 3 and external devices.

[0010] Furthermore, the fault feedback module 4 includes a voltage detection circuit 41, a fault summary circuit 42, and a PWM feedback acquisition circuit 43, which are used to monitor the key point voltage inside the power module under test and the fault signal of the power module under test, and block the PWM output to protect the circuit when there is an abnormality.

[0011] Furthermore, the fault feedback module 4 includes a voltage detection circuit 41, which includes: a dual-channel comparator U35, a first sampling resistor R97, a second sampling resistor R102, a third sampling resistor R99, an overvoltage threshold divider resistor R96, an overvoltage threshold adjustment resistor R94, an undervoltage threshold divider resistor R93, an undervoltage threshold adjustment resistor R87, a first grounding resistor R100, a second grounding resistor R103, a first diode D1, a second diode D2, a first transistor Q3, a first bias resistor R98, a second bias resistor R101, and a filter capacitor C22. The output terminal of the isolated 15V power supply is connected to one end of the second sampling resistor R102 through the first sampling resistor R97, and the other end of the second sampling resistor R102 is grounded. The connection node between the first sampling resistor R97 and the second sampling resistor R102 is connected to the first channel positive input pin and the second channel negative input pin of the dual-channel comparator U35 through the third sampling resistor R99, which is used to form the sampling voltage input branch. The output terminal of the isolated 5V power supply is connected to the common terminal of the parallel overvoltage threshold adjustment resistor R94 and the overvoltage threshold voltage divider resistor R96. The other end of the overvoltage threshold adjustment resistor R94 and the other end of the overvoltage threshold voltage divider resistor R96 are connected to the first terminal of the first grounding resistor R100, and the second terminal of the first grounding resistor R100 is grounded. The connection node of the overvoltage threshold adjustment resistor R94, the overvoltage threshold voltage divider resistor R96 and the first grounding resistor R100 is connected to the first channel inverting input pin of the dual-channel comparator U35 to form an overvoltage threshold voltage generation circuit. The output terminal of the isolated 5V power supply is connected to the common terminal of the parallel undervoltage threshold adjustment resistor R87 and undervoltage threshold voltage divider resistor R93. The other end of the undervoltage threshold adjustment resistor R87 and the other end of the undervoltage threshold voltage divider resistor R93 are connected to the first terminal of the second grounding resistor R103, and the second terminal of the second grounding resistor R103 is grounded. The connection node of the undervoltage threshold adjustment resistor R87, the undervoltage threshold voltage divider resistor R93 and the second grounding resistor R103 is connected to the second channel positive input pin of the dual-channel comparator U35 to form an undervoltage threshold voltage generation circuit. The first channel output pin of the dual-channel comparator U35 is connected to the base of the first transistor Q3 through the first diode D1, and the second channel output pin is connected to the base of the first transistor Q3 through the second diode D2; the collector of the first transistor Q3 serves as the output terminal of the voltage detection circuit 41, used to output overvoltage and undervoltage protection signals.

[0012] Furthermore, the control module 3 outputs a fault signal as the first fault signal based on a fault command from an external host computer; the fault feedback module 4 also includes a fault aggregation circuit 42, which is equipped with: The multi-input logic processing unit 421 is used to summarize the overvoltage and undervoltage protection signals and multiple sets of three-phase fault signals. It includes a CMOS AND gate element 421a, which is provided with a first fault input terminal T1 for receiving the overvoltage and undervoltage protection signals and multiple second fault input terminals T2 for receiving multiple sets of three-phase fault signals from an external power module under test. An isolation output unit 422 is used to electrically isolate the aggregated overvoltage and undervoltage protection signals and multiple sets of three-phase fault signals output by the multi-input logic processing unit 421, so as to output a second fault signal. The isolation output unit 422 includes an optocoupler 422a. The input terminal of the optocoupler 422a is connected to the output terminal of the CMOS AND gate element 421a, and the output terminal of the optocoupler 422a is connected to the OR gate output unit 423. This disconnects the electrical connection between the multi-input logic processing unit 421 and the OR gate output unit 423 to suppress common-mode interference. OR gate output unit 423 includes a dual-input OR gate element 423a. The dual-input OR gate element 423a is provided with a first signal receiving terminal T3 for receiving the first fault signal, a second signal receiving terminal T4 for receiving the second fault signal, and a fault output terminal SO connected to the control module 3 and outputting a fault summary signal to block the PWM output.

[0013] Furthermore, the fault feedback module 4 also includes a PWM feedback acquisition circuit 43, equipped with a feedback dual-channel optocoupler 431. The output terminal of the power module under test is connected to the control module 3 through the feedback dual-channel optocoupler 431, used to convert the PWM signal output by the power module under test into a TTL level signal that the control module 3 can receive. Furthermore, the adapter 5 includes a temperature sensor interface 51, a drive PWM output interface 52, a module PWM feedback interface 53, and a fault output interface 54.

[0014] Furthermore, it also includes a reserved connector interface 6 for measuring external power modules under test with different interfaces.

[0015] Low-cost and efficient testing: Enables rapid testing of power modules without the need for expensive testing fixtures. Basic functional verification of power modules can be completed through board-level testing, significantly saving testing costs and shortening product development cycles.

[0016] High versatility and adaptability: The interface is easy to expand, with reserved dual 37-pin DB connector interfaces. By simply adding a DB interface adapter board, power modules with different interfaces on the market can be measured, which improves the versatility and adaptability of the test circuit.

[0017] Strong anti-interference capability: The design adopts multi-level power isolation (such as reverse connection protection circuit and linear regulator isolation) and signal isolation (such as high-speed optocoupler and isolated transceiver) to effectively suppress harmonic interference and common-mode interference, ensuring the stability of the test process and the accuracy of the data, and providing a reliable test environment for the development of control algorithms.

[0018] Comprehensive fault protection: The fault feedback module enables real-time monitoring and summarization of overvoltage, undervoltage, and three-phase faults. Through logic processing, it quickly blocks the PWM output to protect the power module under test from fault damage and improve test safety. Attached Figure Description

[0019] Figure 1 This is a system composition diagram for this case; Figure 2 This is the circuit schematic of the power module in this case; Figure 3 This is the circuit schematic of the buffer chip of the driver module in this case; Figure 4 This is the schematic diagram of the inverter and high-speed dual-channel optocoupler circuit of the driver module in this case; Figure 5 This is the circuit schematic of the main control chip of the main control module in this case; Figure 6 This is the schematic diagram of the fiber optic transceiver circuit of the main control module in this case; Figure 7 This is the schematic diagram of the isolation circuit of the main control module in this case; Figure 8 This is the schematic diagram of the voltage detection circuit of the fault feedback module in this case; Figure 9 This is the circuit diagram of the fault summary circuit of the fault feedback module in this case; Figure 10 This is the schematic diagram of the PWM input circuit of the fault feedback module in this case; Figure 11 This is the circuit diagram of the adapter in this case; Figure 12 This is the circuit schematic diagram of the connector interface reserved in this case; Detailed Implementation

[0020] This utility model provides a 1MW three-level power module test circuit that achieves efficient board-level testing of power modules through modular design. The circuit is centered around a power module 1, a drive module 2, a control module 3, and a fault feedback module 4, along with an adapter 5 and a reserved connector interface 6, forming a complete test system. The power module 1 provides multi-level isolated power, the drive module 2 performs PWM signal level conversion and electrical isolation, the control module 3 uses a main control chip and high-speed communication circuit to achieve signal output and data interaction, and the fault feedback module 4 monitors voltage and fault signals in real time and executes protection mechanisms. The adapter 5 and reserved interface 6 ensure the circuit's compatibility with different power modules. The modules work together to achieve harmonic interference suppression, fault protection, and control algorithm verification for the three-level power module, solving the problems of large size, high cost, and low functional integration of traditional test fixtures.

[0021] The working principle of this utility model will be described in detail below with reference to the accompanying drawings and specific circuit parameters:

[0022] like Figure 2 As shown, the power module input is connected to a low-voltage auxiliary power supply, with an input voltage range of DC13V-DC17V. Its specific structure is as follows: Reverse connection protection circuit 11: It is composed of PMOS transistor 111 and other components. JP1 is a 15V power input port. PMOS transistor 111 realizes the reverse connection protection function to prevent external power reverse connection from damaging the circuit. It outputs 15V isolated power supply ISO_15V to the drive module.

[0023] The first power chip circuit 12 is connected to the output terminal of the reverse connection protection circuit 11. It uses an isolated power module U38 to step down ISO_15V to a non-isolated 5V power supply VCC5V0, which powers the non-isolated parts of the drive module 2, control module 3 and fault feedback module 4.

[0024] The first linear regulator circuit 13 is connected to the output of the reverse connection protection circuit. It uses a linear regulator U39 to convert the isolated 15V power supply ISO_15V to the isolated 5V power supply ISO_VCC5V for use by the circuits in the fault feedback module that require electrical isolation.

[0025] The second linear regulator circuit 14 is connected to the output terminal of the first power chip circuit 13. It uses a linear regulator V1 to convert the non-isolated 5V power supply VCC5V0 to a non-isolated 3.3V power supply VCC3V3 to power the main control chip of the control module 3.

[0026] The second power supply chip circuit 15 is connected to the output terminal of the first linear regulator circuit 13. It uses an isolated power supply module U40 to convert the non-isolated 5V power supply VCC5V0 into an isolated 1.5V power supply ISO1_5V for use by the isolated 485, thereby enabling anti-interference communication between the control module 3 and the external host computer.

[0027] like Figures 3-4 As shown, the input to drive module 2 is the 3.3V PWM signal output from the control module, and its specific working process is as follows: Buffer chip 21: The buffer chip U30 with model number SN74LVC16245 is used. The operating voltage is 3.3V and 5V. It is directly connected to the IO port of the control module to convert the 3.3V PWM signal output by the control module into a 5V PWM signal. A total of 3 sets of SN74LVC16245 buffer chips are used. Each phase requires 6 PWM signals. Each set outputs two phases of PWM signals, for a total of 6 phases.

[0028] Inverter 22: The inverter U21, model 74LS14, is connected to the output pin of the buffer chip 21 to invert the 5V PWM signal, remove interference glitches from the PWM signal, and prevent the IGBT power module from being mis-activated. Six groups of 74LS14 chips are used, with each group outputting PWM for one phase.

[0029] High-speed dual-channel optocoupler 23: It adopts a high-speed dual-channel optocoupler HCPL-2231, which is connected to the output of the inverter to convert the 5V PWM signal into a 15V level PWM signal that can drive the IGBT gate. At the same time, the optocoupler realizes electrical isolation and interlock protection of the signal to prevent the modules from conducting at the same time. The output of the optocoupler is connected to the power module through DB37 connector or horn connector. A total of 18 HCPL2231s are used to output 18 groups of 36 complementary PWM waveforms.

[0030] like Figures 5-7 As shown, control module 3 consists of main control chip 311 and its peripheral circuits, and its specific functions are implemented as follows: The main control chip 311, model XC6SLX9-2TQG144, belongs to the Xilinx Spartan 6 series. To meet the requirements of two sets of three-phase three-level PWM outputs, at least 36 PWM output pins are needed. At the same time, it needs to receive one fault signal and PWM signal returned from each phase power module (a total of 6 phases and 12 sets of IO), as well as 485 signals, fiber optic signals and other protection signals for communication with the host computer. The XC6SLX9-2TQG144 chip can easily meet the above IO resource requirements, output multiple PWM signals to the drive module and receive fault feedback signals from the fault feedback module.

[0031] Fiber optic transceiver circuit 32: includes fiber optic transmitter 321 and fiber optic receiver 322, with two transmitters and two receivers, and a maximum speed of 5 Mbit / s. The transmitter driver chip 323 is TI's SN75451. The driver chip 323 is connected to the main control chip 311 to realize high-speed optical communication between the control module 3 and the external host computer.

[0032] Isolation circuit 33: TI's ISO1410 half-duplex isolated RS485 transceiver 331 is used and connected to the main control chip 311 to realize RS485 bus communication between the control module and field devices, ensuring the anti-interference capability of communication.

[0033] like Figures 8-10 As shown, the fault feedback module 4 is used to detect fault signals and power supply voltage of the power module. Its specific structure and working principle are as follows: Voltage detection circuit 41: It is composed of a dual-channel comparator U35, a first sampling resistor R97, a second sampling resistor R102, a third sampling resistor R99, an overvoltage threshold divider resistor R96, an overvoltage threshold adjustment resistor R94, an undervoltage threshold divider resistor R93, an undervoltage threshold adjustment resistor R87, a first grounding resistor R100, a second grounding resistor R103, a first diode D1, a second diode D2, a first transistor Q3, a first bias resistor R98, a second bias resistor R101, and a filter capacitor C22. The output of the isolated 15V power supply is divided by the first sampling resistor R97 and the second sampling resistor R102. The divided signal is then connected to the first channel positive input pin and the second channel inverting input pin of the dual-channel comparator U35 via the third sampling resistor R99, forming the sampling voltage input branch. The output of the isolated 5V power supply is divided by the overvoltage threshold adjustment resistor R94, the overvoltage threshold divider resistor R96, and the first grounding resistor R100, forming the overvoltage threshold voltage generation circuit, which is connected to the first channel inverting input pin of the dual-channel comparator U35. The output of the isolated 5V power supply is divided by the undervoltage threshold adjustment resistor R87, the undervoltage threshold divider resistor R93, and the second grounding resistor R103, forming the undervoltage threshold voltage generation circuit, which is connected to the second channel positive input pin of the dual-channel comparator U35. When the input voltage is greater than the overvoltage threshold or less than the undervoltage threshold, the output pin of the dual-channel comparator U35 is connected to the base of the first transistor Q3 through a diode, turning on the first transistor Q3 and outputting an overvoltage or undervoltage protection signal.

[0034] Fault summary circuit 42: Includes a multi-input logic processing unit 421, an isolated output unit 422, and an OR gate output unit 423. The multi-input logic processing unit 421 uses a CMOS AND gate element 421a, with its first input pin connected to overvoltage and undervoltage protection signals, and its second input pin connected to multiple sets of three-phase fault signals. The isolated output unit has an optocoupler 422a, whose input is connected to the output of the CMOS AND gate element 421a, and whose output is connected to the OR gate output unit 423, thus cutting off the electrical connection between the logic processing unit and the OR gate unit and suppressing common-mode interference. The OR gate output unit 423 uses a dual-input OR gate element 423a, whose first input pin receives the fault signal output by the isolated output unit, and its second input pin receives the manual fault trigger signal (first fault signal) from the control module. The output logic OR result serves as the fault summary signal, used to block the PWM output.

[0035] PWM feedback acquisition circuit 43: It is equipped with a dual-channel optocoupler 431. The output terminal of the power module under test is connected to the control module 3 through the dual-channel optocoupler 431. The PWM signal output by the power module under test is converted into a TTL level signal that can be received by the control module 3. The output of the optocoupler is connected to the IO port of the main control chip 311.

[0036] Adapter 5: The drive module 3 and the power module under test are connected via adapter 5. The adapter includes a temperature sensor interface 51, a PWM signal and control interface 52, a PWM input and feedback interface 53, and a fault output interface 54, which realizes signal transmission and power connection between the drive module 3 and the power module under test.

[0037] Reserved connector interface 6: The test circuit also includes a reserved connector interface 6 for measuring power modules with different interfaces. By adding a DB interface adapter board, different types of power modules can be adapted, improving the versatility of the test circuit.

[0038] The 1MW three-level power module test circuit of this invention achieves rapid testing, fault detection and signal processing of the power module through the coordinated work of the above modules, solving the problems of large size and high cost of existing test fixtures, and has good practicality and promotion value.

Claims

1. A test circuit for a 1MW three-level power module, characterized in that, It includes a power supply module (1), a drive module (2), a control module (3), and a fault feedback module (4); the power supply module (1) supplies power to the drive module (2), the control module (3), and the fault feedback module (4); the output of the control module (3) is connected to an external power module under test through the drive module (2) and communicates with an external host computer, and receives signals from the fault feedback module (4); the fault feedback module (4) is connected to the output of the external power module under test through an adapter (5), and the output of the fault feedback module (4) is connected to the input of the control module (3).

2. The 1MW three-level power module test circuit according to claim 1, characterized in that, The power module (1) includes: The reverse connection protection circuit (11) is connected to an external input power supply at its input terminal and outputs an isolated 15V power supply through a PMOS transistor (111) to prevent the external input power supply from being reversed and to supply power to the drive module (2). The first power chip circuit (12) is connected to the output terminal of the reverse connection protection circuit (11) and is used to convert the isolated 15V power supply into a non-isolated 5V power supply for use by the non-isolated parts of the drive module (2), control module (3) and fault feedback module (4). The first linear regulator circuit (13) is connected to the output terminal of the reverse connection protection circuit (11) to convert the isolated 15V power supply into an isolated 5V power supply for use by the circuits in the fault feedback module (4) that require electrical isolation. The second linear regulator circuit (14) is connected to the output terminal of the first power chip circuit (12) and is used to convert the non-isolated 5V power supply into a non-isolated 3.3V power supply to power the control module (3). The second power chip circuit (15) is connected to the output terminal of the first linear regulator circuit (13) to convert the non-isolated 5V power supply into an isolated 1.5V power supply so as to realize anti-interference communication between the control module (3) and the external host computer.

3. The 1MW three-level power module test circuit according to claim 1, characterized in that, The driving module (2) includes: The buffer chip (21) has its input terminal connected to the PWM signal output terminal of the control module, and is used to convert the PWM signal output by the control module into an intermediate level signal. An inverter (22) is connected to the output of the buffer chip and is used to invert the intermediate level signal. A high-speed dual-channel optocoupler (23) has its input end connected to the output end of the inverter and its output end connected to the power module under test. It is used to electrically isolate the intermediate level signal after inversion and convert it into a drive level signal that is compatible with the power module under test.

4. The 1MW three-level power module test circuit according to claim 1, characterized in that, The control module (3) includes: The main control chip circuit (31) includes a main control chip (311) of model XC6SLX9-2TQG144, which is used to output multiple PWM signals to the drive module (2) and receive the fault feedback signal from the fault feedback module (4); The fiber optic transceiver circuit (32) includes a fiber optic transmitter (321), a fiber optic receiver (322), and a driver chip (323). The fiber optic transmitter (321) is connected to the transmitting interface of the main control chip (311) via the driver chip (323), and the fiber optic receiver (322) is connected to the receiving interface of the main control chip via the driver chip (323). It is used to realize high-speed optical communication between the control module (3) and the external host computer. The isolation circuit (33) includes an isolation transceiver (331) connected to the main control chip (311) for implementing differential signal isolation communication between the control module (3) and external devices.

5. A 1MW three-level power module test circuit according to claim 1, characterized in that, The fault feedback module (4) includes a voltage detection circuit (41), a fault summary circuit (42), and a PWM feedback acquisition circuit (43), which are used to monitor the key point voltage inside the power module under test and the fault signal of the power module under test, and block the PWM output to protect the circuit when there is an abnormality.

6. A 1MW three-level power module test circuit according to claim 2, characterized in that, The fault feedback module (4) includes a voltage detection circuit (41), which includes: a dual-channel comparator U35, a first sampling resistor R97, a second sampling resistor R102, a third sampling resistor R99, an overvoltage threshold divider resistor R96, an overvoltage threshold adjustment resistor R94, an undervoltage threshold divider resistor R93, an undervoltage threshold adjustment resistor R87, a first grounding resistor R100, a second grounding resistor R103, a first diode D1, a second diode D2, a first transistor Q3, a first bias resistor R98, a second bias resistor R101, and a filter capacitor C22. The output terminal of the isolated 15V power supply is connected to one end of the second sampling resistor R102 through the first sampling resistor R97, and the other end of the second sampling resistor R102 is grounded. The connection node between the first sampling resistor R97 and the second sampling resistor R102 is connected to the first channel positive input pin and the second channel negative input pin of the dual-channel comparator U35 through the third sampling resistor R99, which is used to form the sampling voltage input branch. The output terminal of the isolated 5V power supply is connected to the common terminal of the parallel overvoltage threshold adjustment resistor R94 and the overvoltage threshold voltage divider resistor R96. The other end of the overvoltage threshold adjustment resistor R94 and the other end of the overvoltage threshold voltage divider resistor R96 are connected to the first terminal of the first grounding resistor R100, and the second terminal of the first grounding resistor R100 is grounded. The connection node of the overvoltage threshold adjustment resistor R94, the overvoltage threshold voltage divider resistor R96 and the first grounding resistor R100 is connected to the first channel inverting input pin of the dual-channel comparator U35 to form an overvoltage threshold voltage generation circuit. The output terminal of the isolated 5V power supply is connected to the common terminal of the parallel undervoltage threshold adjustment resistor R87 and undervoltage threshold voltage divider resistor R93. The other end of the undervoltage threshold adjustment resistor R87 and the other end of the undervoltage threshold voltage divider resistor R93 are connected to the first terminal of the second grounding resistor R103, and the second terminal of the second grounding resistor R103 is grounded. The connection node of the undervoltage threshold adjustment resistor R87, the undervoltage threshold voltage divider resistor R93 and the second grounding resistor R103 is connected to the second channel positive input pin of the dual-channel comparator U35 to form an undervoltage threshold voltage generation circuit. The first channel output pin of the dual-channel comparator U35 is connected to the base of the first transistor Q3 through the first diode D1, and the second channel output pin is connected to the base of the first transistor Q3 through the second diode D2; the collector of the first transistor Q3 serves as the output terminal of the voltage detection circuit (41) and is used to output overvoltage and undervoltage protection signals.

7. A 1MW three-level power module test circuit according to claim 6, characterized in that, The control module (3) outputs a fault signal as the first fault signal based on the fault command from the external host computer; the fault feedback module (4) further includes a fault aggregation circuit (42), which is equipped with: The multi-input logic processing unit (421) is used to summarize the overvoltage and undervoltage protection signals and multiple sets of three-phase fault signals. It includes a CMOS AND gate element (421a), which has a first fault input terminal (T1) for receiving the overvoltage and undervoltage protection signals and multiple second fault input terminals (T2) for receiving multiple sets of three-phase fault signals from an external power module under test. An isolation output unit (422) is used to electrically isolate the aggregated overvoltage and undervoltage protection signals and multiple sets of three-phase fault signals output by the multi-input logic processing unit (421) to output a second fault signal. The isolation output unit (422) includes an optocoupler (422a). The input terminal of the optocoupler (422a) is connected to the output terminal of the CMOS AND gate element (421a), and the output terminal of the optocoupler (422a) is connected to an OR gate output unit (423). This disconnects the electrical connection between the multi-input logic processing unit (421) and the OR gate output unit (423) to suppress common-mode interference. OR gate output unit (423) includes a dual-input OR gate element (423a), which is provided with a first signal receiving terminal (T3) for receiving the first fault signal, a second signal receiving terminal (T4) for receiving the second fault signal, and a fault output terminal (SO) connected to the control module (3) and outputting a fault summary signal to block the PWM output.

8. A 1MW three-level power module test circuit according to claim 5, characterized in that, The fault feedback module (4) also includes a PWM feedback acquisition circuit (43), which is equipped with a dual-channel optocoupler (431). The output terminal of the power module under test is connected to the control module (3) through the dual-channel optocoupler (431) to convert the PWM signal output by the power module under test into a TTL level signal that can be received by the control module (3).

9. A 1MW three-level power module test circuit according to claim 1, characterized in that, The adapter (5) includes a temperature sensor interface (51), a drive PWM output interface (52), a module PWM feedback interface (53), and a fault output interface (54).

10. A 1MW three-level power module test circuit according to claim 1, characterized in that, It also includes a reserved connector interface (6) for measuring external power modules under test with different interfaces.

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