Relay control circuit

Abstract

The utility model provides a relay control circuit, this circuit includes: processor, the processor is used for when closing relay, voltage switch signal and relay switch signal are high simultaneously with being placed, after the relay closure preset time length, voltage switch signal is placed as low level, when disconnecting the relay, relay switch signal is placed as low level, voltage control circuit, when voltage switch signal is high, output first voltage, when voltage switch signal is low, output second voltage, relay control circuit is used for when relay switch signal is high, control relay closes, when relay switch signal is low, control relay disconnects. The utility model under the premise of guaranteeing single coil non - holding type relay reliable attraction, significantly reduce its maintenance power consumption.

Description

Technical Field

[0001] This utility model relates to the field of relay technology, and in particular to a relay control circuit. Background Technology

[0002] Ordinary single-coil, non-holding relays require a continuous application of the rated voltage (such as 12V) to maintain the energized state, which causes the relay coil to heat up for a long time and consumes a lot of power.

[0003] Directly reducing the voltage that keeps the relay engaged may cause contact bounce or release due to insufficient engaging force. Using PWM (Pulse Width Modulation) for real-time voltage regulation can easily generate electromagnetic interference, and the coil inductance can cause current pulsation, potentially leading to contact vibration. While magnetic latching relays are energy-efficient, they are expensive, have complex control logic, and their state is uncertain after power failure. Summary of the Invention

[0004] To address the problems existing in the prior art, this utility model provides a relay control circuit that significantly reduces the holding power consumption of a single-coil non-holding relay while ensuring reliable engagement, and avoids PWM interference and the control complexity of magnetic latching relays.

[0005] This utility model provides a relay control circuit, including:

[0006] The processor controls the output voltage switch signal and the relay switch signal. When the relay is closed, both the voltage switch signal and the relay switch signal are simultaneously set to a high level. After the relay has been closed for a preset time, the voltage switch signal is then set to a low level. When the relay is opened, the relay switch signal is set to a low level.

[0007] A voltage control circuit is provided, wherein the input terminal of the voltage control circuit is connected to the output terminal of the processor, and the output terminal of the voltage control circuit is connected to the relay. The voltage control circuit is used to output a first voltage when the voltage switch signal is high and to output a second voltage when the voltage switch signal is low. The voltage value of the first voltage is greater than the voltage value of the second voltage. The first voltage is the rated voltage of the relay, and the second voltage is within the coil sustaining voltage range of the relay.

[0008] A relay control circuit is provided, wherein the input terminal of the relay control circuit is connected to the output terminal of the processor, and the output terminal of the relay control circuit is connected to the relay. The relay control circuit is used to control the relay to close when the relay switch signal is high level, and to control the relay to open when the relay switch signal is low level.

[0009] According to the present invention, a relay control circuit is provided, wherein the processor is used to control the output voltage switching signal through a first IO interface and to control the output relay switching signal through a second IO interface;

[0010] The input terminal of the voltage control circuit is connected to the first IO interface, and the input terminal of the relay control circuit is connected to the second IO interface.

[0011] According to the present invention, a relay control circuit is provided, the voltage control circuit comprising:

[0012] The transistor has its base connected to the first IO interface and its emitter grounded.

[0013] The PMOS transistor has its gate (G) connected to the collector of the transistor and the wire for the first voltage, its source (S) grounded, and its drain (D) connected to the output terminal of the voltage control circuit.

[0014] A diode, the input terminal of which is connected to the wire of the second voltage, and the output terminal of which is connected to the output terminal of the voltage control circuit.

[0015] According to the relay control circuit provided by this utility model, when the voltage switch signal is high level, both the transistor and the PMOS transistor are turned on, and the output terminal of the voltage control circuit outputs the first voltage.

[0016] According to the relay control circuit provided by this utility model, when the voltage switch signal is low, both the transistor and the PMOS transistor are turned off, and the output terminal of the voltage control circuit outputs the second voltage.

[0017] According to the present invention, a relay control circuit includes:

[0018] The NMOS transistor has its drain (D) connected to the relay, its gate (G) connected to the second I / O interface, and its source (S) grounded.

[0019] According to the relay control circuit provided by this utility model, when the voltage switch signal and the relay switch signal are both set to high level, the NMOS transistor is turned on, the coil voltage of the relay is the first voltage, and the K3 contact of the relay is closed.

[0020] According to the relay control circuit provided by this utility model, after the relay is closed for a preset time, when the voltage switch signal is set to a low level, the NMOS transistor is turned on, the coil voltage of the relay is the second voltage, and the K3 contact of the relay continues to be energized.

[0021] According to the relay control circuit provided by this utility model, when the relay switch signal is set to a low level, the Nmos transistor is turned off and the K3 of the relay is disconnected.

[0022] The relay control circuit provided by this utility model automatically switches the coil voltage of the relay to a lower voltage within the coil holding voltage range after the relay is closed under rated voltage and a certain delay. Under the premise of ensuring reliable engagement of the single-coil non-holding relay, it significantly reduces its holding power consumption, reduces heat generation and extends the life of the device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the relay control circuit provided by this utility model;

[0025] Figure 2 This is a schematic diagram of the voltage control circuit in the relay control circuit provided by this utility model;

[0026] Figure 3 This is a schematic diagram of the structure of the relay control circuit provided by this utility model. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0028] The following is combined with Figure 1 This invention describes a relay control circuit, comprising:

[0029] The processor controls the output voltage switch signal and the relay switch signal. When the relay is closed, both the voltage switch signal and the relay switch signal are simultaneously set to a high level. After the relay has been closed for a preset time, the voltage switch signal is then set to a low level. When the relay is opened, the relay switch signal is set to a low level.

[0030] A voltage control circuit is provided, wherein the input terminal of the voltage control circuit is connected to the output terminal of the processor, and the output terminal of the voltage control circuit is connected to the relay. The voltage control circuit is used to output a first voltage when the voltage switch signal is high and to output a second voltage when the voltage switch signal is low. The first voltage is the rated voltage of the relay, and the second voltage is within the coil sustaining voltage range of the relay.

[0031] A relay control circuit is provided, wherein the input terminal of the relay control circuit is connected to the output terminal of the processor, and the output terminal of the relay control circuit is connected to the relay. The relay control circuit is used to control the relay to close when the relay switch signal is high level, and to control the relay to open when the relay switch signal is low level.

[0032] The relay control circuit in this embodiment can be applied to relays in new energy household storage integrated machines, or to relays in other devices.

[0033] The processor can be a CPU (Central Processing Unit) or an MCU (Microcontroller Unit).

[0034] The coil sustaining voltage range of a relay can be obtained from the relay's datasheet. For example, the rated voltage of a certain ALFG2PF121 relay is 12V, and the coil sustaining voltage range is 45% to 80% of the rated voltage, i.e., 5.4V to 9.6V.

[0035] The first voltage can be set to 12V, and the second voltage to 6.8V. The dual voltage channel is designed so that after the relay is energized, there is a preset delay, such as 2 seconds, before the coil voltage is switched from 12V to 6.8V, reducing power consumption by about 68% ((122-6.82) / 122≈68%).

[0036] like Figure 1As shown, the CPU controls the 12V voltage switch signal and the relay switch signal through two I / O interfaces. When the relay needs to close, both the 12V voltage switch signal and the relay switch signal are simultaneously set to high level. The 12V voltage passes sequentially through the voltage control circuit (12V control MOS), the relay coil, and the relay control circuit (relay control MOS) to the power ground, causing the relay contacts to close. After a 5-second delay, the 12V switch signal is then set low, the 12V control MOS is opened, and the relay coil's holding voltage becomes 6.8V.

[0037] This embodiment is a voltage-switchable conventional relay control circuit. A delay switching module automatically switches the coil drive voltage from 12V to 6.8V after the relay is energized. While ensuring reliable energization, it reduces power consumption by 68%, significantly reducing heat generation and extending device lifespan.

[0038] This embodiment automatically switches the relay coil voltage to a lower voltage within the coil holding voltage range after a certain delay after the relay closes at the rated voltage. This significantly reduces the holding power consumption, reduces heat generation, and extends the device life while ensuring reliable engagement of the single-coil non-holding relay.

[0039] Based on the above embodiments, such as Figure 2 and Figure 3 As shown, in this embodiment, the processor is used to control the output voltage switch signal RELAY12V_ON through the first IO interface and to control the output relay switch signal GRID_REALY_L2_M through the second IO interface;

[0040] The input terminal of the voltage control circuit is connected to the first IO interface, and the input terminal of the relay control circuit is connected to the second IO interface.

[0041] Based on the above embodiments, such as Figure 2 As shown, the voltage control circuit in this embodiment includes:

[0042] Transistor Q6, the base D of transistor Q6 is connected to the first IO interface, and the emitter E of transistor is grounded;

[0043] Pmos transistor Q5, the gate of Pmos transistor Q5 is connected to the collector C of the transistor and the +12V_BUS wire of the first voltage, the source of Pmos transistor is grounded, and the drain of Pmos transistor is connected to the output terminal REALY_12V of the voltage control circuit.

[0044] Diode D12, the input terminal of which is connected to the wire of the second voltage +6.8V_L, and the output terminal of which is connected to the output terminal of the voltage control circuit REALY_12V.

[0045] Based on the above embodiments, in this embodiment, when the voltage switch signal RELAY12V_ON is high, both transistor Q6 and PMOS transistor Q5 are turned on, the gate of PMOS transistor Q5 is pulled low, the gate-gate voltage is -12V, and the output terminal REALY_12V of the voltage control circuit outputs the first voltage (e.g., 12V).

[0046] Based on the above embodiments, in this embodiment, when the voltage switch signal RELAY12V_ON is low, both transistor Q6 and PMOS transistor Q5 are turned off, the gate of PMOS transistor Q5 is pulled to 12V, and the output terminal REALY_12V of the voltage control circuit outputs the second voltage (e.g., 6.8V).

[0047] Based on the above embodiments, such as Figure 3 As shown, the relay control circuit in this embodiment includes:

[0048] NMOS transistor Q7, the drain (D) of NMOS transistor Q7 is connected to the relay, the gate (G) of NMOS transistor Q7 is connected to the second IO interface, and the source (S) of NMOS transistor Q7 is grounded.

[0049] Based on the above embodiments, in this embodiment, when the voltage switch signal RELAY12V_ON and the relay switch signal GRID_REALY_L2_M are both set to high level, the NMOS transistor Q7 is turned on, the coil voltage of the relay is the first voltage (e.g., 12V), and the K3 contact of the relay is closed.

[0050] Based on the above embodiments, in this embodiment, after the relay is closed for a preset time (e.g., 2s), when the voltage switch signal is set to RELAY12V_ON at a low level, the NMOS transistor Q7 is turned on, the coil voltage of the relay is the second voltage (e.g., 6.8V), and the K3 contact of the relay continues to be energized.

[0051] Based on the above embodiments, in this embodiment, when the relay switch signal GRID_REALY_L2_M is set to a low level, the Nmos transistor Q7 is turned off and the relay K3 is disconnected.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A relay control circuit, characterized in that, include: The processor controls the output voltage switch signal and the relay switch signal. When the relay is closed, both the voltage switch signal and the relay switch signal are simultaneously set to a high level. After the relay has been closed for a preset time, the voltage switch signal is then set to a low level. When the relay is opened, the relay switch signal is set to a low level. A voltage control circuit is provided, wherein the input terminal of the voltage control circuit is connected to the output terminal of the processor, and the output terminal of the voltage control circuit is connected to the relay. The voltage control circuit is used to output a first voltage when the voltage switch signal is high and to output a second voltage when the voltage switch signal is low. The voltage value of the first voltage is greater than the voltage value of the second voltage. The first voltage is the rated voltage of the relay, and the second voltage is within the coil sustaining voltage range of the relay. A relay control circuit is provided, wherein the input terminal of the relay control circuit is connected to the output terminal of the processor, and the output terminal of the relay control circuit is connected to the relay. The relay control circuit is used to control the relay to close when the relay switch signal is high level, and to control the relay to open when the relay switch signal is low level.

2. The relay control circuit according to claim 1, characterized in that, The processor is used to control the output voltage switching signal through the first IO interface and to control the output relay switching signal through the second IO interface; The input terminal of the voltage control circuit is connected to the first IO interface, and the input terminal of the relay control circuit is connected to the second IO interface.

3. The relay control circuit according to claim 2, characterized in that, The voltage control circuit includes: The transistor has its base connected to the first IO interface and its emitter grounded. The PMOS transistor has its gate (G) connected to the collector of the transistor and the wire for the first voltage, its source (S) grounded, and its drain (D) connected to the output terminal of the voltage control circuit. A diode, the input terminal of which is connected to the wire of the second voltage, and the output terminal of which is connected to the output terminal of the voltage control circuit.

4. The relay control circuit according to claim 3, characterized in that, When the voltage switch signal is high, both the transistor and the PMOS transistor are turned on, and the output terminal of the voltage control circuit outputs the first voltage.

5. The relay control circuit according to claim 3, characterized in that, When the voltage switch signal is low, both the transistor and the PMOS transistor are turned off, and the output terminal of the voltage control circuit outputs the second voltage.

6. The relay control circuit according to claim 2, characterized in that, The relay control circuit includes: The NMOS transistor has its drain (D) connected to the relay, its gate (G) connected to the second I / O interface, and its source (S) grounded.

7. The relay control circuit according to claim 6, characterized in that, When the voltage switch signal and the relay switch signal are both set to high level, the NMOS transistor is turned on, the coil voltage of the relay is the first voltage, and the K3 contact of the relay is closed.

8. The relay control circuit according to claim 6, characterized in that, After the relay has been closed for a preset period of time, when the voltage switch signal is set to a low level, the NMOS transistor is turned on, the coil voltage of the relay is the second voltage, and the K3 contact of the relay continues to be engaged.

9. The relay control circuit according to claim 6, characterized in that, When the relay switch signal is set to low level, the Nmos transistor is turned off, and the K3 of the relay is disconnected.

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