An oscillator circuit and an isolated driving chip using the same

Abstract

The application relates to the technical field of chips, in particular to an oscillator circuit and an isolated driving chip applying the same, which comprises a first control module, a bias voltage module and a delay module, the first control module is connected to the bias voltage module, the bias voltage module is connected to the delay module, the delay module is connected to a second control module, and the second control module is used for connecting an external under-voltage protection module; when the first control module receives external bias current and the bias voltage module connects an external power supply end VCC, the bias voltage module outputs voltage for the delay module, and the second control module feeds back to the delay module after receiving the voltage output by the under-voltage protection module to generate oscillation. The application has the effect of improving the oscillation frequency.

Description

Technical Field

[0001] This application relates to the technical field of chips, and in particular to an oscillator circuit and an isolated driver chip using this circuit. Background Technology

[0002] In power electronics systems and industrial automation, isolation driver chips serve as core components connecting low-voltage control terminals and high-voltage power terminals. Their performance directly determines the system's reliability, response speed, and electromagnetic compatibility. The core function of isolation driver chips is to safely transmit control signals to the high-voltage side through electrical isolation, while simultaneously enabling rapid switching of signals.

[0003] An oscillator is required in isolation driver chips. However, the low frequency of oscillators in existing technologies limits the input signal frequency of the isolation driver chip. Therefore, an oscillator circuit is urgently needed to improve the performance of the isolation driver. Summary of the Invention

[0004] To improve the oscillation frequency, this application provides an oscillator circuit and an oscillator using this circuit.

[0005] Firstly, the oscillator circuit provided in this application adopts the following technical solution: An oscillator circuit includes a first control module, a bias voltage module, and a delay module. The first control module is connected to the bias voltage module, the bias voltage module is connected to the delay module, and the delay module is connected to a second control module. The second control module is used to connect to an external undervoltage protection module. When the first control module receives an external bias current and the bias voltage module is connected to the external power supply terminal VCC, the bias voltage module outputs a voltage for the delay module to use. After receiving the voltage output by the undervoltage protection module, the second control module feeds it back to the delay module to generate high-frequency oscillation.

[0006] By adopting the above technical solution, the bias voltage module provides bias voltage. After receiving external bias current, the bias voltage module can output voltage for the delay module to use. Thus, after the second control module receives the voltage output by the protection module, it can realize output feedback to the input stage. Through the action of the delay module, high-frequency oscillation is realized.

[0007] Optionally, the bias voltage module includes PMOS transistors P1, PMOS transistor P2, and NMOS transistor N10. The source of PMOS transistor P1 is connected to the power supply terminal VCC, the drain of PMOS transistor P1 is connected to the first control module, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the source of PMOS transistor P2 is connected to the power supply terminal VCC, the drain of PMOS transistor P2 is connected to the first control module, the drain of PMOS transistor P2 is also connected to the gate of NMOS transistor N10, the drain of NMOS transistor N10 is connected to the power supply terminal VCC, and the source of NMOS transistor N10 is connected to the delay module.

[0008] Optionally, the first control module includes NMOS transistors N1, N2, N3, and N4. The drain of NMOS transistor N1 is connected to the receiving terminal IB, the source of NMOS transistor N1 is connected to the ground terminal, the gate of NMOS transistor N1 is shorted to the drain, the gate of NMOS transistor N1 is also connected to the gate of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the drain of PMOS transistor P1, the source of NMOS transistor N2 is connected to the ground terminal, the source of NMOS transistor N3 is connected to the ground terminal, the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2, the gate of NMOS transistor N3 is connected to the receiving terminal IB, the gate of NMOS transistor N4 is connected to the receiving terminal IB, the source of NMOS transistor N4 is connected to the ground terminal, and the drain of NMOS transistor N4 is connected to the source of NMOS transistor N10.

[0009] Optionally, the delay module includes a first delay module, a second delay module, and a third delay module. The first delay module, the second delay module, and the third delay module are all connected to the bias voltage module. The first delay module is connected to the second control module, the second delay module is connected to the first delay module, the third delay module is connected to the second delay module, and the third delay module is also connected to the second control module.

[0010] Optionally, the first delay module includes a PMOS transistor P3, an NMOS transistor N5, and a resistor R1. The source of the PMOS transistor P3 is connected to the source of the NMOS transistor N10, the gate of the PMOS transistor P3 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the second control module, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the PMOS transistor P3, and the source of the NMOS transistor N5 is connected to ground.

[0011] Optionally, it also includes a resistor R4 for adjusting the rising edge time of the oscillation waveform and a resistor R5 for adjusting the falling edge time of the oscillation waveform. The resistor R4 is disposed at the source of the PMOS transistor P3, one end of the resistor R4 is connected to the source of the PMOS transistor P3, and the other end of the resistor R4 is connected to the source of the NMOS transistor N10. The resistor R5 is disposed at the source of the NMOS transistor N5, one end of the resistor R5 is connected to the source of the NMOS transistor N5, and the other end of the resistor R5 is connected to the ground terminal.

[0012] Optionally, the second delay module includes a PMOS transistor P4, an NMOS transistor N6, and a resistor R2. The source of the PMOS transistor P4 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P4 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the first delay module. The drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N6. The gate of the NMOS transistor N6 is connected to the gate of the PMOS transistor P4. The source of the NMOS transistor N6 is connected to ground.

[0013] Optionally, it also includes a resistor R6 for adjusting the rising edge time of the oscillation waveform and a resistor R7 for adjusting the falling edge time of the oscillation waveform. The resistor R6 is disposed at the source of the PMOS transistor P4, one end of the resistor R6 is connected to the source of the PMOS transistor P4, and the other end of the resistor R6 is connected to the source of the NMOS transistor N10. The resistor R7 is disposed at the source of the NMOS transistor N6, one end of the resistor R7 is connected to the source of the NMOS transistor N6, and the other end of the resistor R7 is connected to the ground terminal.

[0014] Optionally, the third delay module includes a PMOS transistor P5, an NMOS transistor N8, and a resistor R3. The source of the PMOS transistor P5 is connected to the source of the NMOS transistor N10, the gate of the PMOS transistor P5 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the second delay module, the drain of the PMOS transistor P5 is connected to the second control module, the drain of the NMOS transistor N8 is also connected to the second control module, the gate of the NMOS transistor N8 is connected to the gate of the PMOS transistor P4, and the source of the NMOS transistor N8 is connected to ground.

[0015] Secondly, the isolation driver chip provided in this application adopts the following technical solution: An isolation driver chip includes an oscillator circuit as described in the first aspect.

[0016] In summary, this application includes at least one of the following beneficial technical effects: 1. The bias voltage module provides bias voltage. After receiving external bias current, the bias voltage module can output voltage for the delay module to use. Thus, after the second control module receives the voltage output by the protection module, it can realize output feedback to the input stage. Through the action of the delay module, the circuit oscillation is realized. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the circuit connection in this embodiment.

[0018] Explanation of reference numerals in the attached diagram: 1. First control module; 2. Bias voltage module; 3. Second control module; 4. Drive enhancement module. Detailed Implementation

[0019] The following is in conjunction with the appendix Figure 1 This application will be described in further detail.

[0020] This application discloses an oscillator circuit. (Refer to...) Figure 1 An oscillator circuit includes a first control module 1, a bias voltage module 2, and a delay module. The first control module 1 is connected to the bias voltage module 2, the bias voltage module 2 is connected to the delay module, and the delay module is connected to a second control module 3. The second control module 3 is used to connect to an external undervoltage protection module.

[0021] The bias voltage module 2 includes PMOS transistors P1, PMOS transistor P2, and NMOS transistor N10. The source of PMOS transistor P1 is connected to the power supply terminal VCC, the drain of PMOS transistor P1 is connected to the first control module 1, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the source of PMOS transistor P2 is connected to the power supply terminal VCC, the drain of PMOS transistor P2 is connected to the first control module 1, the drain of PMOS transistor P2 is also connected to the gate of NMOS transistor N10, the drain of NMOS transistor N10 is connected to the power supply terminal VCC, and the source of NMOS transistor N10 is connected to the delay module.

[0022] The first control module 1 includes NMOS transistors N1, N2, N3, and N4. The drain of NMOS transistor N1 is connected to the receiving terminal IB, the source of NMOS transistor N1 is connected to the ground terminal, the gate of NMOS transistor N1 is shorted to the drain, the gate of NMOS transistor N1 is also connected to the gate of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the drain of PMOS transistor P1, the source of NMOS transistor N2 is connected to the ground terminal, the source of NMOS transistor N3 is connected to the ground terminal, the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2, the gate of NMOS transistor N3 is connected to the receiving terminal IB, the gate of NMOS transistor N4 is connected to the receiving terminal IB, the source of NMOS transistor N4 is connected to the ground terminal, and the drain of NMOS transistor N4 is connected to the source of NMOS transistor N10.

[0023] The delay module includes a first delay module, a second delay module, and a third delay module. The first delay module, the second delay module, and the third delay module are all connected to the bias voltage module 2. The first delay module is connected to the second control module 3. The second delay module is connected to the first delay module. The third delay module is connected to the second delay module. The third delay module is also connected to the second control module 3.

[0024] Specifically, the first delay module and the second delay module have the same component composition. The first delay module includes a PMOS transistor P3, an NMOS transistor N5, and a resistor R1. The source of the PMOS transistor P3 is connected to a resistor R4, and the other end of the resistor R4 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P3 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the second control module 3. The drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the PMOS transistor P3, and the source of the NMOS transistor N5 is connected to a resistor R5, the other end of which is connected to ground.

[0025] The second delay module includes a PMOS transistor P4, an NMOS transistor N6, and a resistor R2. The source of the PMOS transistor P4 is connected to the resistor R6, and the other end of the resistor R6 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P4 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first delay module. The drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N6, and the gate of the NMOS transistor N6 is connected to the gate of the PMOS transistor P4. The source of the NMOS transistor N6 is connected to a resistor R7, and the other end of the resistor R7 is connected to the ground terminal.

[0026] The third delay module includes a PMOS transistor P5, an NMOS transistor N8, and a resistor R3. The source of the PMOS transistor P5 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P5 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the second delay module. The drain of the PMOS transistor P5 is connected to the second control module 3. The drain of the NMOS transistor N8 is also connected to the second control module 3. The gate of the NMOS transistor N8 is connected to the gate of the PMOS transistor P4. The source of the NMOS transistor N8 is connected to the ground terminal.

[0027] The second control module 3 includes a PMOS transistor P6 and an NMOS transistor N7. The source of PMOS transistor P6 is connected to the source of NMOS transistor N10. The gate of PMOS transistor P6 is connected to the input terminal UVP, which is used to connect to an external undervoltage protection module. The drain of PMOS transistor P6 is connected to the drain of NMOS transistor N7. The source of NMOS transistor N7 is connected to the drain of NMOS transistor N8. The gate of NMOS transistor N7 is connected to the input terminal UVP. The drain of NMOS transistor N7 is also connected to resistor R1.

[0028] Furthermore, the second control module 3 is connected to an output terminal X, and a drive enhancement module 4 is provided between the second control module 3 and the output terminal X. The drive enhancement module 4 includes a PMOS transistor P7 and an NMOS transistor N9. The source of the PMOS transistor P7 is connected to the source of the NMOS transistor N10, the gate of the PMOS transistor P7 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P7 is connected to the drain of the NMOS transistor N9, the gate of the NMOS transistor N9 is connected to the gate of the PMOS transistor P7, the source of the NMOS transistor N9 is connected to the ground terminal, and the gate of the NMOS transistor N9 is connected to the output terminal X.

[0029] The implementation principle of an oscillator circuit according to an embodiment of this application is as follows: A bias voltage module 2 provides a bias voltage to the first control module 1, and a bias current is received at the receiving terminal IB, thereby providing bias current to each branch of the first control module 1. At this time, the source output voltage of the NMOS transistor N10 supplies power to the delay module, the second control module 3, and the drive enhancement module 4. After receiving the voltage output from the undervoltage protection module at the input terminal UVP, the output is fed back to the input stage using the delay module, causing the circuit to generate high-frequency oscillation. The oscillation loop utilizes the junction capacitance of the MOS transistor itself, which reduces the number of capacitors, improves the frequency response, and reduces the circuit's footprint.

[0030] This application also discloses an isolation driver chip. An isolation driver chip includes the aforementioned oscillator circuit.

[0031] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. An oscillator circuit, characterized in that: It includes a first control module (1), a bias voltage module (2), and a delay module. The first control module (1) is connected to the bias voltage module (2), the bias voltage module (2) is connected to the delay module, and the delay module is connected to a second control module (3). The second control module (3) is used to connect to an external undervoltage protection module, and the second control module (3) is also connected to an output terminal X. When the first control module (1) receives the external bias current and the bias voltage module (2) is connected to the external power supply terminal VCC, the bias voltage module (2) outputs a voltage for the delay module to use. The second control module (3) receives the voltage output by the undervoltage protection module and feeds it back to the delay module to generate high-frequency oscillation.

2. The oscillator circuit according to claim 1, characterized in that: The bias voltage module (2) includes PMOS transistors P1, PMOS transistor P2, and NMOS transistor N10. The source of PMOS transistor P1 is connected to the power supply terminal VCC, the drain of PMOS transistor P1 is connected to the first control module (1), the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the source of PMOS transistor P2 is connected to the power supply terminal VCC, the drain of PMOS transistor P2 is connected to the first control module (1), the drain of PMOS transistor P2 is also connected to the gate of NMOS transistor N10, the drain of NMOS transistor N10 is connected to the power supply terminal VCC, and the source of NMOS transistor N10 is connected to the delay module.

3. An oscillator circuit according to claim 2, characterized in that: The first control module (1) includes NMOS transistors N1, N2, N3 and N4. The drain of NMOS transistor N1 is connected to the receiving terminal IB, the source of NMOS transistor N1 is connected to the ground terminal, the gate of NMOS transistor N1 is shorted to the drain, the gate of NMOS transistor N1 is also connected to the gate of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the drain of PMOS transistor P1, the source of NMOS transistor N2 is connected to the ground terminal, the source of NMOS transistor N3 is connected to the ground terminal, the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2, the gate of NMOS transistor N3 is connected to the receiving terminal IB, the gate of NMOS transistor N4 is connected to the receiving terminal IB, the source of NMOS transistor N4 is connected to the ground terminal, and the drain of NMOS transistor N4 is connected to the source of NMOS transistor N10.

4. An oscillator circuit according to claim 2 or 3, characterized in that: The delay module includes a first delay module, a second delay module and a third delay module. The first delay module, the second delay module and the third delay module are all connected to the bias voltage module (2). The first delay module is connected to the second control module (3). The second delay module is connected to the first delay module. The third delay module is connected to the second delay module. The third delay module is also connected to the second control module (3).

5. An oscillator circuit according to claim 4, characterized in that: The first delay module includes a PMOS transistor P3, an NMOS transistor N5, and a resistor R1. The source of the PMOS transistor P3 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P3 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the second control module (3). The drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5. The gate of the NMOS transistor N5 is connected to the gate of the PMOS transistor P3. The source of the NMOS transistor N5 is connected to the ground terminal.

6. An oscillator circuit according to claim 5, characterized in that: It also includes a resistor R4 for adjusting the rising edge time of the oscillation waveform and a resistor R5 for adjusting the falling edge time of the oscillation waveform. The resistor R4 is disposed at the source of the PMOS transistor P3, one end of the resistor R4 is connected to the source of the PMOS transistor P3, and the other end of the resistor R4 is connected to the source of the NMOS transistor N10. The resistor R5 is disposed at the source of the NMOS transistor N5, one end of the resistor R5 is connected to the source of the NMOS transistor N5, and the other end of the resistor R5 is connected to the ground terminal.

7. An oscillator circuit according to claim 4, characterized in that: The second delay module includes a PMOS transistor P4, an NMOS transistor N6, and a resistor R2. The source of the PMOS transistor P4 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P4 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the first delay module. The drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N6. The gate of the NMOS transistor N6 is connected to the gate of the PMOS transistor P4. The source of the NMOS transistor N6 is connected to ground.

8. An oscillator circuit according to claim 7, characterized in that: It also includes a resistor R6 for adjusting the rising edge time of the oscillation waveform and a resistor R7 for adjusting the falling edge time of the oscillation waveform. The resistor R6 is disposed at the source of the PMOS transistor P4, one end of the resistor R6 is connected to the source of the PMOS transistor P4, and the other end of the resistor R6 is connected to the source of the NMOS transistor N10. The resistor R7 is disposed at the source of the NMOS transistor N6, one end of the resistor R7 is connected to the source of the NMOS transistor N6, and the other end of the resistor R7 is connected to the ground terminal.

9. An oscillator circuit according to claim 4, characterized in that: The third delay module includes a PMOS transistor P5, an NMOS transistor N8, and a resistor R3. The source of the PMOS transistor P5 is connected to the source of the NMOS transistor N10. The gate of the PMOS transistor P5 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the second delay module. The drain of the PMOS transistor P5 is connected to the second control module (3). The drain of the NMOS transistor N8 is also connected to the second control module (3). The gate of the NMOS transistor N8 is connected to the gate of the PMOS transistor P4. The source of the NMOS transistor N8 is connected to the ground terminal.

10. An isolation driver chip, characterized in that: Includes an oscillator circuit as described in any one of claims 1 to 9.

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