Sense amplifier circuit and system and memory cell readout method using the same

Abstract

The present invention relates to a sense amplifier circuit and system and a memory cell sensing method using the same, the sense amplifier circuit including: a current mirror circuit unit receiving a bias current from an external bias circuit and mirroring the bias current to a plurality of paths; a reference resistance unit including a reference resistance and an N-type metal oxide semiconductor field effect transistor activating the reference resistance; a pre-charge circuit unit receiving a pre-charge signal and pre-charging a reference bit line connected to the reference resistance based on the pre-charge signal; an amplifier circuit unit sensing cell data of a cell corresponding to a selected fuse using a voltage difference between a resistance of the selected fuse and the reference resistance; and a buffer circuit unit outputting the sensed data, the amplifier circuit unit including a plurality of P-type metal oxide semiconductor field effect transistors, at least one input stage of the plurality of P-type metal oxide semiconductor field effect transistors of the amplifier circuit unit can be electrically connected with a connection resistance.

Description

Technical Field

[0001] This invention relates to a readout amplifier circuit and system, and a method for reading out storage cells using the same.

[0002] More specifically, the present invention relates to a readout amplifier circuit and system and a method for reading out memory cells using the same: readout operation over a wide power supply range can be achieved by using a low reference resistor and ensuring gain through a two-stage operational amplifier circuit, and a low fuse resistance can be sensed to ensure a sense resistance margin and improve yield. Background Technology

[0003] The content described in this section is merely background information for this embodiment and does not constitute prior art.

[0004] Various semiconductor applications incorporate polysilicon fuse one-time programmable (OTP) memory IP, which retains stored information even when no power is supplied, for purposes such as voltage, current, frequency adjustment, and batch / chip ID storage. The readout amplifier circuitry plays a crucial role in reading data from selected cells within this type of memory.

[0005] Existing sense amplifier circuits utilize the fuse unit resistance and the turn-on resistance of a P-type metal-oxide-semiconductor field-effect transistor (PMOS) acting as a pull-up load to implement a voltage divider, and use an inverter to sense the intermediate voltage to read the cell data. However, in this approach, the turn-on resistance of the PMOS transistor falls within the range of the sense drain supply voltage (VDD), and its resistance value varies. Therefore, when using a wide supply range, the following problems and side effects exist: the reference resistance value of the sense amplifier is not constant; it cannot sense low-flush polysilicon fuses, resulting in a decrease in yield; if a large sense current is used for sense operation at a low drain supply voltage, not only will the sense current consumption increase, but the unblown initial fuse may also blow due to continuous Joule thermal stress, raising concerns about long-term reliability; if a high flush voltage is used to ensure a highly flush polysilicon fuse, it will cause device reliability issues, and even if the flush voltage is increased, the wide resistance distribution characteristic cannot be avoided.

[0006] Due to these issues, existing sense amplifier circuits cannot utilize low drain supply voltages or select low sense reference resistors, thus making it impossible to avoid a decrease in read yield. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The problem to be solved by the present invention is to provide a readout amplifier circuit and system and a method for reading out memory cells using the same, which can achieve readout operation over a wide power supply range by using a low reference resistor and ensuring gain through a two-stage operational amplifier circuit, and can also sense a low fuse resistance, thereby ensuring a sensing resistance margin and improving yield.

[0009] Furthermore, the problem to be solved by the present invention is to provide a readout amplifier circuit and system and a method for reading out a memory cell using the same, which adds a connection resistor to the gate input stage of a P-type metal-oxide-semiconductor field-effect transistor (PMOS) included in the amplifier circuit cell, and can also sense a fuse with a low resistance value.

[0010] Furthermore, the problem to be solved by the present invention is to provide a readout amplifier circuit and system, as well as a method for reading out the memory cell using the same, which uses a two-stage operational amplifier and a variable reference resistor to achieve stable readout operation even over a wide power supply range.

[0011] The objectives of this invention are not limited to those described above. Other objectives and advantages of this invention not mentioned herein will be understood through the following description and will become clearer through embodiments of the invention. Furthermore, it will be apparent that the objectives and advantages of this invention can be achieved by the means and combinations thereof pointed out in the claims.

[0012] means for solving problems

[0013] The present invention provides a sense amplifier circuit for selecting and reading cells of a memory cell array, which may include: a current mirror circuit unit for receiving a bias current from an external bias circuit and mirroring the bias current to multiple paths; a reference resistor unit including a reference resistor and an N-type metal-oxide-semiconductor field-effect (NMOS) transistor that activates the reference resistor; a precharge circuit unit for receiving a precharge signal and precharging a reference bit line connected to the reference resistor based on the precharge signal; an amplifier circuit unit for sensing cell data of the cell corresponding to the selected cell using the voltage difference between the resistance of a select fuse corresponding to the selected cell and the reference resistor; and a buffer circuit unit for outputting the sensed data. The amplifier circuit unit may include a plurality of P-type metal-oxide-semiconductor field-effect transistors, at least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors of the amplifier circuit unit being electrically connected to a connection resistor.

[0014] Furthermore, the current mirror circuit unit may include: a first current mirror that mirrors the bias current and provides it to the select fuse; a second current mirror that mirrors the bias current and provides it to the reference resistor unit; a third current mirror that mirrors the bias current and provides it to the first amplifier circuit of the amplifier circuit unit; and a fourth current mirror that mirrors the bias current and provides it to the second amplifier circuit of the amplifier circuit unit.

[0015] Furthermore, the amplifier circuit unit may include: a first amplifier circuit that generates a first amplifier signal by comparing the voltage of an internal bit line electrically connected to the connection resistor and the select fuse and the voltage of a reference bit line electrically connected to the connection resistor and the reference resistor; and a second amplifier circuit that generates a second amplifier signal by amplifying the first amplifier signal.

[0016] Furthermore, the first amplifier circuit may include a first P-type metal-oxide-semiconductor field-effect transistor and a second P-type metal-oxide-semiconductor field-effect transistor, wherein the gate terminals of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor may be electrically connected to a first connection resistor and a second connection resistor, respectively.

[0017] Furthermore, the first connection resistor and the second connection resistor can adjust the gate input voltage of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor upwards.

[0018] Furthermore, the reference resistor unit may include a first reference resistor and a second reference resistor, as well as a first N-type metal-oxide-semiconductor field-effect transistor and a second N-type metal-oxide-semiconductor field-effect transistor that selectively activate the first reference resistor and the second reference resistor, respectively.

[0019] Furthermore, the first N-type metal-oxide-semiconductor field-effect transistor can activate the first reference resistor in response to the first word line signal, and the second N-type metal-oxide-semiconductor field-effect transistor can activate the first reference resistor and the second reference resistor in response to the second word line signal.

[0020] Furthermore, the first reference resistor and the second reference resistor may have different resistance values.

[0021] Furthermore, the pre-charge circuit unit may include at least one P-type metal-oxide-semiconductor field-effect transistor. When the pre-charge signal is activated, the P-type metal-oxide-semiconductor field-effect transistor can be turned on, so that the reference bit line connected to the reference resistor is pre-charged to the power supply voltage.

[0022] Other embodiments of the present invention include a readout amplifier circuit for selecting and reading cells of a memory cell array, which may include: a reference resistor unit including a reference resistor and an N-type metal-oxide-semiconductor field-effect transistor activating the reference resistor; and an amplifier circuit unit that senses cell data of the cell corresponding to the selected cell by utilizing the voltage difference between the resistance of a select fuse corresponding to the selected cell and the reference resistor. The amplifier circuit unit may include a two-stage operational amplifier circuit configuration. The amplifier circuit unit may include a plurality of P-type metal-oxide-semiconductor field-effect transistors, and at least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors of the amplifier circuit unit may be electrically connected to a connection resistor.

[0023] Furthermore, it may include a current mirror circuit unit that receives bias current from an external bias circuit and mirrors the bias current to multiple paths.

[0024] Furthermore, the current mirror circuit unit may include: a first current mirror that mirrors the bias current and provides it to the select fuse; a second current mirror that mirrors the bias current and provides it to the reference resistor unit; a third current mirror that mirrors the bias current and provides it to the first amplifier circuit of the amplifier circuit unit; and a fourth current mirror that mirrors the bias current and provides it to the second amplifier circuit of the amplifier circuit unit.

[0025] Furthermore, the amplifier circuit unit may include: a first amplifier circuit that generates a first amplifier signal by comparing the voltage of an internal bit line electrically connected to the connection resistor and the select fuse and a reference bit line electrically connected to the connection resistor and the reference resistor; and a second amplifier circuit that generates a second amplifier signal by amplifying the first amplifier signal.

[0026] Furthermore, the first amplifier circuit may include a first P-type metal-oxide-semiconductor field-effect transistor and a second P-type metal-oxide-semiconductor field-effect transistor. The gate terminals of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor may be electrically connected to a first connection resistor and a second connection resistor, respectively. The internal bit line may include a node electrically connected to the first connection resistor and the select fuse. The reference bit line may include a node electrically connected to the second connection resistor and the reference resistor.

[0027] Furthermore, the first connection resistor and the second connection resistor can adjust the gate input voltage of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor upwards.

[0028] Furthermore, the reference resistor unit may include a first reference resistor and a second reference resistor, as well as a first N-type metal-oxide-semiconductor field-effect transistor and a second N-type metal-oxide-semiconductor field-effect transistor that selectively activate the first reference resistor and the second reference resistor, respectively.

[0029] Furthermore, the first N-type metal-oxide-semiconductor field-effect transistor can activate the first reference resistor in response to the first word line signal, and the second N-type metal-oxide-semiconductor field-effect transistor can activate the first reference resistor and the second reference resistor in response to the second word line signal.

[0030] A memory cell readout method according to some embodiments of the present invention, performed by a readout amplifier circuit, may include the following steps: selecting a cell included in a memory cell array; precharging a reference bit line connected to a reference resistor included in a reference resistor cell in response to a precharge signal; receiving a bias current from an external bias circuit and mirroring it to multiple paths; selecting at least one of a first reference resistor and a second reference resistor included in the reference resistor cell and connecting the selected reference resistor to the reference bit line; and sensing cell data of the selected cell by means of an amplifier circuit unit using the voltage difference between the resistance of a selection fuse corresponding to the selected cell and the reference resistor, the amplifier circuit unit including a plurality of P-type metal-oxide-semiconductor field-effect transistors, at least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors of the amplifier circuit unit being electrically connected to a connection resistor, the step of sensing cell data including the following steps: generating a first amplifier signal by first amplifying the voltage difference between an internal bit line electrically connected to the resistance of the connection resistor and the resistance of the selection fuse and the reference bit line electrically connected to the connection resistor and the reference resistor; and generating a second amplifier signal by second amplifying the first amplifier signal.

[0031] Furthermore, the step of connecting the selected reference resistor to the reference bit line may include the following steps: when the first reference resistor is selected, the first N-type metal-oxide-semiconductor field-effect transistor included in the reference resistor unit activates the first reference resistor in response to the first word line signal; when the first reference resistor and the second reference resistor are selected, the second N-type metal-oxide-semiconductor field-effect transistor included in the reference resistor unit activates the first reference resistor and the second reference resistor in response to the second word line signal.

[0032] Furthermore, in the step of sensing unit data, a first logic value can be generated when the voltage of the internal bit line is lower than the voltage of the reference bit line, and a second logic value can be generated when the voltage of the internal bit line is higher than the voltage of the reference bit line.

[0033] The effects of the invention

[0034] The readout amplifier circuit and system of some embodiments of the present invention, as well as the memory cell readout method thereunder, can achieve readout operation over a wide power supply range by using a low reference resistor and ensuring gain through a two-stage operational amplifier circuit, and can also sense a low fuse resistance, thereby ensuring a sense resistance margin and improving yield.

[0035] Furthermore, the readout amplifier circuit and system of some embodiments of the present invention, as well as the memory cell readout method thereunder, have a novel effect of also being able to sense fuses with low resistance values ​​by adding a connection resistor to the gate input stage of the P-type metal-oxide-semiconductor field-effect transistor included in the amplifier circuit cell.

[0036] Furthermore, the readout amplifier circuit and system of some embodiments of the present invention, as well as the memory cell readout method thereunder, use a two-stage operational amplifier and a variable reference resistor to achieve stable readout operation even over a wide power supply range.

[0037] In addition to the above, the specific effects of the present invention will be described below while explaining the specific implementation methods. Attached Figure Description

[0038] Figure 1 This is a block diagram of a readout amplifier system according to some embodiments of the present invention.

[0039] Figure 2 The present invention provides circuit diagrams of readout amplifier systems according to some embodiments of the present invention.

[0040] Figure 3 This is a block diagram of a readout amplifier circuit according to some embodiments of the present invention.

[0041] Figure 4The circuit diagram is provided to illustrate the current mirror circuit unit, reference resistor unit, and precharge circuit unit of the readout amplifier circuit in some embodiments of the present invention.

[0042] Figure 5 The present invention is illustrated by a circuit diagram of an amplifier circuit unit, a connecting resistor, and a buffer circuit unit for a readout amplifier circuit according to some embodiments of the present invention.

[0043] Figure 6 Timing diagrams of the readout amplifier circuits of some embodiments of the present invention are shown. Detailed Implementation

[0044] The terms or words used in this specification and the claims should not be limited to their conventional or dictionary meanings. Rather, they should be defined appropriately by the inventor to best illustrate their invention, in accordance with the meaning and concept of the technical idea of ​​this invention. Furthermore, the embodiments and structures shown in the accompanying drawings are merely one embodiment of the invention and do not represent the entirety of the technical idea. Therefore, it should be understood that at the time of filing this application, there may be various equivalent technical solutions and examples of variations and applications that can replace these.

[0045] The terms "first," "second," "A," and "B," as used in this specification and the claims of the invention, can be used to describe various structural elements, but the structural elements should not be limited by these terms. These terms are used only to distinguish a structural element from other structural elements. For example, without departing from the scope of the invention, a first structural element can be named a second structural element, and similarly, a second structural element can be named a first structural element. The term "and / or" includes a combination of multiple related descriptions or one of multiple related descriptions.

[0046] The terminology used in this specification and the claims is for illustrative purposes only and is not intended to limit the invention. Unless the context clearly indicates otherwise, singular expressions include plural expressions. Terms such as "comprising" or "having" in this application should be understood as not precluding the presence or additional possibilities of features, numbers, steps, operations, structural elements, components, or combinations thereof described in the specification.

[0047] Unless otherwise defined, all terms, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0048] Commonly used terms, such as those defined in dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this application. Furthermore, each structure, process, step, or method included in each embodiment of the invention may be shared to the extent that they are not technically contradictory.

[0049] The following will refer to Figures 1 to 6 This invention will be used to illustrate some embodiments of the readout amplifier circuit and system, as well as the method for reading out the memory cell using the same.

[0050] Figure 1 This is a block diagram of a readout amplifier system according to some embodiments of the present invention. Figure 2 The present invention provides circuit diagrams of readout amplifier systems according to some embodiments of the present invention.

[0051] Reference Figure 1 and Figure 2 The read sense amplifier system 1 in some embodiments of the present invention may include an external bias circuit 100, a memory cell array 200, and a read sense amplifier circuit 300.

[0052] The external bias circuit 100 can provide a bias current (Ibias) to the sense amplifier circuit 300. In other words, the sense amplifier circuit 300 can receive a bias current (Ibias) from the external bias circuit 100. In this case, the bias current (Ibias) can also be referred to as the reference current. On the other hand, the external bias circuit 100 can be a circuit designed to be insensitive to changes in the power supply voltage VDD.

[0053] The memory cell array 200 may include multiple memory cells. In this case, the memory cells may include polysilicon fuse cells. In other words, the memory cell array 200 may include an array of polysilicon fuse cells. In this case, the data stored in one polysilicon fuse cell included in the memory cell array 200 can be read out by the readout amplifier circuit 300.

[0054] The sense amplifier circuit 300 can perform a data readout process on one of the memory cells included in the memory cell array 200 using the bias current (Ibias) received from the external bias circuit 100. In other words, the sense amplifier circuit 300 can read out the data stored in a polysilicon fuse cell included in the memory cell array 200 using the bias current (Ibias) received from the external bias circuit 100.

[0055] As examples, the sense amplifier circuit 300 can select the memory cell to be read from a plurality of memory cells included in the memory cell array 200, and read the data stored in the memory cell by comparing the data of the selected memory cell with a reference resistor.

[0056] In this configuration, the sense amplifier circuit 300 can mirror the bias current (Ibias) to multiple paths, calculate and amplify the difference between the voltage value of the selected fuse corresponding to the selected memory cell and the voltage value of the reference resistor, and read the data stored in the memory cell based on the amplification result. In this configuration, the input stage of the P-type metal-oxide-semiconductor field-effect transistor in the amplifier circuit unit of the sense amplifier circuit 300 can be connected to a connection resistor.

[0057] The following will refer to Figures 3 to 6 The operation of the readout amplifier circuit 300 in some embodiments of the present invention will be described in more detail below.

[0058] Figure 3 This is a block diagram of a readout amplifier circuit according to some embodiments of the present invention. Figure 4 The circuit diagram is provided to illustrate the current mirror circuit unit, reference resistor unit, and precharge circuit unit of the readout amplifier circuit in some embodiments of the present invention. Figure 5 The present invention is illustrated by a circuit diagram of an amplifier circuit unit, a connecting resistor, and a buffer circuit unit for a readout amplifier circuit according to some embodiments of the present invention.

[0059] Reference Figures 1 to 5 In some embodiments of the present invention, the readout amplifier circuit 300 may include a current mirror circuit unit 310, a reference resistor unit 320, a pre-charge circuit unit 330, an amplifier circuit unit 340 including a first amplifier circuit 341 and a second amplifier circuit 342, a connection resistor 345, and a buffer circuit unit 350. However, the embodiments of the present invention are not limited thereto, and may be omitted. Figures 3 to 5 The current mirror circuit unit 310, reference resistor unit 320, precharge circuit unit 330, amplifier circuit unit 340, connection resistor 345, and buffer circuit unit 350 shown are used for implementation, or it can be implemented by including in the readout amplifier circuit 300. Figures 3 to 5 Other structures not shown in the diagram are used to implement this.

[0060] As an example, although not in Figures 3 to 5As shown in the figure, but in some embodiments of the present invention, the readout amplifier circuit 300 may also include a selection unit (not shown) for selecting one of the cells included in the memory cell array 200 as a data readout cell. Hereinafter, for ease of explanation, it will be assumed that one of the cells included in the memory cell array 200 has been selected, and data will be read out using the resistor RFUSE of the selection fuse corresponding to the selected cell.

[0061] The current mirror circuit unit 310 can receive bias current (Ibias) from the external bias circuit 100 and mirror the bias current (Ibias) to multiple paths.

[0062] As examples, the current mirror circuit unit 310 may include: a P-type metal-oxide-semiconductor field-effect transistor PM6 that receives a bias current (Ibias); a first current mirror PM3 that mirrors the bias current (Ibias) and provides it to a selection fuse corresponding to the selected memory cell; a second current mirror PM4 that mirrors the bias current (Ibias) and provides it to a reference resistor unit 320; a third current mirror PM5 that mirrors the bias current (Ibias) and provides it to a first amplifier circuit 341 of the amplifier circuit unit 340; and a fourth current mirror PM7 that mirrors the bias current (Ibias) and provides it to a second amplifier circuit 342 of the amplifier circuit unit 340.

[0063] The reference resistor unit 320 may include circuitry associated with a reference for sensing data in the amplifier circuit unit 340. For example, the reference resistor unit 320 may include a reference resistor RREF and N-type metal-oxide-semiconductor field-effect transistors NM8 and NM9 that activate the reference resistor RREF.

[0064] As examples, the reference resistor unit 320 may include multiple reference resistors RREF and corresponding multiple N-type metal-oxide-semiconductor field-effect transistors NM8 and NM9. For instance, the reference resistor unit 320 may include: a first reference resistor RREF1 and a first N-type metal-oxide-semiconductor field-effect transistor NM9 that activates the first reference resistor RREF1, and a first reference resistor RREF1, a second reference resistor RREF2, and a second N-type metal-oxide-semiconductor field-effect transistor NM8 that activates both the first and second reference resistors RREF2. In this case, the resistance values ​​of the first reference resistor RREF1 and the second reference resistor RREF2 may be different.

[0065] The first N-type metal-oxide-semiconductor field-effect transistor NM9 can activate the first reference resistor RREF1 in response to the first word line signal WL_REF1 applied from an external control unit (e.g., control circuit, control center, etc.), and the second N-type metal-oxide-semiconductor field-effect transistor NM8 can activate the first reference resistor RREF1 and the second reference resistor RREF2 in response to the second word line signal WL_REF2 applied from an external control unit.

[0066] In this case, at least one of the first reference resistor RREF1 and the second reference resistor RREF2 can be selected and utilized. In other words, the sense amplifier circuit 300 of some embodiments of the present invention can selectively utilize at least one of the first reference resistor RREF1 and the second reference resistor RREF2.

[0067] For example, the control unit (e.g., control circuit, control center, etc.) included in the sense amplifier circuit 300 of some embodiments of the present invention can select at least one of the first reference resistor RREF1 and the second reference resistor RREF2, and connect the selected reference resistor RREF to the reference bit line RBL. For example, when the first reference resistor RREF1 is selected and utilized, the control unit included in the sense amplifier circuit 300 of some embodiments of the present invention can activate the first reference resistor RREF1 and connect it to the reference bit line RBL by applying a first word line signal WL_REF1 to the first N-type metal-oxide-semiconductor field-effect transistor NM9, and when the first reference resistor RREF1 and the second reference resistor RREF2 are selected and utilized, the first reference resistor RREF1 and the second reference resistor RREF2 can be activated and connected to the reference bit line RBL by applying a second word line signal WL_REF2 to the second N-type metal-oxide-semiconductor field-effect transistor NM8.

[0068] The precharge circuit unit 330 can receive the precharge signal PCGb and precharge the reference bit line RBL connected to the reference resistor RREF based on the precharge signal PCGb.

[0069] As examples, the precharge circuit unit 330 may include at least one P-type metal-oxide-semiconductor field-effect transistor PM12. For instance, when the precharge signal PCGb is activated, the P-type metal-oxide-semiconductor field-effect transistor PM12 may be turned on, thereby precharging the reference bit line RBL connected to the reference resistor RREF to the power supply voltage VDD.

[0070] Amplifier circuit unit 340 can sense the cell data of the memory cell corresponding to the selected fuse by utilizing the voltage difference between the select fuse resistor RFUSE and the reference resistor RREF. In other words, amplifier circuit unit 340 can perform data readout of the memory cell by comparing the voltage difference between the select fuse resistor RFUSE and the reference resistor RREF.

[0071] As examples, amplifier circuit unit 340 may include two-stage operational amplifier circuitry. For instance, amplifier circuit unit 340 may include a first amplifier circuit 341 and a second amplifier circuit 342.

[0072] The first amplifier circuit 341 generates a first amplifier signal by comparing the voltage between the internal bit line (iBL) connected to the select fuse and the connecting resistor and the reference bit line RBL connected to the reference resistor RREF. In other words, the first amplifier circuit 341 generates a first amplifier signal by amplifying the voltage difference between the internal bit line iBL and the reference bit line RBL connected to both ends of the first amplifier circuit 341.

[0073] In this configuration, the internal bit line iBL may include a first connecting resistor 345a and a node electrically connected to the resistor RFUSE that selects the fuse, and the reference bit line RBL may include a second connecting resistor 345b and a node electrically connected to the reference resistor RREF. In other words, the internal bit line iBL may include the node between the first amplifier circuit 341 and the first connecting resistor 345a, and the reference bit line RBL may include the node between the first amplifier circuit 341 and the second connecting resistor 345b.

[0074] The second amplifier circuit 342 can generate a second amplifier signal by amplifying the first amplifier signal generated from the first amplifier circuit 341.

[0075] On the other hand, the amplifier circuit unit 340 can be electrically connected to the connecting resistor 345. In other words, at least a portion of the plurality of structures included in the amplifier circuit unit 340 can be connected to the connecting resistor 345. In this case, the connecting resistor 345 may include a first connecting resistor 345a and a second connecting resistor 345b.

[0076] As some examples, the first amplifier circuit 341 included in the amplifier circuit unit 340 may be electrically connected to the connecting resistor 345.

[0077] For example, the first amplifier circuit 341 may include a plurality of P-type metal-oxide-semiconductor field-effect transistors PM1, PM2, and PM5, wherein the gate terminals of at least a portion of PM1 and PM2 may be connected to the connecting resistor 345. For example, the first P-type metal-oxide-semiconductor field-effect transistor PM1 included in the first amplifier circuit 341 may be connected to the first connecting resistor 345a, and the second P-type metal-oxide-semiconductor field-effect transistor PM2 included in the first amplifier circuit 341 may be connected to the second connecting resistor 345b.

[0078] In this case, the first connection resistor 345a and the second connection resistor 345b can adjust the gate input voltage of each of the first P-type metal-oxide-semiconductor field-effect transistor PM1 and the second P-type metal-oxide-semiconductor field-effect transistor PM2 upwards. That is, the first connection resistor 345a can adjust the voltage of the internal bit line iBL between the first connection resistor 345a and the first P-type metal-oxide-semiconductor field-effect transistor PM1 upwards relative to the real bit line (BL) connected to the resistor RFUSE of the select fuse, and the second connection resistor 345b can adjust the voltage of the reference bit line RBL between the second connection resistor 345b and the second P-type metal-oxide-semiconductor field-effect transistor PM2 upwards. Thus, even at the low fuse voltage of some embodiments of the present invention, a new effect of being able to read data is achieved.

[0079] On the other hand, the amplifier circuit unit 340 can sense the cell data of the memory cell corresponding to the selection fuse based on the first amplifier circuit 341, the second amplifier circuit 342, and the connection resistor 345 as described above. In other words, the amplifier circuit unit 340 can perform data readout of the memory cell by amplifying and comparing the voltage difference between the resistance RFUSE of the selection fuse, which is adjusted upward by the connection resistor 345, and the reference resistor RREF.

[0080] As an example, when the voltage of the internal bit line iBL is lower than the voltage of the reference bit line RBL, the amplifier circuit unit 340 can generate a first logic value. In this case, the first logic value can indicate that the fuse is in the initial cell. For example, the first logic value can include "0".

[0081] As another example, when the voltage of the internal bit line iBL is higher than the voltage of the reference bit line RBL, the amplifier circuit unit 340 can generate a second logic value. In this case, the second logic value can indicate that the fuse is in a blown state (Blown Cell). For example, the second logic value can include "1".

[0082] The buffer circuit unit 350 can output the unit data generated from the amplifier circuit unit 340 to the outside.

[0083] Figure 6 Timing diagrams of the readout amplifier circuits of some embodiments of the present invention are shown.

[0084] Reference Figure 2 and Figure 6 First, a readout enable signal READb can be applied from the control unit included in the readout amplifier circuit 300. For example, the readout enable signal READb can be applied to the N-type metal-oxide-semiconductor field-effect transistor NM12. In this case, since the N-type metal-oxide-semiconductor field-effect transistor NM12 is in the turn-on state, the current mirror circuit unit 310 can output 0V to the actual bit line BL connected to the resistor RFUSE of the select fuse until the readout enable signal READb and the sense amplification enable signal SAEN are applied.

[0085] Next, a precharge signal PCGb can be applied from the control unit included in the sense amplifier circuit 300. For example, the precharge signal PCGb can be applied to the precharge circuit unit 330. In this case, the reference bit line RBL can be charged to the power supply voltage VDD via the precharge signal PCGb.

[0086] Next, word line signals WL_REF1 and WL_REF2 can be applied from the control unit included in the sense amplifier circuit 300. For example, the first word line signal WL_REF1 can be applied to the first N-type metal-oxide-semiconductor field-effect transistor NM9, and the second word line signal WL_REF2 can be applied to the second N-type metal-oxide-semiconductor field-effect transistor NM8. In this case, the first reference resistor RREF1 can be activated by the first word line signal WL_REF1, and both the first reference resistor RREF1 and the second reference resistor RREF2 can be activated by the second word line signal WL_REF2.

[0087] Next, a sense amplification enable signal SAEN can be applied from the control unit included in the sense amplifier circuit 300. In this case, since the N-type metal-oxide-semiconductor field-effect transistor NM12 is in the turn-on state, the current mirror circuit unit 310 can output 0V to the actual bit line (BL) connected to the resistor RFUSE of the select fuse until the sense enable signal READb and the sense amplification enable signal SAEN are applied.

[0088] Next, a sense amplification enable clock signal SAEN_CLKb can be applied from the control unit included in the sense amplifier circuit 300, and a precharge signal PCGb can be disabled from the control unit included in the sense amplifier circuit 300.

[0089] Next, the unit data is read out through the amplification process of the amplifier circuit unit 340 as described above, thereby the buffer circuit unit 350 can output the sensed unit data as output data DOUT.

[0090] As an example, when the select fuse is in the initial state (Initial Cell), the voltage of the internal bit line iBL will be lower than the voltage of the reference bit line RBL. In this case, the buffer circuit unit 350 outputs the first logic value "0" as the output data DOUT.

[0091] As another example, when the selected fuse is in the blown state (Blown Cell), the voltage of the internal bit line iBL will be higher than the voltage of the reference bit line RBL. In this case, the buffer circuit unit 350 outputs the second logic value "1" as the output data DOUT.

[0092] The above description is merely an illustrative explanation of the technical concept of this embodiment. Those skilled in the art can make various modifications and variations without departing from the essential characteristics of this embodiment. Therefore, this embodiment is not intended to limit the technical concept of this embodiment but is used to describe it; the scope of the technical concept of this embodiment is not limited to this embodiment. The protection scope of this embodiment should be interpreted according to the following claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the claims of this embodiment.

Claims

1. A readout amplifier circuit for selecting and reading cells from a memory cell array, characterized in that, include: The current mirror circuit unit receives bias current from an external bias circuit and mirrors the bias current to multiple paths; A reference resistor unit includes a reference resistor and an N-type metal-oxide-semiconductor field-effect transistor that activates the reference resistor; A pre-charge circuit unit receives a pre-charge signal and pre-charges the reference bit line connected to the reference resistor based on the pre-charge signal. An amplifier circuit unit senses cell data corresponding to the selected fuse by utilizing the voltage difference between the resistance of the selected fuse and the reference resistor; and The buffer circuit unit outputs the sensed data. The amplifier circuit unit includes multiple P-type metal-oxide-semiconductor field-effect transistors. At least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors in the amplifier circuit unit is electrically connected to a connecting resistor.

2. The readout amplifier circuit according to claim 1, characterized in that, The current mirror circuit unit includes: A first current mirror reflects the bias current and provides it to the selected fuse; The second current mirror mirrors the bias current and provides it to the reference resistor unit; The third current mirror mirrors the bias current and provides it to the first amplifier circuit of the amplifier circuit unit; and The fourth current mirror mirrors the bias current and provides it to the second amplifier circuit of the amplifier circuit unit.

3. The readout amplifier circuit according to claim 1, characterized in that, The amplifier circuit unit includes: A first amplifier circuit generates a first amplifier signal by comparing the voltage of an internal bit line electrically connected to the connection resistor and the select fuse, and the voltage of a reference bit line electrically connected to the connection resistor and the reference resistor; and The second amplifier circuit generates a second amplifier signal by amplifying the first amplifier signal.

4. The readout amplifier circuit according to claim 3, characterized in that, The first amplifier circuit includes a first P-type metal-oxide-semiconductor field-effect transistor and a second P-type metal-oxide-semiconductor field-effect transistor. The gate terminals of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor are electrically connected to the first connection resistor and the second connection resistor, respectively.

5. The readout amplifier circuit according to claim 4, characterized in that, The first connection resistor and the second connection resistor adjust the gate input voltage of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor upwards.

6. The readout amplifier circuit according to claim 1, characterized in that, The reference resistor unit includes a first reference resistor and a second reference resistor, as well as a first N-type metal-oxide-semiconductor field-effect transistor and a second N-type metal-oxide-semiconductor field-effect transistor that selectively activate the first reference resistor and the second reference resistor, respectively.

7. The readout amplifier circuit according to claim 6, characterized in that, The first N-type metal-oxide-semiconductor field-effect transistor activates the first reference resistor in response to the first word line signal. The second N-type metal-oxide-semiconductor field-effect transistor activates the first reference resistor and the second reference resistor in response to the second word line signal.

8. The readout amplifier circuit according to claim 6, characterized in that, The first reference resistor and the second reference resistor have different resistance values.

9. The readout amplifier circuit according to claim 1, characterized in that, The precharge circuit unit includes at least one P-type metal-oxide-semiconductor field-effect transistor. When the precharge signal is activated, the P-type metal-oxide-semiconductor field-effect transistor is turned on, so that the reference bit line connected to the reference resistor is precharged to the power supply voltage.

10. A sense amplifier circuit for selecting and reading cells of a memory cell array, characterized in that, include: A reference resistor unit includes a reference resistor and an N-type metal-oxide-semiconductor field-effect transistor that activates the reference resistor; and An amplifier circuit unit senses cell data corresponding to the selected fuse by utilizing the voltage difference between the resistance of the selected fuse and the reference resistor. The amplifier circuit unit includes a two-stage operational amplifier circuit. The amplifier circuit unit includes multiple P-type metal-oxide-semiconductor field-effect transistors. At least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors in the amplifier circuit unit is electrically connected to a connecting resistor.

11. The readout amplifier circuit according to claim 10, characterized in that, It also includes a current mirror circuit unit that receives bias current from an external bias circuit and mirrors the bias current to multiple paths.

12. The readout amplifier circuit according to claim 11, characterized in that, The current mirror circuit unit includes: A first current mirror reflects the bias current and provides it to the selected fuse; The second current mirror mirrors the bias current and provides it to the reference resistor unit; The third current mirror mirrors the bias current and provides it to the first amplifier circuit of the amplifier circuit unit; and The fourth current mirror mirrors the bias current and provides it to the second amplifier circuit of the amplifier circuit unit.

13. The readout amplifier circuit according to claim 10, characterized in that, The amplifier circuit unit includes: A first amplifier circuit generates a first amplifier signal by comparing the voltage of an internal bit line electrically connected to the connection resistor and the select fuse, and a reference bit line electrically connected to the connection resistor and the reference resistor; and The second amplifier circuit generates a second amplifier signal by amplifying the first amplifier signal.

14. The readout amplifier circuit according to claim 13, characterized in that, The first amplifier circuit includes a first P-type metal-oxide-semiconductor field-effect transistor and a second P-type metal-oxide-semiconductor field-effect transistor. The gate terminals of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor are electrically connected to the first connection resistor and the second connection resistor, respectively. The internal bit line includes nodes that are electrically connected to the first connection resistor and the select fuse. The reference bit line includes a node electrically connected to the second connection resistor and the reference resistor.

15. The readout amplifier circuit according to claim 14, characterized in that, The first connection resistor and the second connection resistor adjust the gate input voltage of the first P-type metal-oxide-semiconductor field-effect transistor and the second P-type metal-oxide-semiconductor field-effect transistor upwards.

16. The readout amplifier circuit according to claim 10, characterized in that, The reference resistor unit includes a first reference resistor and a second reference resistor, as well as a first N-type metal-oxide-semiconductor field-effect transistor and a second N-type metal-oxide-semiconductor field-effect transistor that selectively activate the first reference resistor and the second reference resistor, respectively.

17. The readout amplifier circuit according to claim 16, characterized in that, The first N-type metal-oxide-semiconductor field-effect transistor activates the first reference resistor in response to the first word line signal. The second N-type metal-oxide-semiconductor field-effect transistor activates the first reference resistor and the second reference resistor in response to the second word line signal.

18. A method for reading out a memory cell, executed by a readout amplifier circuit, characterized in that, Includes the following steps: Select one cell included in the storage cell array; In response to a precharge signal, the reference bit line connected to the reference resistor included in the reference resistor cell is precharged; Receive bias current from an external bias circuit and mirror it to multiple paths; Select at least one of the first reference resistor and the second reference resistor included in the reference resistor unit, and connect the selected reference resistor to the reference bit line; as well as The cell data of the selected cell is sensed by means of an amplifier circuit unit using the voltage difference between the resistance of the selected fuse corresponding to the selected cell and the reference resistor. The amplifier circuit unit includes multiple P-type metal-oxide-semiconductor field-effect transistors. At least one input stage of the plurality of P-type metal-oxide-semiconductor field-effect transistors in the amplifier circuit unit is electrically connected to a connecting resistor. The steps for sensing unit data include the following steps: A first amplifier signal is generated by first amplifying the voltage difference between the internal bit line electrically connected to the connecting resistor and the select fuse and the reference bit line electrically connected to the connecting resistor and the reference resistor; as well as The second amplifier signal is generated by amplifying the first amplifier signal a second time.

19. The method for reading a storage cell according to claim 18, characterized in that, The step of connecting the selected reference resistor to the reference bit line includes the following steps: When the first reference resistor is selected, the first N-type metal-oxide-semiconductor field-effect transistor included in the reference resistor unit activates the first reference resistor in response to the first word line signal. When the first reference resistor and the second reference resistor are selected, the second N-type metal-oxide-semiconductor field-effect transistor included in the reference resistor unit activates the first reference resistor and the second reference resistor in response to the second word line signal.

20. The method for reading a storage cell according to claim 18, characterized in that, In the step of sensing unit data... A first logic value is generated when the voltage of the internal bit line is lower than the voltage of the reference bit line. A second logic value is generated when the voltage of the internal bit line is higher than the voltage of the reference bit line.

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