Multi-service optical terminal

Abstract

The application discloses a multi-service optical terminal, which comprises a cabinet, a front panel of the cabinet is provided with indicator lights, a rear panel of the cabinet is provided with optical interfaces, two-way Ethernet interfaces, two-way USB interfaces, two-way DVI video interfaces, 16-way switching value input interfaces, 16-way switching value output interfaces and a RS422 interface; a service board is arranged in the cabinet, the service board is provided with an FPGA chip and optical interface units, Ethernet units, USB units, DVI video units, switching value input units, switching value output units and RS422 units which are electrically connected with the FPGA chip, and is used for realizing bidirectional transmission of Ethernet services, switching value services and RS422 services in cooperation with the Ethernet interfaces, the switching value interfaces and the RS422 interface, and realizing unidirectional transmission of USB services and DVI video services in cooperation with the USB interfaces and the DVI video interfaces. The multi-service optical terminal can simultaneously transmit Ethernet data, USB interface data, DVI video data, switching value data and RS422 data, and reduces the complexity and development cost of equipment development.

Description

Technical Field

[0001] This utility model relates to the field of optical transceiver technology, and in particular to multi-service optical transceivers. Background Technology

[0002] An optical transceiver is a terminal device for optical signal transmission. It is a fiber optic communication device that extends data transmission. It mainly uses optical transmission characteristics to achieve the purpose of long-distance transmission through technologies such as signal modulation and photoelectric conversion.

[0003] In the prior art, patent CN203457157U discloses a USB optical transceiver, which includes a transmitter and a receiver. The transmitter and receiver are connected via optical fiber. The transmitter includes multiple flexible slots, a rack, and a controller. The rack has a cavity, and the controller is placed inside the cavity. The flexible slots are set on the rack. The receiver has multiple USB interfaces. The multiple flexible slots are respectively provided with video interfaces, E1 interfaces, Ethernet interfaces, telephone interfaces, RS485 data interfaces, and switch interfaces. This breaks through the limitation that USB signals can only be transmitted with short-distance cables, allowing USB devices to be easily extended on optical fibers. This extends the application range and connection distance of various USB bus-based devices, making the connection, wide-area propagation, distribution, and sharing of USB devices possible.

[0004] It can be seen that it needs to encapsulate the business into USB interface type data before transmitting it through fiber optic cable, which will significantly increase the complexity and cost of device development. Utility Model Content

[0005] This application provides a multi-service optical transceiver that can simultaneously transmit Ethernet data, USB interface data, DVI video data, switch data, and RS422 data, reducing the complexity and cost of device development.

[0006] This application provides a multi-service optical transceiver, including a chassis. The chassis has a front panel and a rear panel facing each other. The front panel has an indicator light, and the rear panel has an optical interface, two Ethernet interfaces, two USB interfaces, two DVI video interfaces, 16 digital input interfaces, 16 digital output interfaces, and one RS422 interface. The chassis houses a service board, which includes an FPGA chip and optical interface units, Ethernet units, USB units, DVI video units, digital input units, digital output units, and RS422 units that are electrically connected to the FPGA chip. These units are used to enable bidirectional transmission of Ethernet, digital input, and RS422 services in conjunction with the Ethernet, digital input, and RS422 interfaces, respectively, and to enable unidirectional transmission of USB and DVI video services in conjunction with the USB and DVI video interfaces.

[0007] In one possible implementation, the optical interface has two channels. The optical interface unit includes a bidirectional analog switch chip and two optical modules. The bidirectional analog switch chip is electrically connected to the FPGA chip and is connected to the two optical modules respectively. The two optical modules are connected to the two optical interfaces respectively. The optical interfaces are used to connect optical fibers.

[0008] In one possible implementation, the bidirectional analog switch chip is the CH482X ultra-high-speed differential signal bidirectional analog switch chip.

[0009] In one possible implementation, the optical module has an optical port rate of 1.25 Gbit / s and an optical port code of NRZ.

[0010] In one possible implementation, the optical module is designated as DTABSP9-11LQJ1 or DTABSQ2-11LQJ1.

[0011] Beneficial effects: Compared with the prior art, the multi-service optical transceiver provided in this application integrates optical interface unit, Ethernet unit, USB unit, DVI video unit, switch input unit, switch output unit and RS422 unit on the service board, which can simultaneously realize Ethernet service, USB service, DVI video service, switch service and RS422 service. It has a higher degree of integration, is convenient for networking applications, and can meet the access needs of various complex scenarios. In addition, by using two optical interfaces in conjunction with a bidirectional analog switch chip and two optical modules, the two optical channels can be used as backups for each other. In the event of a failure in one channel, the system can automatically switch to the other channel for data transmission, thereby ensuring normal communication of business data and improving communication reliability.

[0012] These and other objects, features and advantages of this utility model will be fully realized through the following detailed description. Attached Figure Description

[0013] Figure 1 The diagram shows a front-view stereoscopic structure of the multi-service optical transceiver of this application.

[0014] Figure 2 A rear-view stereoscopic structural diagram of the multi-service optical transceiver of this application is shown.

[0015] Figure 3 The diagram shows the structural connection relationship of the multi-service optical transceiver of this application. The term "near end" refers to the optical transceiver when it is used as a transmitter, and the term "far end" refers to the optical transceiver when it is used as a receiver or user.

[0016] Figure 4 A rear view structural schematic diagram of the multi-service optical transceiver of this application is shown; Detailed Implementation The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0017] Those skilled in the art should understand that, in the disclosure of this specification, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limitations on this utility model.

[0018] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0019] refer to Figures 1 to 4This application provides a multi-service optical transceiver, including a chassis 10. The chassis 10 has a front panel 11 and a rear panel 12 facing each other. The front panel 11 has indicator lights, and the rear panel 12 has an optical interface 21, two Ethernet interfaces 22, two USB interfaces 23, two DVI video interfaces 24, 16 digital input interfaces 25, 16 digital output interfaces 26, and one RS422 interface 27. The chassis 10 also houses a service board, which includes an FPGA chip and optical interface units, Ethernet units, USB units, DVI video units, digital input units, and digital output units electrically connected to the FPGA chip. The RS422 unit is used to cooperate with the Ethernet interface 22, the digital input interface (including 16 digital input interfaces 25 and 16 digital output interfaces 26), and the RS422 interface 27 to realize bidirectional transmission of Ethernet services, digital input services, and RS422 services, and to cooperate with the USB interface 23 and the DVI video interface 24 to realize unidirectional transmission of USB services and DVI video services. In this way, multiple interface types can be integrated at the same time, which is convenient for networking applications and can meet the access requirements of various complex scenarios. At the same time, compared with the existing technology, it can also reduce the complexity of device development and reduce development costs.

[0020] In one embodiment, the optical interface 21 has two channels, and the optical interface unit includes a bidirectional analog switch chip and two optical modules. The bidirectional analog switch chip is electrically connected to the FPGA chip and is connected to the two optical modules respectively. The two optical modules are connected to the two optical interfaces 21 respectively. The optical interfaces 21 are used to connect optical fibers. In this way, the two optical interfaces 21 and the two optical modules can make the two optical channels backup each other. Even if one channel fails, it can automatically switch to the other channel for data transmission, thereby ensuring normal communication of business data and improving communication reliability. Specifically, when the FPGA chip detects a line abnormality, it adjusts the on / off direction of the bidirectional analog switch chip through IO signals and automatically switches to the other channel for data transmission.

[0021] In one embodiment, the bidirectional analog switch chip is an ultra-high-speed differential signal bidirectional analog switch chip CH482X, used for optical channel switching.

[0022] In one embodiment, the optical module uses wavelength division multiplexing (WDM) technology to achieve bidirectional transmission on a single fiber (or single optical fiber), wherein the optical port rate of the optical module is 1.25 Gbit / s and the optical port code is NRZ.

[0023] In one embodiment, the optical module is model DTABSP9-11LQJ1 or DTABSQ2-11LQJ1. One end of the multi-service optical transceiver uses a 1310nm wavelength optical signal for transmitting and a 1550nm wavelength optical signal for receiving; alternatively, one end uses a 1550nm wavelength optical signal for transmitting and a 1310nm wavelength optical signal for receiving.

[0024] The working principle of the sending end is as follows: Ethernet Unit: Receives Ethernet data from the Ethernet interface on the rear panel of the chassis. After passing through the Ethernet PHY chip YT8522, it is converted into RMII interface signals (including clock, data, and control signals. The clock direction of this chip is provided to the PHY by the FPGA chip). The data is then connected to the FPGA chip through the RMII interface. The FPGA chip performs data frame reception, frame conversion, and FIFO buffering operations on the data.

[0025] USB Unit: USB data is received from USB interface 23 on the rear panel 12 of chassis 10. The USB protocol data is converted into UART serial communication protocol signal by the USB to serial port chip CH9350 and enters the FPGA chip through the UART interface of the FPGA. The FPGA performs protocol parsing and data buffering processing on the UART data.

[0026] DVI Video Unit: The DVI serial video signal is received from the DVI video interface 24 on the rear panel 12 of the chassis 10. The ADV7611 decoding chip of the DVI video interface 24 converts the serial TMDS video signal into 24-bit parallel RGB data, which is then sent to the FPGA chip through the parallel bus. The FPGA chip performs timing control, FIFO buffering and other processing on the data.

[0027] Digital input unit: Connected to digital input interface 12 on the rear panel of chassis 10. The digital signal is optically isolated by PC817 and then connected to the FPGA chip through the GPIO port. The FPGA chip performs data filtering, debouncing, status acquisition and judgment processing.

[0028] RS422 Unit: RS422 data is received from RS422 interface 27 on the rear panel 12 of chassis 10. The RS422 differential signal is converted into a single-ended serial signal by the RS422 transceiver chip MAX3077 and then connected through the UART communication module of the FPGA. The FPGA chip performs timing configuration, sampling, and serial-to-parallel conversion processing on the RS422 signal.

[0029] FPGA chip: The FPGA chip summarizes the above-mentioned switch data, RS422 data, Ethernet data, USB converted data, and DVI data, and completes the framing according to the custom frame format (including frame header, data type identifier, valid data, and check bit). The framed data is processed by 8B10B encoding, and the encoded parallel data is converted into high-speed serial electrical signals by the FPGA high-speed transceiver.

[0030] Optical Interface Unit: The FPGA chip connects to the CH482X via the SERDES interface and I / O ports. The CH482X connects to two optical modules. By default, the connection with optical module 1 is active. When the FPGA chip detects an optical channel fault, it modifies the I / O signal (high-low level conversion) and sends it to the analog switch chip CH482X. The analog switch chip then switches the channel to another path to ensure normal communication. The optical modules convert electrical signals into optical signals and transmit the data through the fiber optic interface. Its receiving end working principle: Optical Interface Unit: The optical module receives optical signals through optical interface 21, completes the conversion of optical signals to electrical signals, restores the optical signals to high-speed serial electrical signals, and then connects to the high-speed transceiver of the FPGA chip through the SEDES interface via an ultra-high-speed differential signal bidirectional analog switch.

[0031] FPGA chip: The high-speed transceiver converts high-speed serial electrical signals into parallel data and performs 8B10B decoding to restore the original framed data. The FPGA chip performs deframe processing on the data and recovers Ethernet data, USB data, DVI data, switch data, and RS422 data according to the data type code.

[0032] Ethernet Unit: The deframed Ethernet data is re-encapsulated into Ethernet frames and output to the Ethernet PHY chip YT8522 through the RMII interface, and output through Ethernet interface 22 on the rear panel of chassis 10.

[0033] USB Unit: The deframed USB data is converted into a UART serial signal and output to the USB to serial port chip CH9350 through the FPGA's UART module. After being converted into USB protocol data by CH9350, it is output through the USB interface 23 on the rear panel 12 of the chassis 10.

[0034] DVI Video Unit: After frame decoding, the DVI video data is processed by FPGA through TDMS encoding, serial and differential conversion, etc., and output as TDMS differential signal, which is directly output to the rear panel 12 DVI video interface 24 of the chassis 10.

[0035] Digital output unit: The digital data after frame de-framing is converted into a 3.3V level signal, which is output through the GPIO port of the FPGA. After weak current isolation and signal driving by the optical MOS relay LT239, it is connected to the high-power relay HF-3FF and output to the outside through the digital output interface 12 on the rear panel of chassis 10.

[0036] RS422 Unit: The deframed RS422 data is converted into a serial signal and output to the RS422 transceiver (MAX3077) through the UART module of the FPGA. After being converted into an RS422 differential signal by the MAX3077, it is output to the outside through the RS422 interface 27 on the rear panel 12 of the chassis 10.

[0037] It should be noted that the terms "first" and "second" used in this application are for descriptive purposes only and do not indicate any order. They should not be construed as indicating or implying relative importance, and can be interpreted as names.

[0038] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are merely examples and do not limit the present invention. The advantages of the present invention have been fully and effectively realized. The functions and structural principles of the present invention have been shown and explained in the embodiments, and any modifications or variations may be made to the implementation of the present invention without departing from the stated principles.

Claims

1. A multi-service optical transceiver, characterized in that, Includes a chassis, which has a front panel and a rear panel. The front panel has indicator lights, and the rear panel has an optical interface, two Ethernet interfaces, two USB interfaces, two DVI video interfaces, 16 digital input interfaces, 16 digital output interfaces, and one RS422 interface. The chassis houses a service board, which includes an FPGA chip and optical interface units, Ethernet units, USB units, DVI video units, digital input units, digital output units, and RS422 units that are electrically connected to the FPGA chip. These units are used to enable bidirectional transmission of Ethernet, digital input, and RS422 services in conjunction with the Ethernet, digital input, and RS422 interfaces, respectively, and to enable unidirectional transmission of USB and DVI video services in conjunction with the USB and DVI video interfaces.

2. The multi-service optical transceiver as described in claim 1, characterized in that, The optical interface has two channels. The optical interface unit includes a bidirectional analog switch chip and two optical modules. The bidirectional analog switch chip is electrically connected to the FPGA chip and is connected to the two optical modules respectively. The two optical modules are connected to the two optical interfaces respectively. The optical interfaces are used to connect optical fibers.

3. The multi-service optical transceiver as described in claim 2, characterized in that, The bidirectional analog switch chip is the CH482X ultra-high-speed differential signal bidirectional analog switch chip.

4. The multi-service optical transceiver as described in claim 2, characterized in that, The optical module has an optical port rate of 1.25 Gbit / s and an optical port code of NRZ.

5. The multi-service optical transceiver as described in claim 2, characterized in that, The optical module is model DTABSP9-11LQJ1 or DTABSQ2-11LQJ1.

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