Transistor and electronic device
By designing a structure with increasing barrier layer thickness in the transistor, the problem of low withstand voltage caused by uneven electric field distribution in the channel layer is solved, achieving high voltage adaptability and reduced on-resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GREE ELECTRIC APPLIANCE INC OF ZHUHAI
- Filing Date
- 2025-08-26
- Publication Date
- 2026-07-24
AI Technical Summary
The uneven electric field distribution in the channel layer of high electron mobility transistors leads to low withstand voltage, making them unsuitable for high-voltage applications.
Design a transistor structure in which the thickness of the barrier layer increases from the internal region toward a first direction and a second direction respectively, with the first direction being opposite to the second direction. A drain is disposed adjacent to the first boundary of the barrier layer, and a source is disposed adjacent to the second boundary. A gate is disposed above the internal region. The two-dimensional electron gas concentration of the channel layer is positively correlated with the thickness of the barrier layer, forming a smooth electric field distribution.
The transistor's voltage withstand capability has been improved, making it suitable for high-voltage scenarios, and its on-resistance has been reduced.
Smart Images
Figure CN224556136U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, specifically relating to a transistor and an electronic device. Background Technology
[0002] In related technologies, the electric field distribution in the channel layer of high electron mobility transistors (HEMTs) is not smooth, resulting in low breakdown voltage and making them unsuitable for high-voltage applications. Utility Model Content
[0003] This application aims to provide a transistor and an electronic device that at least solves the problem in the related art that the uneven electric field distribution of the channel layer of a high electron mobility transistor leads to low voltage withstand capability and makes it unsuitable for high voltage scenarios.
[0004] To solve the above-mentioned technical problems, this application is implemented as follows:
[0005] In a first aspect, embodiments of this application provide a transistor, including: a barrier layer, an isolation layer, a channel layer, a drain, a source, and a gate;
[0006] The isolation layer is disposed on top of the channel layer;
[0007] The barrier layer is disposed on the isolation layer. The thickness of the barrier layer increases from the inner region of the barrier layer towards the first direction and the second direction respectively. The drain is disposed adjacent to the first boundary of the barrier layer, the source is disposed adjacent to the second boundary of the barrier layer, and the gate is disposed above the inner region of the barrier layer.
[0008] Wherein, the first direction is opposite to the second direction; the second boundary of the barrier layer is disposed in the first direction of the first boundary of the barrier layer; the two-dimensional electron gas concentration of the channel layer is positively correlated with the thickness of the corresponding region of the barrier layer.
[0009] Secondly, embodiments of this application also provide an electronic device, including the transistors described in the first aspect.
[0010] In this embodiment, an isolation layer is disposed above the channel layer, and a barrier layer is disposed above the isolation layer. Since the thickness of the barrier layer increases from the internal region of the barrier layer towards the first direction and the second direction respectively, with the first direction being opposite to the second direction, and a drain is disposed adjacent to the first boundary of the barrier layer, and a source is disposed adjacent to the second boundary of the barrier layer, with the second boundary of the barrier layer being disposed in the first direction of the first boundary of the barrier layer, and a gate is disposed above the internal region of the barrier layer, the thickness of the barrier layer increases from the region below the gate towards the region below the drain and the region below the source respectively. Since the two-dimensional electron gas concentration of the channel layer is positively correlated with the thickness of the corresponding barrier layer region, the two-dimensional electron gas concentration of the channel layer increases from the region below the gate towards the region below the drain and the region below the source respectively. This results in a smooth electric field distribution between the region of the channel layer below the gate and the region of the channel layer below the drain, and between the region of the channel layer below the gate and the region of the channel layer below the source. Compared with the non-smooth electric field distribution of the channel layer in related technologies, this improves the voltage withstand capability of the transistor, thereby adapting to high-voltage scenarios. Attached Figure Description
[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a schematic diagram of a transistor provided in an embodiment of this application;
[0013] Figure 2 This is a schematic diagram of a gate provided in an embodiment of this application;
[0014] Figure 3 This is a schematic diagram of an epitaxial layer on a substrate provided in an embodiment of this application;
[0015] Figure 4 This is a schematic diagram of the etching of an initial barrier layer provided in an embodiment of this application;
[0016] Figure 5 This is a schematic diagram of the etching of a first area to be etched, provided in an embodiment of this application;
[0017] Figure 6 This is a schematic diagram of the etching of a second area to be etched, provided in an embodiment of this application.
[0018] Figure 7 This is a schematic diagram of the etching of a third area to be etched, provided in an embodiment of this application;
[0019] Figure 8 This is a schematic diagram of the etching of a fourth area to be etched, provided in an embodiment of this application;
[0020] Figure 9 This is a schematic diagram of an initial passivation layer provided in an embodiment of this application;
[0021] Figure 10 This is a schematic diagram of the etching of an initial passivation layer provided in an embodiment of this application;
[0022] Figure 11 This is a schematic diagram of the energy band of a HEMT device provided in an embodiment of this application;
[0023] Figure 12 This is a flowchart of a transistor manufacturing method provided in an embodiment of this application.
[0024] Figure label:
[0025] 10-Barrier layer; 10a-Initial barrier layer; 10b-Third opening; 11-First region; 12-Second region; 13-First region to be etched; 14-Second region to be etched; 15-Third region to be etched; 16-Fourth region to be etched; 31-Drain; 32-Source; 33-Gate; 33a-First section; 33b-Second section; 21-Isolation layer; 22-Channel layer; 23-Passivation layer; 23a-Initial passivation layer; 23b-Groove; 23c-First opening; 23d-Second opening; 24-Insertion layer; 25-Substrate layer; 26-Nucleation layer; 27-Buffer layer. Detailed Implementation
[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0027] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0028] Reference Figure 1 This application provides a transistor comprising: a barrier layer 10, an isolation layer 21, a channel layer 22, a drain 31, a source 32, and a gate 33; the isolation layer 21 is disposed on the channel layer 22; the barrier layer 10 is disposed on the isolation layer 21, and the thickness of the barrier layer 10 increases from the internal region of the barrier layer 10 towards a first direction and a second direction respectively; the drain 31 is disposed adjacent to the first boundary of the barrier layer 10, the source 32 is disposed adjacent to the second boundary of the barrier layer 10, and the gate 33 is disposed above the internal region of the barrier layer 10; wherein, the first direction is opposite to the second direction; the second boundary of the barrier layer 10 is disposed in the first direction of the first boundary of the barrier layer 10; the two-dimensional electron gas concentration of the channel layer 22 is positively correlated with the thickness of the corresponding region of the barrier layer 10.
[0029] In some embodiments, the thickness of the barrier layer 10 increases in steps from the internal region of the barrier layer 10 toward the first direction and the second direction, respectively.
[0030] In some embodiments, the second boundary of the barrier layer 10 is disposed opposite to the first boundary of the barrier layer 10.
[0031] In some embodiments, the barrier layer 10 includes multiple regions, and the internal region of the barrier layer 10 is a region inside the barrier layer 10 that is far from the boundary of the barrier layer 10.
[0032] In some embodiments, the transistor can be a gallium nitride high electron mobility transistor (GaN HEMT). As one of the representatives of third-generation semiconductors, gallium nitride high electron mobility transistors have great potential in high voltage and high frequency applications due to their advantages such as high electron mobility, high critical breakdown electric field, and stable physicochemical properties.
[0033] In some embodiments, the material of the barrier layer 10 includes N-type doped Al. x Ga 1-x N, x ranges from 0.1 to 0.3.
[0034] In some embodiments, the band structure of the barrier layer 10 and the channel layer 22 form a heterojunction, forming a two-dimensional electron gas at the interface.
[0035] In some embodiments, the material of the isolation layer 21 includes undoped Al. x Ga 1-x N.
[0036] In some embodiments, the isolation layer 21 serves as an isolation layer, which can reduce the influence of doped atoms in the barrier layer 10 on the channel, and also helps to increase the concentration and mobility of the two-dimensional electron gas in the channel.
[0037] In some embodiments, the material of the channel layer 22 includes GaN.
[0038] In some embodiments, the channel layer 22 is used for electron transport, and the polarization between the channel layer 22 and the AlGaN barrier layer 10 induces a two-dimensional electron gas.
[0039] In some embodiments, the material of the drain electrode 31 includes metal.
[0040] In some embodiments, the source electrode 32 is made of metal.
[0041] In some embodiments, the transistors provided in this application can be used to fabricate ultraviolet photodetectors.
[0042] Reference Figure 12 In some embodiments, E C For the rewind level, E F For the Fermi level, E V The valence band energy level is A1, which is the interface between AlGaN and GaN. For a depletion-mode GaN device, let the thickness of the AlGaN / GaN barrier layer 10 be d, and let the doped layer (with a doping concentration of N) be the boundary layer. D ) and thickness d i The undoped isolation layer 21 is composed of Al with a relative permittivity of ε(x). x GaN 1-x Surface potential of N Schottky barrier height formed by Ni metal on AlGaN surface To approximate this, the expression for the change of the potential barrier with respect to the Al composition is as follows:
[0043]
[0044] Surface density of two-dimensional electron gas (n s2D The expression for ) is as follows:
[0045]
[0046] In the formula σ pol (x) represents the polarization charge at the AlGaN / GaN interface, e is the fundamental charge, ε0 is the dielectric constant of vacuum, and ΔE F It represents the distance from the bottom conduction band energy of the GaN-side quantum well to the Fermi level. The conduction band order ΔE at the AlGaN / GaN interface. C (x)=0.7ΔE g ΔE gThis refers to the bandgap difference between AlGaN and GaN. Practical AlGaN / GaN HEMT devices typically insert AlN at the heterojunction to form an AlGaN / AlN / GaN heterojunction, improving transistor performance. Considering the effective bandgap ΔE of the AlN insertion layer 24 relative to the barrier layer 10... C,eff With the effect of increasing dielectric constant, neglecting the difference in dielectric constant between AlGaN and AlN, the corrected expression for the surface density of the two-dimensional electron gas is:
[0047]
[0048] in:
[0049]
[0050] σ AlGAN σ is the interfacial polarization charge density of AlGaN / GaN. AlN Let ΔE be the interfacial polarization charge density of AlN / GaN. C,AlN / GaN For the conduction band order of the AlN / GaN interface (taking positive values), ΔE c,AlGaN / AlN (x) represents the conduction band order of the AlGaN / AlN interface (taking positive values), d AlN The thickness of the AlN insertion layer 24 is given. When the applied gate voltage is lower than the threshold voltage, the barrier layer 10 below the gate 33 is thinner and has a weaker polarization effect, which cannot induce enough two-dimensional electron gas in the channel to keep the transistor in the normally off state.
[0051] Due to N D (dd i ) 2 Since d is a quadratic term, and d in the denominator of the corrected expression for the surface density of a two-dimensional electron gas is a linear term, the larger d is, the more linear n becomes. s2D The larger the thickness, the more the horizontal barrier layer 10 thickness is gradually varied, which can increase the concentration of two-dimensional electron gas from the gate 33 to both sides of the source 32 and drain 31. That is, the concentration of two-dimensional electron gas in the channel layer 22 increases stepwise from the region below the gate 33 to the region below the drain 31 and the region below the source 32, respectively. The horizontal electric field is smoothed, which improves the breakdown voltage of the transistor.
[0052] When the applied gate voltage is higher than the threshold voltage, electrons in GaN are replenished below the gate 33, the conductive channel is turned on, and the transistor is turned on. Since the barrier layer 10 near the source 32 and drain 31 is the thickest, the two-dimensional electron gas concentration near the source 32 and drain 31 is also high. Therefore, by adopting this structure, the on-resistance of the transistor can be reduced at the same time.
[0053] In this embodiment, the isolation layer 21 is disposed above the channel layer 22, and the barrier layer 10 is disposed above the isolation layer 21. Since the thickness of the barrier layer 10 increases in steps from its internal region towards a first direction and a second direction (the first direction being opposite to the second direction), and a drain 31 is disposed adjacent to the first boundary of the barrier layer 10, and a source 32 is disposed adjacent to the second boundary of the barrier layer 10 (the second boundary of the barrier layer 10 is located in a first direction from the first boundary of the barrier layer 10), and a gate 33 is disposed above the internal region of the barrier layer 10, the thickness of the barrier layer 10 increases from the region below the gate 33 towards the region below the drain 31 and... The region below the source 32 increases in a stepped manner. Since the concentration of two-dimensional electron gas in the channel layer 22 is positively correlated with the thickness of the corresponding barrier layer 10, the concentration of two-dimensional electron gas in the channel layer 22 increases in a stepped manner from the region below the gate 33 to the region below the drain 31 and the region below the source 32. This results in a smooth electric field distribution between the region of the channel layer 22 below the gate 33 and the region of the channel layer 22 below the drain 31, and between the region of the channel layer 22 below the gate 33 and the region of the channel layer 22 below the source 32. Compared with the non-smooth electric field distribution of the channel layer in related technologies, this improves the voltage withstand capability of the transistor, thereby adapting to high-voltage scenarios.
[0054] Optionally, in some embodiments, the barrier layer 10 includes n first regions 11 and m second regions 12, where n and m are both positive integers; the first first region 11 is disposed on the first boundary of the barrier layer 10, the drain 31 is disposed adjacent to the first first region 11, the (i+1)th first region 11 is disposed adjacent to the ith first region 11 in the first direction, and the thickness of the (i+1)th first region 11 is less than the thickness of the ith first region 11; the first second region 12 is disposed on the barrier layer 10. The second boundary is defined by the source electrode 32 being disposed adjacent to the first second region 12, the (j+1)th second region 12 being disposed adjacent to the second direction of the jth second region 12, the thickness of the (j+1)th second region 12 being less than the thickness of the jth second region 12, the mth second region 12 being disposed in the first direction of the nth first region 11, and the gate electrode 33 being disposed between the (m-1)th second region 12 and the (n-1)th first region 11; where i is a positive integer less than n and j is a positive integer less than m.
[0055] For example, the barrier layer 10 includes five first regions 11 and three second regions 12. The second first region 11 is adjacent to the first first region 11 in a first direction, and the thickness of the second first region 11 is less than the thickness of the first first region 11. The third first region 11 is adjacent to the second first region 11 in a first direction, and the thickness of the third first region 11 is less than the thickness of the second first region 12. The fourth first region 11 is adjacent to the third first region 11 in a first direction, and the thickness of the fourth first region 11 is less than the thickness of the third first region 12. The fifth first region 12 is adjacent to the first first region 11 in a first direction. The fourth first region 11 is located in the first direction, and the thickness of the fifth first region 11 is less than the thickness of the fourth first region 11; the second second region 12 is adjacent to the first second region 12 in the second direction, and the thickness of the second second region 12 is less than the thickness of the first second region 12; the third second region 12 is adjacent to the second second region 12 in the second direction, and the thickness of the third second region 12 is less than the thickness of the second second region 12; the third second region 12 is located in the first direction of the fifth first region 11; and a gate 33 is disposed between the fourth second region 12 and the second first region 11.
[0056] In some embodiments, the total width of the n first regions 11 is greater than the total width of the m second regions 12.
[0057] In this embodiment, since the total width of the n first regions 11 is greater than the total width of the m second regions 12, the distance between the source and the gate is less than the distance between the drain and the gate. The gate is closer to the source, which allows the current to be guided to the source faster, thereby accelerating the conduction of the transistor and improving the sensitivity of the transistor conduction.
[0058] In some embodiments, at least some of the widths of all first regions 11 and all second regions 12 are the same; in other embodiments, the width of each first region 11 and the width of each second region 12 are different.
[0059] For example, the barrier layer 10 includes five first regions 11 and three second regions 12. The width of each first region 11 is different. The width of the first first region 11 is different from the width of the first second region 12. The width of the second first region 11 is different from the width of the second second region 12. The width of the third first region 11 is different from the width of the third second region 12. The width of the fourth first region 11 is different from the width of each second region 12. The width of the fifth first region 11 is different from the width of each second region 12.
[0060] For example, the barrier layer 10 includes six first regions 11 and four second regions 12. The width of the first first region 11 is different from the width of the first second region 12. The width of the second first region 11 is the same as the width of the second second region 12. The width of the third first region 11 is different from the width of the third second region 12. The width of the fourth first region 11 is the same as the width of the fourth second region 12. The width of the fifth first region 11 is different from the width of each second region 12. The width of the sixth first region 11 is different from the width of each second region 12.
[0061] In this embodiment, since the first first region 11 is disposed on the first boundary of the barrier layer 10, a drain 31 is disposed adjacent to the first first region 11, and the (i+1)th first region 11 is disposed adjacent to the first direction of the ith first region 11, the thickness of the (i+1)th first region 11 is less than the thickness of the ith first region 11, and the mth second region 12 is disposed in the first direction of the nth first region 11, a gate 33 is disposed between the (m-1)th second region 12 and the (n-1)th first region 11. The thickness of the barrier layer 10 increases in steps from the region below the gate 33 to the region below the drain 31. Since the first second region 12 is disposed on the second boundary of the barrier layer 10, the source 32 is disposed adjacent to the first second region 12, and the (j+1)th second region 12 is disposed adjacent to the second direction of the jth second region 12, and the thickness of the (j+1)th second region 12 is less than the thickness of the jth second region 12, the thickness of the barrier layer 10 increases in steps from the region below the gate 33 to the region below the source 32.
[0062] Optionally, in some embodiments, the nth first region 11 and the mth second region 12 are spaced apart by a preset distance; the gate 33 is disposed between the nth first region 11 and the mth second region 12.
[0063] In some embodiments, the material of the gate 33 includes metal.
[0064] For example, the barrier layer 10 includes five first regions 11 and three second regions 12. The second first region 11 is adjacent to the first first region 11 in a first direction, and the thickness of the second first region 11 is less than the thickness of the first first region 11. The third first region 11 is adjacent to the second first region 11 in a first direction, and the thickness of the third first region 11 is less than the thickness of the second first region 12. The fourth first region 11 is adjacent to the third first region 11 in a first direction, and the thickness of the fourth first region 11 is less than the thickness of the third first region 11. The fifth first region 11 is adjacent to the fourth first region 11 in a first direction. In the direction of the fifth first region 11, the thickness of the fifth first region 11 is less than the thickness of the fourth first region 11; the second second region 12 is adjacent to the first second region 12 in the second direction, and the thickness of the second second region 12 is less than the thickness of the first second region 12; the third second region 12 is adjacent to the second second region 12 in the second direction, and the thickness of the third second region 12 is less than the thickness of the second second region 12; the third second region 12 is located in the first direction of the fifth first region 11; the fifth first region 11 and the third second region 12 are spaced apart by a preset distance; and a gate 33 is provided between the fifth first region 11 and the third second region 12.
[0065] In this embodiment, since the nth first region 11 and the mth second region 12 are spaced apart by a preset distance, and a gate 33 is provided between the nth first region 11 and the mth second region 12, the two-dimensional electron gas concentration at the interface between the region of the isolation layer 21 below the gate 33 and the region of the channel layer 22 below the gate 33 is the lowest.
[0066] Optionally, in some embodiments, the nth first region 11 is adjacent to the mth second region 12; the thickness of the nth first region 11 is less than the thickness of the mth second region 12; and the gate 33 is disposed adjacent to the nth first region 11.
[0067] In some embodiments, the gate 33 is a P-GaN gate, and the material of the P-GaN gate includes p-type doped GaN material.
[0068] For example, the barrier layer 10 includes five first regions 11 and three second regions 12. The second first region 11 is adjacent to the first first region 11 in a first direction, and the thickness of the second first region 11 is less than the thickness of the first first region 11. The third first region 11 is adjacent to the second first region 11 in a first direction, and the thickness of the third first region 12 is less than the thickness of the second first region 12. The fourth first region 11 is adjacent to the third first region 11 in a first direction, and the thickness of the fourth first region 12 is less than the thickness of the third first region 12. The fifth first region 12 is adjacent to the fourth first region 11 in a first direction. The thickness of region 11 is less than the thickness of the fourth first region 11; the second second region 12 is disposed adjacent to the first second region 12 in the second direction, and the thickness of the second second region 12 is less than the thickness of the first second region 12; the third second region 12 is disposed adjacent to the second second region 12 in the second direction, and the thickness of the third second region 12 is less than the thickness of the second second region 12; the third second region 12 is disposed in the first direction of the fifth first region 11; the fifth first region 11 is adjacent to the third second region 12, and a gate 33 is disposed adjacent to the fifth first region 11, and the thickness of the fifth first region 11 is less than the thickness of the third second region 12.
[0069] In this embodiment, since the nth first region 11 is adjacent to the mth second region 12, and a gate 33 is disposed adjacently above the nth first region 11, and the thickness of the nth first region 11 is less than the thickness of the mth second region 12, the two-dimensional electron gas concentration at the interface between the region of the isolation layer 21 below the gate 33 and the region of the channel layer 22 below the gate 33 is the lowest.
[0070] Optionally, in some embodiments, the thickness of the kth second region 12 is equal to the thickness of the kth first region 11, where k is a positive integer less than or equal to m.
[0071] For example, the barrier layer 10 includes six first regions 11 and four second regions 12. The width of the first first region 11 is the same as the width of the first second region 12. The width of the second first region 11 is the same as the width of the second second region 12. The width of the third first region 11 is the same as the width of the third second region 12. The width of the fourth first region 11 is the same as the width of the fourth second region 12. The width of the fifth first region 11 is different from the width of each second region 12. The width of the sixth first region 11 is different from the width of each second region 12.
[0072] In this embodiment, since the thickness of the kth second region 12 is equal to the thickness of the kth first region 11, and k is a positive integer less than or equal to m, k second regions 12 and kth first regions 11 can be processed simultaneously. This is beneficial to reduce the processing steps of the structure in which the thickness of the barrier layer 10 increases stepwise from the internal region of the barrier layer 10 to the first direction and the second direction respectively.
[0073] Optionally, in some embodiments, the transistor further includes a passivation layer 23; the passivation layer 23 is disposed adjacent to the barrier layer 10, and the passivation layer 23 is provided with a groove 23b, a first opening 23c, and a second opening 23d. The groove 23b is disposed above the inner region of the barrier layer 10, the first opening 23c is disposed adjacent to the first boundary of the barrier layer 10, and the second opening 23d is disposed adjacent to the second boundary of the barrier layer 10; the gate 33 is disposed in the groove 23b; the drain 31 is disposed in the first opening 23c and adjacent to the barrier layer 10; the source 32 is disposed in the second opening 23d and adjacent to the barrier layer 10.
[0074] In some embodiments, the material of the passivation layer 23 includes SiN.
[0075] In some embodiments, the passivation layer 23 serves to protect the transistor surface, reduce surface states, lower leakage current, enhance the source-drain 31-ohm contact and breakdown voltage, etc.
[0076] Reference Figure 2 In some embodiments, the gate 33 includes a first portion 33a and a second portion 33b. The first portion 33a is disposed on the passivation layer 23 outside the groove 23b. One end of the second portion 33b is connected to the lower surface of the first portion 33a. The second portion 33b is disposed in the groove 23b. The second portion 33b is separated from the isolation layer 21 by the passivation layer 23.
[0077] In this embodiment, since the gate 33 is disposed in the recess 23b, and the recess 23b is disposed above the internal region of the barrier layer 10, the two-dimensional electron gas concentration at the interface between the region of the isolation layer 21 below the gate 33 and the region of the channel layer 22 below the gate 33 is the lowest. Since the drain 31 is disposed in the first aperture 23c, and the drain 31 is disposed adjacent to the barrier layer 10, and the first aperture 23c is disposed adjacent to the first boundary of the barrier layer 10, the two-dimensional electron gas concentration at the interface between the region of the isolation layer 21 below the drain 31 and the region of the channel layer 22 below the drain 31 is the highest in the first direction of the gate 33. Since the source 32 is disposed in the second aperture 23d, and the source 32 is disposed adjacent to the barrier layer 10, and the second aperture 23d is disposed adjacent to the second boundary of the barrier layer 10, the two-dimensional electron gas concentration at the interface between the region of the isolation layer 21 below the source 32 and the region of the channel layer 22 below the source 32 is the highest in the second direction of the gate 33.
[0078] Optionally, in some embodiments, the transistor further includes an insertion layer 24 disposed between the channel layer 22 and the isolation layer 21.
[0079] In some embodiments, the material of the insert layer 24 includes AlN.
[0080] In this embodiment, the insertion layer 24 can deepen the quantum well between the isolation layer 21 and the channel layer 22, increase the two-dimensional electron gas density, further reduce the scattering effect of the barrier layer 10 on the two-dimensional electron gas in the channel, thereby improving the carrier mobility.
[0081] Optionally, in some embodiments, the transistor further includes a substrate layer 25 disposed beneath the channel layer 22.
[0082] In some embodiments, the material of the substrate layer 25 includes, but is not limited to, Si, SiC, sapphire, GaN, etc.
[0083] In this embodiment, the substrate layer 25 is the basic support structure of the entire transistor, and the substrate layer 25 is used for the epitaxial growth of the epitaxial layer (e.g., the nucleation layer 26).
[0084] Optionally, in some embodiments, the transistor further includes a nucleation layer 26 disposed between the channel layer 22 and the substrate layer 25.
[0085] In some embodiments, the material of the nucleation layer 26 includes AlN, AlGaN, etc.
[0086] In this embodiment, the nucleation layer 26 is used to reduce the lattice mismatch between the substrate layer 25 and the buffer layer 27, thereby reducing the interface defect density and improving the crystal quality of the epitaxial layer.
[0087] Optionally, in some embodiments, the transistor further includes a buffer layer 27 disposed between the channel layer 22 and the nucleation layer 26.
[0088] In some embodiments, the material of the buffer layer 27 includes GaN.
[0089] In this embodiment, the buffer layer 27 is used to further reduce the impact of lattice mismatch and differences in thermal expansion coefficients, providing a higher quality growth interface, while also being able to withstand a certain voltage. By adjusting the growth temperature, V-III ratio, cavity pressure, etc. of the buffer layer 27, a buffer layer 27 with good crystal quality is grown, thereby reducing the longitudinal leakage current of the transistor. The V-III ratio refers to the flow ratio of group V elements (such as nitrogen, phosphorus, arsenic, etc.) to group III elements (such as gallium, aluminum, indium, etc.).
[0090] This application also provides an electronic device, including the transistors described above. The specific implementation of the transistors in the electronic device is similar to that described above, and will not be repeated here.
[0091] In summary, in this embodiment, the isolation layer 21 is disposed above the channel layer 22, and the barrier layer 10 is disposed above the isolation layer 21. Since the thickness of the barrier layer 10 increases in steps from its internal region towards the first and second directions (the first and second directions being opposite), and a drain 31 is disposed at the first boundary of the barrier layer 10, and a source 32 is disposed at the second boundary of the barrier layer 10 (the second boundary is located in the first direction of the first boundary), and a gate 33 is disposed above the internal region of the barrier layer 10, the thickness of the barrier layer 10 increases from the region below the gate 33 towards the region below the drain 31 and the region below the source 32. The area of the barrier layer 10 increases in a stepwise manner. Since the concentration of two-dimensional electron gas in the channel layer 22 below the barrier layer 10 is positively correlated with the thickness of the barrier layer 10, the concentration of two-dimensional electron gas in the channel layer 22 increases in a stepwise manner from the area below the gate 33 to the area below the drain 31 and the area below the source 32. This results in a smooth electric field distribution between the area of the channel layer 22 below the gate 33 and the area of the channel layer 22 below the drain 31, and between the area of the channel layer 22 below the gate 33 and the area of the channel layer 22 below the source 32. Compared with the non-smooth electric field distribution of the channel layer in related technologies, this improves the voltage withstand capability of the transistor, thus adapting to high-voltage scenarios.
[0092] Figure 12 This application provides a method for manufacturing a transistor, applicable to transistors as described above. Figure 12 As shown, the method may include:
[0093] Step 101: Form an initial barrier layer 10a, the isolation layer 21, and the channel layer 22; the initial barrier layer 10a is disposed on the isolation layer 21.
[0094] In this embodiment, a barrier layer 10 is formed by forming an initial barrier layer 10a, an isolation layer 21 and a channel layer 22, and then performing multiple etching operations on the initial barrier layer 10a to form a barrier layer 10. Then, a gate 33 is disposed above the inner region of the barrier layer 10, a drain 31 is disposed at the first boundary of the barrier layer 10, and a source 32 is disposed at the second boundary of the barrier layer 10 to form a transistor.
[0095] In some embodiments, step 101 includes the following sub-steps:
[0096] Sub-step 1011: Obtain substrate layer 25 and form nucleation layer 26 on substrate layer 25.
[0097] In some embodiments, an AlGaN / GaN epitaxial layer is grown on substrate 25 using metal-organic chemical vapor deposition (MOCVD). Trimethylgallium (TMGa), trimethylaluminum (TMAl), and high-purity ammonia (NH3) are used as Ga source, Al source, and N source, respectively, and high-purity H2 and N2 are used as carrier gases. After pretreatment of the substrate at a high temperature of 1070°C to 1100°C, the temperature is cooled to 500°C to 600°C, and then a nucleation layer 26 with a thickness of 20 nm to 200 nm is grown under a pressure of 400 to 500 torr.
[0098] In this embodiment of the application, a substrate layer 25 is obtained, and a nucleation layer 26 is formed on the substrate layer 25, and then a buffer layer 27 is formed on the nucleation layer 26.
[0099] Sub-step 1012: Form a buffer layer 27 on the nucleation layer 26.
[0100] In some embodiments, the pressure is reduced to 110 to 150 torr and the temperature is increased to 1050°C to 1150°C to grow a high-resistivity GaN epitaxial layer of approximately 3 μm to 8 μm thickness, namely buffer layer 27. Buffer layer 27 is N-type doped with a doping concentration of 1e14 cm⁻¹. -3 .
[0101] In this embodiment, a buffer layer 27 is formed on the nucleation layer 26, and then a channel layer 22 is formed on the buffer layer 27.
[0102] Sub-step 1013: Form a channel layer 22 on the buffer layer 27.
[0103] In some embodiments, the epitaxial temperature is adjusted to 1100°C to 1180°C, and triethylgallium (TEGa) is used as the Ga source to epitaxially grow a high-quality GaN channel layer 22. The thickness of the channel layer 22 is 100 nm to 200 nm, and the doping concentration is 1e15 cm⁻¹. -3 .
[0104] In this embodiment, a channel layer 22 is formed on the buffer layer 27, and then an insertion layer 24 is formed on the channel layer 22.
[0105] Sub-step 1014: Form an insertion layer 24 on the channel layer 22.
[0106] In some embodiments, the epitaxial temperature is reduced to 1000°C to 1100°C to epitaxially insert an AlN insertion layer 24, and the thickness of the insertion layer 24 is 1 nm to 2 nm.
[0107] In this embodiment, an insertion layer 24 is formed on the channel layer 22, and then an isolation layer 21 is formed on the insertion layer 24.
[0108] Sub-step 1015: Form an isolation layer 21 on the insertion layer 24.
[0109] In some embodiments, an AlxGa1-xN isolation layer 21 is epitaxially grown at a temperature of 1000°C to 1100°C. The thickness of the isolation layer 21 is 3 nm to 5 nm, and the doping concentration of the isolation layer 21 is 1e15 cm⁻¹. -3 .
[0110] In this embodiment of the application, an isolation layer 21 is formed on the insertion layer 24, and then an initial barrier layer 10a is formed on the isolation layer 21.
[0111] Sub-step 1016: Form an initial barrier layer 10a on the isolation layer 21.
[0112] In some embodiments, the barrier layer 10 is N-type doped Al. x Ga 1-x The Al composition of barrier layer 10 is consistent with that of undoped isolation layer 21. The thickness of barrier layer 10 is 20 nm to 30 nm, and the doping concentration of barrier layer 10 is 1e18 cm⁻¹. -3 up to 5e18cm -3 .
[0113] In this embodiment of the application, an initial barrier layer 10a is formed on the isolation layer 21, and then the initial barrier layer 10a is etched multiple times to form the barrier layer 10.
[0114] Reference Figure 3In some embodiments, a nucleation layer 26 is formed above the substrate layer 25, a buffer layer 27 is formed above the nucleation layer 26, a channel layer 22 is formed above the buffer layer 27, an insertion layer 24 is formed above the channel layer 22, an isolation layer 21 is formed above the insertion layer 24, and an initial barrier layer 10a is formed above the isolation layer 21.
[0115] Step 102: Perform multiple etching operations on the initial barrier layer 10a to form the barrier layer 10.
[0116] In some embodiments, an inductively coupled plasma etching machine is used to perform multiple etching operations on the initial barrier layer 10a to form the barrier layer 10.
[0117] In some embodiments, the barrier layer 10 includes five first regions 11 and three second regions 12; see reference Figure 4 The initial barrier layer 10a was etched for the first time using an inductively coupled plasma etcher (ICP) to obtain the first first region 11, the first second region 12, and the first region to be etched 13. The etching depth of the first etching was 4 nm to 8 nm. Figure 5 The first etchable region 13 is etched a second time using an inductively coupled plasma etching machine to obtain a second first region 11, a second second region 12, and a second etchable region 14. The etching depth of the second etching is 4 nm to 8 nm. (Refer to...) Figure 6 The second etchable region 14 is etched a third time using an inductively coupled plasma etching machine to obtain the third first region 11, the third second region 12, and the third etchable region 15. The etching depth of the third etching is 4 nm to 8 nm. Figure 7 The third etchable region 15 was etched a fourth time using an inductively coupled plasma etching machine to obtain the fourth first region 11 and the fourth etchable region 16. The etching depth of the fourth etching was 4 nm to 8 nm. Figure 8 The fourth etchable region 16 was etched for the fifth time using an inductively coupled plasma etching machine to obtain the fifth first region 11 and the third opening 10b. The etching depth of the fifth etching was 4nm to 8nm.
[0118] In this embodiment of the application, after forming the initial barrier layer 10a, the isolation layer 21 and the channel layer 22, the initial barrier layer 10a is etched multiple times to form the barrier layer 10. Then, the gate 33 is disposed above the inner region of the barrier layer 10, the drain 31 is disposed at the first boundary of the barrier layer 10, and the source 32 is disposed at the second boundary of the barrier layer 10 to form a transistor.
[0119] Step 103: The gate 33 is disposed above the inner region of the barrier layer 10, the drain 31 is disposed adjacent to the first boundary of the barrier layer 10, and the source 32 is disposed adjacent to the second boundary of the barrier layer 10 to form the transistor.
[0120] In this embodiment, a transistor is formed by disposing the gate 33 above the inner region of the barrier layer 10, disposing the drain 31 adjacently on the first boundary of the barrier layer 10, and disposing the source 32 adjacently on the second boundary of the barrier layer 10, thereby realizing the manufacture of the transistor.
[0121] Optionally, in some embodiments, before step 103, the method further includes:
[0122] Step 104: Form an initial passivation layer 23a on the barrier layer 10.
[0123] Reference Figure 9 In some embodiments, an initial passivation layer 23a of SiN is grown using low-pressure chemical vapor deposition (LPCVD), and the thickness of the initial passivation layer 23a is 50 nm to 200 nm.
[0124] In this embodiment of the application, an initial passivation layer 23a is formed on the barrier layer 10, and then the initial passivation layer 23a is etched with a groove 23b, a first opening 23c and a second opening 23d to form the passivation layer 23.
[0125] Step 105: Etch the initial passivation layer 23a with a groove 23b, a first opening 23c, and a second opening 23d to form the passivation layer 23; the groove 23b is disposed above the internal region of the barrier layer 10, the first opening 23c is disposed at the first boundary of the barrier layer 10, and the second opening 23d is disposed at the second boundary of the barrier layer 10.
[0126] Reference Figure 10 In some embodiments, an inductively coupled plasma etching (ICP-CPE) machine is used to etch the initial passivation layer 23a region above the third opening 10b of the barrier layer 10 to form a groove 23b of the passivation layer 23. The distance between the bottom of the groove 23b and the upper surface of the isolation layer 21 is 20 nm to 50 nm. An ICP-CPE machine is also used to etch the initial passivation layer 23a region above the first boundary of the barrier layer 10 to form a first opening 23c. An ICP-CPE machine is also used to etch the initial passivation layer 23a region above the second boundary of the barrier layer 10 to form a second opening 23d.
[0127] In this embodiment of the application, a passivation layer 23 is formed by etching the initial passivation layer 23a through a groove 23b, a first opening 23c, and a second opening 23d. Then, a gate 33 is disposed in the groove 23b, a drain 31 is disposed in the first opening 23c, and a source 32 is disposed in the second opening 23d to form a transistor.
[0128] Step 103 includes the following sub-steps:
[0129] Sub-step 1031: The gate 33 is disposed in the groove 23b, the drain 31 is disposed in the first opening 23c, and the source 32 is disposed in the second opening 23d to form the transistor.
[0130] In some embodiments, the drain 31 includes a first drain layer and a second drain layer, with the first drain layer disposed below the second drain layer.
[0131] In some embodiments, the material of the first drain layer includes Ti, and the material of the second drain layer includes Al.
[0132] In some embodiments, the source 32 includes a first source layer and a second source layer, wherein the first source layer is disposed below the second source layer.
[0133] In some embodiments, the material of the first source layer includes Ti, and the material of the second source layer includes Al.
[0134] In some embodiments, magnetron sputtering is used to deposit electrode metals, and rapid annealing is used to form an ohmic contact between the drain 31 and the upper surface of the first first region 11, the first drain layer is in contact with the upper surface of the first first region 11, the thickness of the first drain layer is 20 nm to 30 nm, and the thickness of the second drain layer is 150 nm to 200 nm; magnetron sputtering is used to deposit electrode metals, and rapid annealing is used to form an ohmic contact between the source 32 and the upper surface of the first second region 12, the first source layer is in contact with the upper surface of the first second region 12, the thickness of the first source layer is 20 nm to 30 nm, and the thickness of the second source layer is 150 nm to 200 nm.
[0135] In this embodiment, a transistor is formed by setting the gate 33 in the recess 23b, setting the drain 31 in the first opening 23c, and setting the source 32 in the second opening 23d, thereby realizing the manufacture of the transistor.
[0136] In related technologies, the epitaxial growth of AlGaN with gradient Al composition involves variable doping in the vertical direction. However, barrier layers with different Al compositions in the lateral direction are difficult to achieve in terms of fabrication.
[0137] In this embodiment, the thickness of the barrier layer 10 can be increased stepwise from the internal region of the barrier layer 10 towards the first and second directions by an etching process, which is easy to implement in terms of process.
[0138] In this embodiment, an AlGaN barrier layer 10 with a laterally varying thickness is introduced into the GaN HEMT transistor to form a groove 23b gate enhancement GaN HEMT transistor. This adjusts the polarization intensity between AlGaN / GaN, thereby improving the two-dimensional electron gas concentration at the AlGaN / GaN heterojunction. The two-dimensional electron gas in the channel increases from the gate 33 to the source 32 and drain 31, thus adjusting the lateral electric field distribution of the transistor, reducing the leakage current of the transistor, and thereby increasing the breakdown voltage of the transistor.
[0139] In this embodiment, the horizontally varying barrier layer 10 causes the polarization intensity between AlGaN / GaN cells to gradually increase from the gate 33 towards both the source 32 and drain 31. The polarization is weakest below the gate 33, resulting in the lowest two-dimensional electron gas concentration, keeping the transistor in a normally off state. The two-dimensional electron gas concentration increases from the gate 33 towards both the source 32 and drain 31. When the applied gate voltage exceeds the threshold voltage, GaN electrons replenish the area below the gate 33, turning the transistor on. By adjusting the concentration of the two-dimensional electron gas in the horizontal direction, the gate control capability of the transistor is improved, the electric field distribution in the horizontal direction is optimized, the off-state current of the transistor is reduced, and the breakdown voltage of the transistor is increased.
[0140] In this embodiment, an initial barrier layer 10a, an isolation layer 21, and a channel layer 22 are formed. The initial barrier layer 10a is disposed on the isolation layer 21. Multiple etching operations are then performed on the initial barrier layer 10a to form the barrier layer 10. A gate 33 is then disposed above the inner region of the barrier layer 10, a drain 31 is disposed at the first boundary of the barrier layer 10, and a source 32 is disposed at the second boundary of the barrier layer 10 to form a transistor. The isolation layer 21 of the transistor is disposed on the channel layer 22, and the barrier layer 10 is disposed on the isolation layer 21. Since the thickness of the barrier layer 10 increases in steps from the inner region of the barrier layer 10 towards the first and second directions (the first and second directions are opposite), and the first boundary of the barrier layer 10 has a drain 31, and the second boundary of the barrier layer 10 has a source 32, the second boundary of the barrier layer 10 is disposed on the barrier layer 21. In the first direction of the first boundary of the barrier layer 10, a gate 33 is disposed above the internal region of the barrier layer 10. The thickness of the barrier layer 10 increases in steps from the region below the gate 33 to the region below the drain 31 and the region below the source 32. Since the two-dimensional electron gas concentration of the channel layer 22 below the region of the barrier layer 10 is positively correlated with the thickness of the region of the barrier layer 10, the two-dimensional electron gas concentration of the channel layer 22 increases in steps from the region below the gate 33 to the region below the drain 31 and the region below the source 32. This results in a smooth electric field distribution between the region of the channel layer 22 below the gate 33 and the region of the channel layer 22 below the drain 31, and between the region of the channel layer 22 below the gate 33 and the region of the channel layer 22 below the source 32. Compared with the non-smooth electric field distribution of the channel layer in related technologies, this improves the voltage withstand capability of the transistor, thereby adapting to high-voltage scenarios.
[0141] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0142] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A transistor, characterized in that, include: Barrier layer (10), isolation layer (21), channel layer (22), drain (31), source (32) and gate (33); The isolation layer (21) is disposed on the channel layer (22); The barrier layer (10) is disposed on the isolation layer (21). The thickness of the barrier layer (10) increases from the internal region of the barrier layer (10) towards the first direction and the second direction respectively. The drain (31) is disposed adjacent to the first boundary of the barrier layer (10), the source (32) is disposed adjacent to the second boundary of the barrier layer (10), and the gate (33) is disposed above the internal region of the barrier layer (10). Wherein, the first direction is opposite to the second direction; the second boundary of the barrier layer (10) is disposed in the first direction of the first boundary of the barrier layer (10); the two-dimensional electron gas concentration of the channel layer (22) is positively correlated with the thickness of the corresponding region of the barrier layer (10).
2. The transistor according to claim 1, characterized in that, The barrier layer (10) includes n first regions (11) and m second regions (12), where n and m are both positive integers; The first first region (11) is disposed at the first boundary of the barrier layer (10), and the drain (31) is disposed adjacent to the first first region (11). The (i+1)th first region (11) is disposed adjacent to the first direction of the ith first region (11), and the thickness of the (i+1)th first region (11) is less than the thickness of the ith first region (11). The first second region (12) is disposed at the second boundary of the barrier layer (10), and the source (32) is disposed adjacent to the first second region (12). The (j+1)th second region (12) is disposed adjacent to the second direction of the jth second region (12), and the thickness of the (j+1)th second region (12) is less than the thickness of the jth second region (12). The mth second region (12) is disposed in the first direction of the nth first region (11), and the gate (33) is disposed between the (m-1)th second region (12) and the (n-1)th first region (11). Where i is a positive integer less than n, and j is a positive integer less than m.
3. The transistor according to claim 2, characterized in that, The nth first region (11) and the mth second region (12) are separated by a preset distance; The gate (33) is disposed between the nth first region (11) and the mth second region (12).
4. The transistor according to claim 2, characterized in that, The nth first region (11) is adjacent to the mth second region (12); the thickness of the nth first region (11) is less than the thickness of the mth second region (12); The gate (33) is disposed adjacent to the nth first region (11).
5. The transistor according to claim 2, characterized in that, The thickness of the kth second region (12) is equal to the thickness of the kth first region (11), where k is a positive integer less than or equal to m.
6. The transistor according to claim 2, characterized in that, The total width of the n first regions (11) is greater than the total width of the m second regions (12).
7. The transistor according to claim 1, characterized in that, The transistor also includes a passivation layer (23); The passivation layer (23) is disposed adjacent to the barrier layer (10). The passivation layer (23) is provided with a groove (23b), a first opening (23c) and a second opening (23d). The groove (23b) is disposed above the internal region of the barrier layer (10). The first opening (23c) is disposed adjacent to the first boundary of the barrier layer (10). The second opening (23d) is disposed adjacent to the second boundary of the barrier layer (10). The gate (33) is disposed in the groove (23b); The drain electrode (31) is disposed in the first opening (23c), and the drain electrode (31) is disposed adjacent to the barrier layer (10); The source electrode (32) is disposed in the second opening (23d), and the source electrode (32) is disposed adjacent to the barrier layer (10).
8. The transistor according to claim 1, characterized in that, The transistor further includes an insertion layer (24) disposed between the channel layer (22) and the isolation layer (21).
9. The transistor according to claim 1, characterized in that, The transistor further includes a substrate layer (25) disposed below the channel layer (22).
10. The transistor according to claim 9, characterized in that, The transistor further includes a nucleation layer (26) disposed between the channel layer (22) and the substrate layer (25).
11. The transistor according to claim 10, characterized in that, The transistor further includes a buffer layer (27) disposed between the channel layer (22) and the nucleation layer (26).
12. An electronic device, characterized in that, Includes the transistor as described in any one of claims 1 to 11.