Semiconductor structure and method of forming the same
By adjusting the height of the fins and the design of the gate structure in the semiconductor structure, the problem of insufficient performance of semiconductor devices under high density and high integration was solved, achieving better gate filling performance and high voltage resistance, and improving the working performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-06-03
- Publication Date
- 2026-06-05
AI Technical Summary
As the density and integration of semiconductor devices increase, the shortening of the gate size of planar transistors leads to a weakening of the channel current control capability, resulting in short-channel effects and increased leakage current, which affects the electrical performance of semiconductor devices. The performance of fin field-effect transistors is difficult to improve as the feature size is further reduced.
In a semiconductor structure, by removing a portion of the initial fin exposed above the isolation layer in the channel region in the first device region, the remaining initial fin is retained as the first fin, and a first gate oxide layer and gate structure covering the channel region are formed, including a high-k dielectric layer and a gate electrode layer, with the top of the source/drain doped layer higher than the top of the fin in the channel region.
The aspect ratio of the gap between adjacent fins in the channel region is reduced, which improves the fillability of the gate structure, reduces the probability of void defects, and increases the high voltage withstand performance of the first device, thereby improving the working performance of the semiconductor structure.
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Figure CN115440818B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.
[0003] To better adapt to the shrinking feature size, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. However, with further reductions in feature size, it is difficult to further improve the performance of FinFETs. Summary of the Invention
[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a first device region for forming a first device; a fin protruding from the substrate, the fin including a first fin located in the first device region, the fin including a channel region along its extending direction; an isolation layer located on the substrate and covering a portion of the sidewalls of the fin, the top of the isolation layer being lower than the top of the fin in the channel region, the portion of the first fin above the isolation layer serving as a first effective fin; a first gate oxide layer covering the top and sidewalls of the first effective fin in the channel region; a gate structure located on the substrate and spanning the first fin, the gate structure including a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer; and source / drain doped layers located in the fins on both sides of the gate structure, the top of the source / drain doped layers being higher than the top of the first fin in the channel region in the first device region.
[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein an initial fin protruding from the substrate and an isolation layer located on the substrate and covering a portion of the sidewalls of the initial fin are formed on the substrate, the substrate including a first device region for forming a first device, and the initial fin including a channel region along the extending direction of the initial fin; in the first device region, removing a portion of the initial fin exposed above the isolation layer in the channel region, retaining the remaining initial fin as a first fin; forming a first gate oxide layer, the first gate oxide layer covering the top and sidewalls of the first fin in the channel region; after forming the first gate oxide layer, forming a gate structure spanning the first fin in the channel region on the isolation layer, the gate structure including a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] In the semiconductor structure provided by this embodiment of the invention, with the trend of increasingly compact semiconductor structures, in the first device region, the top of the source / drain doped layer is higher than the top of the first fin of the channel region. That is, the height of the first fin of the channel region is reduced. This reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure and improves the filling performance of the gate structure between adjacent first fins in the channel region. At the same time, it reduces the probability of void defects caused by excessive filling depth between adjacent first fins in the channel region when forming the gate structure. Moreover, the lower top of the first fin in the channel region is beneficial to the formation of a thicker first gate oxide layer, thereby increasing the high voltage withstand performance of the first device. All of the above are beneficial to improving the working performance of the semiconductor structure.
[0009] In the semiconductor structure formation method provided by this embodiment of the invention, under the trend of increasingly compact semiconductor structures, in the first device region, the initial fins exposed above the isolation layer in the channel region are removed, and the remaining initial fins are retained as first fins. This reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure and improves the filling performance of the gate structure between adjacent first fins in the channel region. At the same time, it reduces the probability of void defects caused by excessive filling depth between adjacent first fins in the channel region when forming the gate structure. Moreover, the top of the first fins in the channel region is relatively low, which is beneficial to forming a thicker first gate oxide layer according to the device performance requirements, thereby increasing the high voltage withstand performance of the first device. In summary, all of the above are beneficial to improving the working performance of the semiconductor structure. Attached Figure Description
[0010] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure;
[0011] Figures 6 to 9 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0012] Figures 10 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0013] The performance of current semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures still needs improvement, using one semiconductor structure formation method as an example.
[0014] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0015] Reference Figure 1 and Figure 2 , Figure 1 It is a top view. Figure 2 yes Figure 1 A cross-sectional view along the AA direction is provided, showing a substrate 10 with fins 20 protruding from it. The substrate 10 includes a first device region 10I for forming a first device and a second device region 10C for forming a second device. The operating voltage of the first device is greater than the operating voltage of the second device. An interlayer dielectric layer 13 (e.g., ...) is formed on the substrate 10. Figure 1 As shown), a gate opening 15 is formed in the interlayer dielectric layer 13 (as shown). Figure 1 As shown, the gate opening 15 spans the fin 20. Along the extending direction of the fin 20, the area of the fin 20 exposed by the gate opening 15 serves as the channel region 20c. A pseudo-gate oxide layer 30 is also formed on the fin 20, which covers the top and sidewalls of the fin 20 in the channel region 20c.
[0016] refer to Figure 3 Remove the pseudo-gate oxide layer 30 to expose the surface of the fin 20 of the channel region 20c.
[0017] refer to Figure 4 After removing the pseudo gate oxide layer 30, a gate oxide layer (not shown) is formed on the fin 20. The gate oxide layer covers the top and sidewalls of the fin 20 in the channel region 20c. The gate oxide layer includes a first gate oxide layer 31 located in the first device region 10I and a second gate oxide layer 32 located in the second device region 10C.
[0018] Since the operating voltage of the first device is greater than that of the second device, the thickness of the first gate oxide layer 31 in the first device region 10I is usually greater than the thickness of the second gate oxide layer 32 in the second device region 10C.
[0019] refer to Figure 5 After the gate oxide layer is formed, a gate structure 50 is formed in the gate opening 15, which spans the channel region 20c and includes a high-k dielectric layer 51 covering the gate oxide layer and a gate electrode layer 52 located on the high-k dielectric layer 51.
[0020] As the density and integration of semiconductor devices increase, the spacing between adjacent fins 20 continuously decreases, meaning the aspect ratio between adjacent fins 20 continuously increases. Consequently, the filling performance of the gate structure 50 between adjacent fins 20 becomes increasingly poor. This is especially true for the first device region 10I, where the first gate oxide layer 31 is typically thicker. After the formation of the gate oxide layer, the spacing between adjacent fins 20 in the first device region 10I is further reduced, meaning the aspect ratio between adjacent fins 20 in the first device region 10I is further increased. This further increases the difficulty of filling the gate structure 50 between adjacent fins 20 in the first device region 10I. At the same time, it also increases the probability of void defects in the gate structure 50 due to poor filling performance, affecting the working performance of the semiconductor structure.
[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein an initial fin protruding from the substrate and an isolation layer located on the substrate and covering a portion of the sidewalls of the initial fin are formed on the substrate, the substrate including a first device region for forming a first device, and the initial fin including a channel region along the extending direction of the initial fin; in the first device region, removing a portion of the initial fin exposed above the isolation layer in the channel region, retaining the remaining initial fin as a first fin; forming a first gate oxide layer, the first gate oxide layer covering the top and sidewalls of the first fin in the channel region; after forming the first gate oxide layer, forming a gate structure spanning the first fin in the channel region on the isolation layer, the gate structure including a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer.
[0022] In the semiconductor structure formation method provided by this embodiment of the invention, under the trend of increasingly compact semiconductor structures, in the first device region, the initial fins exposed above the isolation layer in the channel region are removed, and the remaining initial fins are retained as first fins. This reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure and improves the filling performance of the gate structure between adjacent first fins in the channel region. At the same time, it reduces the probability of void defects caused by excessive filling depth between adjacent first fins in the channel region when forming the gate structure. Moreover, the top of the first fins in the channel region is relatively low, which is beneficial to forming a thicker first gate oxide layer according to the device performance requirements, thereby increasing the high voltage withstand performance of the first device. In summary, all of the above are beneficial to improving the working performance of the semiconductor structure.
[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0024] refer to Figures 6 to 9 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 6 It is a top view. Figure 7 yes Figure 6 Cross-sectional view based on the AA direction, Figure 8 yes Figure 6 Sectional view based on the BB direction. Figure 9 yes Figure 6 Sectional view based on the CC direction.
[0025] The semiconductor structure includes: a substrate 101, including a first device region 101I for forming a first device; and a fin (not shown) protruding from the substrate 101, the fin including a first fin 211 located in the first device region 101I. Along the extending direction of the fin, the fin includes a channel region 201c (e.g., Figure 11As shown in the diagram, an isolation layer 121 is located on the substrate 101 and covers part of the sidewalls of the fin. The top of the isolation layer 121 is lower than the top of the fin in the channel region 201c. The portion of the first fin 211 above the isolation layer 121 serves as the first effective fin 231. A first gate oxide layer 311 covers the top and sidewalls of the first effective fin 231 in the channel region 201c. A gate structure 501 is located on the substrate 101 and spans the first fin 211. The gate structure 501 includes a high-k dielectric layer 511 covering the first gate oxide layer 311 and a gate electrode layer 521 located on the high-k dielectric layer 511. A source / drain doped layer 161 is located in the fins on both sides of the gate structure 501. In the first device region 101I, the top of the source / drain doped layer 161 is higher than the top of the first fin 211 in the channel region 201c.
[0026] The substrate 101 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a fin field-effect transistor.
[0027] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0028] In this embodiment, the substrate 101 includes a first device region 101I for forming a first device and a second device region 101C for forming a second device, wherein the operating voltage of the first device is greater than the operating voltage of the second device.
[0029] In this embodiment, the first device is an input / output (I / O) device, and the second device is a core device. The core device is used to implement the main functions of the integrated circuit, and the I / O device is used to provide corresponding input signals to the core device or output corresponding signals from the core device. The operating voltage of the I / O device is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the I / O device is 1.0V to 3.5V.
[0030] It should be noted that the first device region 101I and the second device region 101C may be adjacent or not.
[0031] In this embodiment, taking a fin field-effect transistor as an example, the semiconductor structure includes a fin protruding from the substrate 101, and the fin is used to provide a channel for the fin field-effect transistor.
[0032] In this embodiment, the fin and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.
[0033] In this embodiment, the fin includes a first fin 211 located in the first device region 101I and a second fin 221 located in the second device region 101C. The first fin 211 is used to provide a channel for the first device, and the second fin 221 is used to provide a channel for the second device.
[0034] refer to Figure 6 Along the extending direction of the fin (e.g. Figure 6 (As shown in the X direction), the fin includes a channel region 201c. The fin of the channel region 201c serves as a channel for a transistor.
[0035] In this embodiment, in the channel region 201c, the top of the first fin 211 is lower than the top of the second fin 221.
[0036] If the operating voltage of the first device is greater than that of the second device, the top of the first fin 211 in the channel region 201c is lower. This reduces the aspect ratio of the gap between adjacent first fins 211 in the channel region 201c, which is beneficial for forming a thicker first gate oxide layer 311, thereby increasing the high voltage resistance of the first device and thus improving the working performance of the semiconductor structure.
[0037] In this embodiment, the material of the first fin 211 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material; the material of the second fin 221 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material.
[0038] Specifically, the material of the first fin 211 is determined according to the performance of the first device, and the material of the second fin 221 is determined according to the performance of the second device.
[0039] In this embodiment, the material of the fin is the same as the material of the substrate 101. The material of the first fin 211 is silicon, and the material of the second fin 221 is also silicon.
[0040] The isolation layer 121 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors.
[0041] The material of the isolation layer 121 is an insulating material. In this embodiment, the material of the isolation layer 121 is silicon oxide.
[0042] In this embodiment, the isolation layer 121 covers part of the sidewall of the fin, and the top of the isolation layer 121 is lower than the top of the fin of the channel region 201c, so that the fin at a certain height of the channel region 201c can serve as the channel of the transistor.
[0043] Specifically, the portion of the first fin 211 above the isolation layer 121 serves as the first effective fin 231, and the portion of the second fin 221 above the isolation layer 121 serves as the second effective fin 241, thereby enabling the transistor to use only the first effective fin 231 and the second effective fin 241 as the channel.
[0044] In the channel region 201c, if the top of the first fin 211 is lower than the top of the second fin 221, then the top of the first effective fin 231 is lower than the top of the second effective fin 241.
[0045] In this embodiment, in the channel region 201c, the ratio of the height d1 of the first effective fin 231 to the height d2 of the second effective fin 241 should not be too large or too small. If the ratio of the height d1 of the first effective fin 231 to the height d2 of the second effective fin 241 is too large, the height d1 of the first effective fin 231 will be too large, making it difficult to reduce the aspect ratio of the gap between adjacent first effective fins 231 in the first device region 101I. This makes it difficult to form a thicker first gate oxide layer 311, thus making it difficult to increase the high voltage withstand performance of the first device. At the same time, when forming the gate structure 501, the excessive filling depth between adjacent first effective fins 231 in the channel region 201c can easily generate void defects, affecting the filling performance of the gate structure 501 and thus affecting the working performance of the semiconductor structure. If the ratio of the height d1 of the first effective fin 231 to the height d2 of the second effective fin 241 is too small, the height d1 of the first effective fin 231 will be too small, making it difficult for the first effective fin 231 to have a sufficient height as the channel of the first device, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the channel region 201c, the height d1 of the first effective fin 231 is 5% to 95% of the height d2 of the second effective fin 241. For example, the height d1 of the first effective fin 231 is 30%, 50%, or 70% of the height d2 of the second effective fin 241.
[0046] The first gate oxide layer 311 is used to isolate the gate structure 501 and the first effective fin 231, and the second gate oxide layer 321 is used to isolate the gate structure 501 and the second effective fin 241.
[0047] In this embodiment, the operating voltage of the first device is greater than that of the second device, so the thickness of the second gate oxide layer 321 is less than the thickness of the first gate oxide layer 311. The larger thickness of the first gate oxide layer 311 improves the breakdown resistance between the gate structure 501 and the first effective fin 231 in the first device region 101I, thereby enabling the first device to operate at a higher voltage.
[0048] Since the first gate oxide layer 311 and the second gate oxide layer 321 need to have good isolation performance, in this embodiment, the material of the first gate oxide layer 311 includes one or two of SiO2 and La2O3; the material of the second gate oxide layer 321 includes one or two of SiO2 and La2O3.
[0049] The gate structure 501 is used to control the opening and closing of the transistor's channel. In this embodiment, the gate structure 501 is a metal gate structure.
[0050] The high-k dielectric layer 511 is used to isolate the gate electrode layer 521 from the first effective fin 231 and the second effective fin 241, and to reduce the leakage probability of the semiconductor structure.
[0051] In this embodiment, the high-k dielectric layer 511 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k dielectric layer 511 is made of one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.
[0052] In this embodiment, the material of the gate electrode layer 521 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer 521 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.
[0053] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.
[0054] In this embodiment, the semiconductor structure further includes a sidewall 141 that covers the sidewall of the gate structure 501.
[0055] The sidewall 141 is used to protect the sidewalls of the gate structure 501. The sidewall 141 can be a single-layer structure or a multilayer structure, and the material of the sidewall 141 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 141 is a single-layer structure, and the material of the sidewall 141 is silicon nitride.
[0056] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 131 located on the isolation layer 121. The interlayer dielectric layer 131 covers the sidewall of the sidewall 141 and exposes the top of the gate structure 501.
[0057] The interlayer dielectric layer 131 serves to isolate adjacent devices and also provides a process basis for forming the gate structure 501.
[0058] The material of the interlayer dielectric layer 131 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0059] During the formation of the semiconductor structure, after forming a first source / drain doped layer 161 in the first fins 211 on both sides of the gate structure 501, an interlayer dielectric layer 131 is formed. The interlayer dielectric layer 131 covers the source / drain doped layer 161 and exposes the first fins 211 in the channel region 201c. A portion of the first fins 211 exposed in the channel region 201c by the interlayer dielectric layer 131 is removed. Therefore, the top of the source / drain doped layer 161 is higher than the top of the first fins 211 in the channel region 201c.
[0060] With the trend of increasingly compact semiconductor structures, in the first device region 101I, the top of the source / drain doped layer 161 is higher than the top of the first fin 211 of the channel region 201c. In other words, the height of the first fin 211 of the channel region 201c is reduced. This reduces the aspect ratio of the gap between adjacent first fins 211 in the channel region 201c, which is beneficial for the formation of the gate structure 501 and improves the filling performance of the gate structure 501 between adjacent first fins 211 in the channel region 201c. At the same time, it reduces the probability of void defects caused by excessive filling depth between adjacent first fins 211 in the channel region 201c when forming the gate structure 501. Moreover, the lower top of the first fin 211 in the channel region 201c is conducive to the formation of a thicker first gate oxide layer 311, thereby increasing the high voltage withstand performance of the first device. In summary, all of the above are beneficial to improving the working performance of the semiconductor structure.
[0061] The source / drain doped layer 161 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 161 is the same as the channel conductivity type of the corresponding transistor. For an NMOS transistor, the dopant ions in the source / drain doped layer 161 are N-type ions, including P ions, As ions, or Sb ions; for a PMOS transistor, the dopant ions in the source / drain doped layer 161 are P-type ions, including B ions, Ga ions, or In ions.
[0062] Figures 10 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0063] Reference Figures 10 to 12 , Figure 10 It is a top view. Figure 11 yes Figure 10 Cross-sectional view based on the AA direction, Figure 12 yes Figure 10 A cross-sectional view along the BB direction shows a substrate 100. An initial fin 200 protruding from the substrate 100 and an isolation layer 120 located on the substrate 100 and covering a portion of the sidewalls of the initial fin 200 are formed on the substrate 100. The substrate 100 includes a first device region 100I for forming a first device. Along the extending direction of the initial fin 200, the initial fin includes a channel region 200c (e.g., ...). Figure 10 (As shown).
[0064] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a finned field-effect transistor.
[0065] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0066] In this embodiment, the substrate 100 includes a first device region 100I for forming a first device, and a second device region 100C for forming a second device, wherein the operating voltage of the first device is greater than the operating voltage of the second device.
[0067] In this embodiment, the first device is an input / output (I / O) device, and the second device is a core device. The core device is used to implement the main functions of the integrated circuit, and the I / O device is used to provide corresponding input signals to the core device or output corresponding signals from the core device. The operating voltage of the I / O device is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the I / O device is 1.0V to 3.5V.
[0068] It should be noted that the first device region 100I and the second device region 100C may be adjacent or not.
[0069] In this embodiment, taking the semiconductor structure as a fin field-effect transistor as an example, an initial fin portion 200 protruding from the substrate 100 is formed on the substrate 100, and the initial fin portion 200 is used to provide the channel of the fin field-effect transistor.
[0070] In this embodiment, the initial fin 200 and the substrate 100 are integrally formed. In other embodiments, the initial fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the initial fin.
[0071] refer to Figure 10 Along the extension direction of the initial fin 200 (e.g.) Figure 10 (As shown in the X direction), the initial fin 200 includes a channel region 200c. The initial fin 200 of the channel region 200c is used as a channel for a transistor.
[0072] In this embodiment, the material of the initial fin 200 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. In this embodiment, the material of the initial fin 200 is the same as the material of the substrate 100, and the material of the initial fin 200 is silicon.
[0073] In this embodiment, the initial fin 200 on the substrate 100 of the second device region 100C serves as the second fin 220, which is used to provide a channel for the second device.
[0074] In this embodiment, the material of the second fin 220 is silicon.
[0075] The isolation layer 120 serves as a shallow trench isolation structure, used to isolate adjacent transistors.
[0076] The insulating layer 120 is made of an insulating material. In this embodiment, the insulating layer 120 is made of silicon oxide.
[0077] In this embodiment, the isolation layer 120 covers a portion of the sidewall of the initial fin 200, and the top of the isolation layer 120 is lower than the top of the initial fin 200 in the channel region 200c, so that the portion of the initial fin 200 above the isolation layer 120 is used to provide a channel.
[0078] In this embodiment, the height at which the initial fin protrudes from the isolation layer is the first height d2.
[0079] In this embodiment, during the step of providing the substrate 100, a pseudo-gate oxide layer 300 is also formed on the top and sidewalls of the initial fin 200 exposed in the isolation layer 120.
[0080] As an example, the material of the pseudo-gate oxide layer 300 is silicon oxide.
[0081] In this embodiment, an interlayer dielectric layer 130 is formed on the isolation layer 120, and a gate opening 150 is formed in the interlayer dielectric layer 130. The gate opening 150 spans the initial fin 200 and exposes the top and sidewall of the initial fin 200 of the channel region 200c. Active drain doped layers 160 are formed in the initial fins 200 on both sides of the gate opening 150.
[0082] The interlayer dielectric layer 130 serves to isolate adjacent devices and also provides a process basis for forming the gate opening 150.
[0083] The material of the interlayer dielectric layer 130 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0084] The gate opening 150 is used to provide space for the subsequent formation of the gate structure.
[0085] The source / drain doped layer 160 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 160 is the same as the channel conductivity type of the corresponding transistor. For an NMOS transistor, the dopant ions in the source / drain doped layer 160 are N-type ions, including P-ions, As-ions, or Sb-ions; for a PMOS transistor, the dopant ions in the source / drain doped layer 160 are P-type ions, including B-ions, Ga-ions, or In-ions.
[0086] In this embodiment, a sidewall 140 is also formed on the sidewall of the gate opening 150, and the interlayer dielectric layer 130 covers the sidewall of the sidewall 140.
[0087] The sidewall 140 is used to protect the sidewalls of the subsequently formed gate structure. The sidewall 140 can be a single-layer structure or a multilayer structure, and the material of the sidewall 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 140 is a single-layer structure, and the material of the sidewall 140 is silicon nitride.
[0088] In this embodiment, before forming the interlayer dielectric layer 130, the method further includes forming a pseudo-gate layer (not shown) on the isolation layer 120, the pseudo-gate layer spanning the initial fin 200 and covering the top and sidewalls of the initial fin 200 of the channel region 200c.
[0089] The pseudo-gate layer is used to reserve space for the subsequent formation of the gate structure.
[0090] In this embodiment, the pseudo gate layer covers the pseudo gate oxide layer 300, and the sidewall 140 covers the sidewall of the pseudo gate layer.
[0091] As an example, the material of the pseudo-gate layer is polycrystalline silicon.
[0092] In this embodiment, source and drain doped layers 160 are formed in the initial fins 200 on both sides of the dummy gate layer. After the source and drain doped layers 160 are formed, the interlayer dielectric layer 130 is formed on the substrate 100 on the side of the dummy gate layer. The interlayer dielectric layer 130 exposes the top of the dummy gate layer to prepare for the subsequent removal of the dummy gate layer.
[0093] In this embodiment, the step of forming the gate opening 150 includes: removing the dummy gate layer.
[0094] Reference Figure 13 and Figure 14 , Figure 13 and Figure 14 Based on Figure 11 In the cross-sectional view of the first device region 100I, the initial fin 200 of a portion of the height of the channel region 200c exposed above the isolation layer 120 is removed, and the remaining initial fin 200 is retained as the first fin 210.
[0095] With the trend towards increasingly compact semiconductor structures, in the first device region 100I, the initial fins 200 exposed above the isolation layer 120 in the channel region 200c are removed, and the remaining initial fins 200 are retained as first fins 210. This reduces the aspect ratio of the gap between adjacent first fins 210 in the channel region 200c, which is beneficial for the formation of the gate structure and improves the filling performance of the gate structure between adjacent first fins 210 in the channel region 200c. At the same time, it reduces the probability of void defects caused by excessive filling depth between adjacent first fins 210 in the channel region 200c when forming the gate structure. Moreover, the lower top of the first fins 210 in the channel region 200c facilitates the formation of a thicker first gate oxide layer according to device performance requirements, thereby increasing the high voltage withstand performance of the first device. In summary, all of the above are beneficial for improving the working performance of the semiconductor structure.
[0096] The first fin 210 is used to provide a channel for the first device.
[0097] In this embodiment, the material of the first fin 210 is silicon.
[0098] In this embodiment, in the step of removing the initial fin portion 200 exposed above the isolation layer 120 in the channel region 200c in the first device region 100I, a dry etching process is used to remove the initial fin portion 200 exposed above the isolation layer 120 in the channel region 200c.
[0099] The dry etching process has the characteristics of anisotropic etching and is more directional, which is beneficial to improving the formation quality and dimensional accuracy of the first fin 210. Moreover, the dry etching process can better control the process parameters, has high process controllability, and is easy to obtain more accurate pattern transfer.
[0100] In this embodiment, the height by which the remaining initial fins 200 of the channel region 200c expose the isolation layer 120 is the second height d1. The proportion of the second height d1 to the first height d2 should not be too large or too small. If the proportion of the second height d1 to the first height d2 is too large, the height d1 of the first fin 210 will be too large, making it difficult to reduce the aspect ratio of the gap between adjacent first fins 210 in the first device region 100I. This makes it difficult to form a thicker first gate oxide layer, thus making it difficult to increase the high voltage withstand performance of the first device. At the same time, when forming the gate structure, the excessive filling depth between adjacent first fins 210 in the channel region 200c can easily generate void defects, affecting the filling performance of the gate structure and thus affecting the working performance of the semiconductor structure. If the proportion of the second height d1 to the first height d2 is too small, the height d1 of the first fin 210 will be too small, making it difficult for the first fin 210 to have a sufficient height as the channel of the first device, thus affecting the performance of the semiconductor structure. Therefore, in the first device region 100I, during the step of removing a portion of the initial fin 200 exposed above the isolation layer 120 in the channel region 200c, the remaining height of the initial fin 200 exposed above the isolation layer 120 in the channel region 200c is a second height d1, and the second height d1 accounts for 5% to 95% of the first height d2. For example, the second height d1 is 30%, 50%, or 70% of the first height d2.
[0101] Specifically, refer to Figure 13 In the first device region 100I, the step of removing the initial fin 200 exposed at a certain height above the isolation layer 120 in the channel region 200c includes: forming a first mask layer 410 covering the second fin 220, wherein the first mask layer 410 exposes the initial fin 200 in the channel region 200c in the first device region 100I.
[0102] In the first device region 100I, the first mask layer 410 exposes the initial fin 200 of the channel region 200c in preparation for removing a portion of the initial fin 200. At the same time, the first mask layer 410 also protects the second fin 220 located in the second device region 100C.
[0103] In this embodiment, the first mask layer 410 is a stacked structure, and the first mask layer 410 includes a planarization layer (not shown) and a photoresist layer (not shown) located on the planarization layer.
[0104] In this embodiment, the planarization layer is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost; moreover, using spin-on carbon helps to improve the flatness of the top surface of the planarization layer.
[0105] In this embodiment, in the step of forming the first mask layer 410, the first mask layer 410 covers the pseudo gate oxide layer 300 located on the second fin 220.
[0106] refer to Figure 14 After the first mask layer 410 is formed, before removing the initial fin portion 200 of the channel region 200c exposed by the first mask layer 410, the method further includes: removing the pseudo gate oxide layer 300 exposed by the first mask layer 410.
[0107] Remove the dummy gate oxide layer 300 exposed by the first mask layer 410 to expose the surface of the first fin 210, in preparation for the subsequent formation of the first gate oxide layer.
[0108] Continue to refer to Figure 14 In the first device region 100I, the initial fin 200 of the channel region 200c exposed by the first mask layer 410 is removed, and the remaining initial fin 200 is retained as the first fin 210.
[0109] Remove the initial fin 200 of the channel region 200c exposed by the first mask layer 410 to reduce damage to the second fin 220 during the removal of the initial fin 200 of a portion of the height in the first device region 100I.
[0110] Specifically, along the gate opening 150 of the first device region 100I, a portion of the initial fin 200 of the channel region 200c is removed.
[0111] refer to Figure 15 , Figure 15 Based on Figure 14 The cross-sectional view shows that after the first fin 210 is formed, the first mask layer 410 is removed to prepare for the subsequent formation of the second gate oxide layer.
[0112] Specifically, the dummy gate oxide layer 300 in the gate opening 150 of the first device region 100I is removed.
[0113] Continue to refer to Figure 15 A first gate oxide layer 310 is formed, which covers the top and sidewalls of the first fin 210 of the channel region 200c.
[0114] The first gate oxide layer 310 is used to isolate the subsequently formed gate structure and the first fin 210.
[0115] In this embodiment, an oxidation process is used to form the first gate oxide layer 310, so that the first gate oxide layer 310 is formed only on the first fin 210 exposed on the top and sidewalls of the isolation layer 120.
[0116] The first gate oxide layer 310 needs to have good isolation performance. Therefore, in this embodiment, the material of the first gate oxide layer 310 includes one or both of SiO2 and La2O3.
[0117] It should be noted that a pseudo-gate oxide layer 300 is formed on the top and sidewalls of the second fin 220. During the formation of the first gate oxide layer 310, the pseudo-gate oxide layer 300 protects the top and sidewalls of the second fin 220, so that the first gate oxide layer 310 is selectively formed on the top and sidewalls of the first fin 210 in the channel region 200c.
[0118] Reference Figure 16 and Figure 17 , Figure 16 and Figure 17 Based on Figure 5 The cross-sectional view shows that after the first gate oxide layer 310 is formed and before the second gate oxide layer is subsequently formed, the method further includes: forming a second mask layer 420 covering the first gate oxide layer 310, in the second device region 200C, the second mask layer 420 exposes the dummy gate oxide layer 300 located in the channel region.
[0119] The second mask layer 420 exposes the dummy gate oxide layer 300 located in the channel region, preparing for the subsequent removal of the dummy gate oxide layer 300 in the second device region 100C. At the same time, the second mask layer 420 also protects the first gate oxide layer 310 located in the first device region 100I.
[0120] In this embodiment, the second mask layer 420 is a stacked structure, and the second mask layer 420 includes a planarization layer (not shown) and a photoresist layer (not shown) located on the planarization layer.
[0121] In this embodiment, the planarization layer is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost; moreover, using spin-on carbon helps to improve the flatness of the top surface of the planarization layer.
[0122] refer to Figure 17 Remove the pseudo gate oxide layer 300 exposed by the second mask layer 420.
[0123] The dummy gate oxide layer 300 exposed by the second mask layer 420 is removed, exposing the surface of the second fin 220, in preparation for the subsequent formation of the second gate oxide layer. (See reference) Figure 18 , Figure 18 Based on Figure 17 The cross-sectional view shows that after removing the dummy gate oxide layer 300 exposed by the second mask layer 420, the second mask layer 420 is removed to prepare for the subsequent formation of the gate structure.
[0124] Continue to refer to Figure 18 Before the gate structure is formed, the method further includes forming a second gate oxide layer 320, which covers the top and sidewalls of the second fin 220 of the channel region 200c, and the thickness of the second gate oxide layer 320 is less than the thickness of the first gate oxide layer 310.
[0125] The second gate oxide layer 320 is used to isolate the subsequently formed gate structure and the second fin 220.
[0126] In this embodiment, an oxidation process is used to form the second gate oxide layer 320, so that the second gate oxide layer 320 is formed only on the second fin 220 exposed on the top and sidewalls of the isolation layer 120.
[0127] In this embodiment, the operating voltage of the first device is greater than that of the second device, therefore the thickness of the second gate oxide layer 320 is less than the thickness of the first gate oxide layer 310. A larger thickness of the first gate oxide layer 310 improves the breakdown resistance between the gate structure and the first fin 210 in the first device region 100I, thereby enabling the first device to operate at higher voltages.
[0128] The second gate oxide layer 320 needs to have good isolation performance. Therefore, in this embodiment, the material of the second gate oxide layer 320 includes one or both of SiO2 and La2O3.
[0129] It should be noted that a first gate oxide layer 310 is formed on the top and sidewalls of the first fin 210. During the formation of the second gate oxide layer 320, the first gate oxide layer 310 protects the top and sidewalls of the first fin 210, so that the second gate oxide layer 320 is selectively formed on the top and sidewalls of the second fin 220 in the channel region 200c.
[0130] Reference Figures 19 to 22 , Figure 19 Based on Figure 18 sectional view, Figure 20 This is a top view of the gate structure and fins. Figure 21 yes Figure 20 Sectional view based on the BB direction. Figure 22 yes Figure 20Based on the cross-sectional view in the CC direction, after forming the first gate oxide layer 310, a gate structure 500 spanning the first fin 210 across the channel region 200c is formed on the isolation layer 120. The gate structure 500 includes a high-k dielectric layer 510 covering the first gate oxide layer 310 and a gate electrode layer 520 located on the high-k dielectric layer 510.
[0131] In this embodiment, during the step of forming the gate structure 500, the high-k dielectric layer 510 further covers the second gate oxide layer 320.
[0132] In this embodiment, the gate structure 500 is formed in the gate opening 150.
[0133] The gate structure 500 is used to control the opening and closing of the transistor's channel. In this embodiment, the gate structure 500 is a metal gate structure.
[0134] The high-k dielectric layer 510 is used to isolate the gate electrode layer 520 from the first fin 210 and the second fin 220, and to reduce the leakage probability of the semiconductor structure.
[0135] In this embodiment, the high-k dielectric layer 510 is made of a high-k dielectric material. A high-k dielectric material is defined as a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k dielectric layer 510 is made of one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.
[0136] In this embodiment, the material of the gate electrode layer 520 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer 520 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.
[0137] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.
[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a first device region for forming the first device; A fin protrudes from the substrate, the fin including a first fin located in the first device region, and along the extending direction of the fin, the fin including a channel region; An isolation layer is located on the substrate and covers a portion of the sidewall of the fin. The top of the isolation layer is lower than the top of the fin in the channel region. The portion of the first fin that is higher than the isolation layer serves as the first effective fin. A first gate oxide layer covers the top and sidewalls of the first effective fin in the channel region; A gate structure is located on the substrate and spans the first fin. The gate structure includes a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer. The source and drain doped layers are located in the fins on both sides of the gate structure. In the first device region, the top of the source and drain doped layers is higher than the top of the first fin of the channel region. The reduction in the height of the first fin of the channel region reduces the aspect ratio of the gap between adjacent first fins in the channel region. The substrate further includes a second device region for forming a second device, wherein the operating voltage of the first device is greater than the operating voltage of the second device; The fin also includes a second fin located in the second device region, wherein in the channel region, the top of the first fin is lower than the top of the second fin; The portion of the second fin that is higher than the isolation layer serves as the second effective fin. The semiconductor structure further includes: a second gate oxide layer covering the top and sidewalls of the second effective fin of the channel region, wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer, and after the first gate oxide layer is formed, the spacing between adjacent fins of the first device region is further reduced; The gate structure also spans the second fin, and the high-k dielectric layer also covers the second gate oxide layer.
2. The semiconductor structure as described in claim 1, characterized in that, In the channel region, the height of the first effective fin is 5% to 95% of the height of the second effective fin.
3. The semiconductor structure as described in claim 1, characterized in that, The material of the first fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
4. The semiconductor structure as described in claim 1, characterized in that, The material of the second fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
5. The semiconductor structure as described in claim 1, characterized in that, The material of the first gate oxide layer includes one or two of SiO2 and La2O3; the material of the high-k dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
6. The semiconductor structure according to claim 1, characterized in that, The material of the second gate oxide layer includes one or both of SiO2 and La2O3.
7. The semiconductor structure as described in claim 1, characterized in that, The first device is an input / output device, and the second device is a core device.
8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which an initial fin is formed protruding from the substrate and an isolation layer located on the substrate and covering a portion of the sidewalls of the initial fin. The substrate includes a first device region for forming a first device, and the initial fin includes a channel region along the extension direction of the initial fin. In the first device region, the initial fin portion exposed above the isolation layer in the channel region is removed, and the remaining initial fin portion is retained as the first fin portion; the reduction in the height of the first fin portion in the channel region reduces the aspect ratio of the gap between adjacent first fin portions in the channel region; A first gate oxide layer is formed, which covers the top and sidewalls of the first fin in the channel region; after the first gate oxide layer is formed, the spacing between adjacent fins in the first device region is further reduced. After the first gate oxide layer is formed, a gate structure spanning the first fin portion of the channel region is formed on the isolation layer. The gate structure includes a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer. In the step of providing a substrate, the substrate further includes a second device region for forming a second device, wherein an initial fin on the substrate of the second device region serves as a second fin, and the operating voltage of the first device is greater than the operating voltage of the second device; Before forming the gate structure, the method further includes: forming a second gate oxide layer, the second gate oxide layer covering the top and sidewalls of the second fin of the channel region, the thickness of the second gate oxide layer being less than the thickness of the first gate oxide layer; In the step of forming the gate structure, the high-k dielectric layer further covers the second gate oxide layer.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the first device region, the step of removing the initial fin portion of the channel region exposed above the isolation layer includes: forming a first mask layer covering the second fin portion, wherein the first mask layer exposes the initial fin portion of the channel region in the first device region; In the first device region, the initial fin portion of the channel region exposed by the first mask layer is removed, and the remaining initial fin portion is retained as the first fin portion. After the first fin is formed, the first mask layer is removed.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, a pseudo-gate oxide layer is also formed on the top and sidewalls of the initial fin exposed in the isolation layer; In the step of forming the first mask layer, the first mask layer covers the pseudo gate oxide layer located on the second fin; After the first mask layer is formed, before removing the initial fin portion of the channel region exposed by the first mask layer, the method further includes: removing the pseudo gate oxide layer exposed by the first mask layer; After forming the first gate oxide layer and before forming the second gate oxide layer, the method further includes: forming a second mask layer covering the first gate oxide layer, wherein in the second device region, the second mask layer exposes a dummy gate oxide layer located in the channel region; Remove the dummy gate oxide layer exposed by the second mask layer; Remove the second mask layer.
11. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a substrate, an interlayer dielectric layer is formed on the isolation layer, a gate opening is formed in the interlayer dielectric layer, the gate opening spans the initial fin and exposes the top and sidewalls of the initial fin in the channel region, and an active drain doped layer is formed in the initial fin on both sides of the gate opening. The gate structure is formed in the gate opening.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the interlayer dielectric layer, the method further includes: forming a pseudo-gate layer on the isolation layer, the pseudo-gate layer spanning the initial fin and covering the top and sidewalls of the initial fin in the channel region; The source / drain doped layers are formed in the initial fins on both sides of the dummy gate layer; After forming the source and drain doped layers, the interlayer dielectric layer is formed on the substrate on the side of the dummy gate layer, and the interlayer dielectric layer exposes the top of the dummy gate layer. The step of forming the gate opening includes: removing the dummy gate layer.
13. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the first device region, in the step of removing the initial fin portion exposed above the isolation layer in the channel region, a dry etching process is used to remove the initial fin portion exposed above the isolation layer in the channel region.
14. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a substrate, the first device is an input / output device, and the second device is a core device.
15. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, the height at which the initial fin exposes the isolation layer is a first height; In the first device region, in the step of removing the initial fin portion of the channel region exposed above the isolation layer, the height of the remaining initial fin portion of the channel region exposed above the isolation layer is the second height, and the second height accounts for 5% to 95% of the first height.