integrated component

Abstract

The utility model provides an integrated component, include: semiconductor layer includes semiconductor channel;Gate is located on semiconductor channel;First source / drain region is located on the first side of semiconductor channel;And second source / drain region is located on the second side of semiconductor channel relative to the first side;Among them, the first source / drain region and the second source / drain region have the oxygen vacancy of first concentration, and the semiconductor channel has the oxygen vacancy of second concentration, and the oxygen vacancy of second concentration is less than the oxygen vacancy of first concentration.

Description

Technical Field

[0001] This utility model relates to an integrated component. Background Technology

[0002] In a transistor, a channel separates the first source / drain terminals from the second source / drain terminals. A channel region covers the gate. To operate the transistor, a voltage needs to be applied to the gate. When the voltage meets a device-dependent voltage threshold, a conductive channel is induced between the first and second source / drain terminals, causing current to flow between them. One factor determining the voltage threshold of a transistor with an oxide-semiconductor channel is the oxygen vacancy concentration within the oxide-semiconductor channel. Utility Model Content

[0003] This utility model embodiment provides an integrated device, including: a semiconductor layer including a semiconductor channel; a gate located on the semiconductor channel; a first source / drain region located on a first side of the semiconductor channel; and a second source / drain region located on a second side of the semiconductor channel opposite to the first side; wherein the first source / drain region and the second source / drain region have oxygen vacancies of a first concentration, and the semiconductor channel has oxygen vacancies of a second concentration, the second concentration of oxygen vacancies being less than the first concentration of oxygen vacancies.

[0004] In some embodiments, the system further includes: a first source / drain terminal electrically coupled to a first source / drain region; a first oxide layer spaced between the first source / drain terminal and the first source / drain region; a second source / drain terminal electrically coupled to a second source / drain region; and a second oxide layer spaced between the second source / drain terminal and the second source / drain region. In some embodiments, the system further includes: a gate dielectric layer located on a third side of the semiconductor channel, wherein the first source / drain terminal and the second source / drain terminal are located on a fourth side of the semiconductor channel opposite to the third side. In some embodiments, the first oxide layer and the second oxide layer extend into the semiconductor layer and have a bulk resistivity of less than 0.5 kΩ-μm. In some embodiments, a first concentration of oxygen vacancies is greater than 50%, and a second concentration of oxygen vacancies is less than 40%. In some embodiments, the first source / drain region extends from between the inner sidewalls of the second source / drain region to the outer sidewall of the gate.

[0005] This utility model provides an integrated device, comprising: a semiconductor layer including a semiconductor channel; a gate located on the semiconductor channel; a first source / drain region located on a first side of the semiconductor channel; a first source / drain terminal electrically coupled to the first source / drain region; a first oxide layer separating the first source / drain terminal from the first source / drain region and including material from the first source / drain terminal and the first source / drain region; a second source / drain region located on a second side of the semiconductor channel opposite to the first side; a second source / drain terminal electrically coupled to the second source / drain region; and a second oxide layer separating the second source / drain terminal from the second source / drain region and including material from the second source / drain terminal and the second source / drain region.

[0006] In some embodiments, a first portion of the semiconductor layer directly below the first source / drain terminal and a second portion of the semiconductor layer directly below the second source / drain terminal have oxygen vacancies of a first concentration; wherein the semiconductor channel has oxygen vacancies of a second concentration; and wherein the first concentration is greater than the second concentration. In some embodiments, an insulating layer is further included, extending directly between the first source / drain terminal and the second source / drain terminal; wherein a first oxide layer spaces the insulating layer from the first source / drain terminal; and wherein a second oxide layer spaces the insulating layer from the second source / drain terminal. In some embodiments, an outer region of the insulating layer has oxygen vacancies of a third concentration, and an inner region of the insulating layer has oxygen vacancies of a fourth concentration, the fourth concentration being less than the third concentration. In some embodiments, the semiconductor layer includes an inner sidewall surrounding and flush with the first and second source / drain terminals, wherein the first source / drain terminal is located directly above the second source / drain terminal. In some embodiments, the semiconductor layer extends from above the first source / drain region to the upper surface of the second oxide layer, and wherein the first source / drain terminal has an inner sidewall that surrounds the semiconductor channel and the first source / drain region to form a continuous ring.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 Cross-sectional views of some embodiments of transistors with varying concentrations of oxygen vacancies throughout the semiconductor layer are shown.

[0010] Figure 2A and Figure 2B Cross-sectional and three-dimensional views of some embodiments of a transistor are shown, the transistor including oxygen vacancies with varying concentrations throughout the semiconductor layer, a gate stack located below the semiconductor layer, and first and second source / drain terminals located above the semiconductor layer.

[0011] Figure 3A and Figure 3B Cross-sectional and three-dimensional views of some embodiments of a transistor are shown, the transistor including oxygen vacancies with varying concentrations throughout the semiconductor layer, and a gate stack extending from between the inner sidewalls of the first source / drain terminals to the second source / drain terminals.

[0012] Figure 4A and Figure 4B Cross-sectional and three-dimensional views of some embodiments of a transistor are shown, the transistor including oxygen vacancies with varying concentrations throughout the semiconductor layer, and gate stacks extending around the outer walls of the first and second source / drain terminals.

[0013] Figure 5 A graph showing the current density of a transistor using metal terminals with low oxide formation energy compared to a transistor using metal terminals with higher oxide formation energy is presented.

[0014] Figures 6 to 13 A series of cross-sectional views are shown of some embodiments of a method for forming a transistor, the transistor including oxygen vacancies with varying concentrations throughout a semiconductor layer, a gate stack located below the semiconductor layer, and first and second source / drain terminals located above the semiconductor layer.

[0015] Figures 14 to 20 A series of cross-sectional views are shown of some embodiments of a method for forming a transistor, the transistor including oxygen vacancies with varying concentrations throughout a semiconductor layer, and a gate stack extending from between the inner sidewalls of a first source / drain terminal to a second source / drain terminal.

[0016] Figures 21 to 26 A series of cross-sectional views are shown of some embodiments of a method for forming a transistor, the transistor including oxygen vacancies with varying concentrations throughout a semiconductor layer, and gate stacks extending around the outer walls of the first source / drain terminals and the second source / drain terminals.

[0017] Figure 27A flowchart of some embodiments of a method for forming a transistor is shown, the transistor comprising oxygen vacancies having varying concentrations throughout a semiconductor layer, a gate stack located below the semiconductor layer, and first and second source / drain terminals located above the semiconductor layer.

[0018] Figure 28 A flowchart of some embodiments of a method for forming a transistor is shown, the transistor including oxygen vacancies with varying concentrations throughout a semiconductor layer, and a gate stack extending from between the inner sidewalls of a first source / drain terminal to a second source / drain terminal.

[0019] Figure 29 A flowchart of some embodiments of a method for forming a transistor is shown, the transistor including oxygen vacancies with varying concentrations throughout a semiconductor layer, and a gate stack extending around the outer walls of the first source / drain terminals and the second source / drain terminals. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, element reference numerals and / or letters may be reused in various instances of this disclosure. Such reuse is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of explanation, this document may use spatial relative terms such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” and “upper” to describe the relationship between one component or feature shown in the figures and another component or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0022] A transistor includes a semiconductor layer having a semiconductor channel extending between a first source / drain region and a second source / drain region. A gate stack covers the semiconductor channel and includes a gate terminal and a gate dielectric layer. A voltage applied to the gate terminal drives the transistor to switch its operation between an "off" mode and an "on" mode. In the "off" mode, a depletion region (or, in the case of thin-film transistors (TFTs), the intrinsic state of the channel) isolates the first source / drain region from the second source / drain region. In the "on" mode, a voltage at the gate terminal attracts mobile charge carriers to the channel, thereby forming a conductive channel between the first source / drain region and the second source / drain region.

[0023] The voltage required to form an inversion channel is called the transistor's threshold voltage. The threshold voltage is a measure of transistor performance, and different threshold voltages are suitable for different applications (e.g., a higher threshold voltage is suitable for high-voltage applications, while a lower threshold voltage may be more ideal for lower-voltage applications, such as those utilizing newer technologies to create more compact circuit designs). Many factors determine the transistor's threshold voltage. One of these factors in designs using oxide semiconductor channels is the concentration of oxygen vacancies in the semiconductor channel (when using oxide semiconductor as the channel material). More oxygen vacancies in the semiconductor channel lower the device's threshold voltage, thus lowering the minimum voltage required to turn the device on. If the threshold voltage drops below the expected noise in the gate voltage, the noise may cause the transistor not to drive according to the applied voltage.

[0024] Another metric for transistor performance is the amount of current flowing between the first and second source / drain regions when the transistor is in "on" mode. The current density flowing through the transistor is determined by many factors, including the source / drain terminal resistance (e.g., the contact resistance between the metal source / drain terminals and the oxide semiconductor of the source / drain regions). Reducing the source / drain terminal resistance leads to an increase in the transistor's current density. One way to reduce the source / drain terminal resistance is to increase the concentration of oxygen vacancies in the source / drain regions. However, increasing the number of oxygen vacancies within the semiconductor layer can lower the transistor's threshold voltage to undesirable levels, and depositing multiple oxide semiconductor layers with different oxygen vacancy concentrations increases the number of deposition and patterning steps in the transistor fabrication process, increasing the cost and complexity of the final product. Therefore, a method is needed to increase the number of oxygen vacancies in the first and second source / drain regions without increasing the concentration of oxygen vacancies in the semiconductor channel.

[0025] This disclosure describes a transistor having a metal-oxide-semiconductor (MOS) channel, wherein the concentration of oxygen vacancies in the MOS channel varies between the source / drain regions and the semiconductor channel. A material with a low oxide formation energy is selected as the material for the first and second source / drain terminals. The low oxide formation energy results in the formation of an oxide layer between the first and second source / drain terminals and the semiconductor channel during annealing. The formation of the oxide layer attracts oxygen atoms from the first and second source / drain terminals, resulting in a higher concentration of oxygen vacancies in the first and second source / drain terminals. When an oxide material with a low resistivity (e.g., less than about 0.5 kΩ-μm) is selected as the material for the first and second source / drain terminals, the increased concentration of oxygen vacancies and the low resistivity of the oxide combine to reduce the contact resistance at the interface between the first and second source / drain terminals and the first and second source / drain regions. The reduced contact resistance increases the resulting current density of the transistor. The threshold voltage of a transistor is partly dependent on the concentration of oxygen vacancies in the channel, which is substantially unaffected by this technique. Localizing the variation in oxygen vacancy concentration to the first and second source / drain regions mitigates the threshold voltage variation of the transistor while increasing the current density, thereby improving the overall performance of the device.

[0026] Figure 1 A cross-sectional view 100 is shown of some embodiments of a transistor having varying concentrations of oxygen vacancies throughout the semiconductor layer.

[0027] A substrate 102 is overlaid on a semiconductor layer 104. The semiconductor layer 104 includes a channel 106, a first source / drain region 108, and a second source / drain region 110. The first source / drain region 108 is located on a first side of the channel 106, and the second source / drain region 110 is located on a second side of the channel 106 opposite to the first side. In some embodiments, a gate stack 112 extends beneath the semiconductor layer 104. The gate stack 112 includes a gate terminal 114 and a gate dielectric layer 116. The gate dielectric layer 116 spaces the gate terminal 114 from the semiconductor layer 104.

[0028] The first source / drain terminal 118 is covered by and electrically coupled to a first source / drain region 108. A first oxide layer 120 extends between the first source / drain terminal 118 and the first source / drain region 108. Similarly, the second source / drain terminal 122 is covered by a second source / drain region 110 and electrically coupled to it through a second oxide layer 124.

[0029] Channel 106 has a first concentration of oxygen vacancies, while the first source / drain region 108 and the second source / drain region 110 have a second concentration of oxygen vacancies greater than the first concentration. In some embodiments, the first concentration of oxygen vacancies is less than 40% (e.g., less than 40% of possible oxygen sites in channel 106 have oxygen vacancies), while the second concentration of oxygen vacancies is greater than 50% (e.g., more than 50% of possible oxygen sites in the first source / drain region 108 and the second source / drain region 100 have oxygen vacancies). The higher concentration of oxygen vacancies in the first source / drain region 108 and the second source / drain region 110 reduces the contact resistance between the first and second source / drain regions 108, 110 and the first and second source / drain terminals. The lower concentration of oxygen vacancies in channel 106 results in a threshold voltage of the transistor that is higher than the threshold voltage provided by the semiconductor layer 104 having a uniformly higher concentration of oxygen vacancies. In other words, localizing the higher concentration of oxygen vacancies to the first and second source / drain regions 108, 110 increases the current density of the transistor without sacrificing the higher threshold voltage of the transistor with the lower concentration of oxygen vacancies at the channel 106.

[0030] Figure 2A and Figure 2B Cross-sectional view 200a and three-dimensional view 200b of some embodiments of a transistor are shown. The transistor includes a semiconductor layer with varying concentrations of oxygen vacancies, a gate stack below the semiconductor layer, and first and second source / drain terminals above the semiconductor layer.

[0031] like Figure 2A As shown in cross-sectional view 200a, in some embodiments, an insulating layer 202 extends between the first source / drain terminal 118 and the second source / drain terminal 122. In some embodiments, the insulating layer 202 may be or comprise an insulating material, such as silicon dioxide (SiO2) or a similar material. The oxygen-to-silicon ratio of the silicon dioxide is greater than or equal to 1.5. In a further embodiment, the first oxide layer 120 and the second oxide layer 124 line the sidewalls of the first source / drain terminal 118 and the second source / drain terminal 122 at the interface between the first and second source / drain terminals 118, 122 and the insulating layer 202.

[0032] The first portion of the first and second oxide layers 120, 124 located between the first and second source / drain terminals 118, 122 and the semiconductor layer 104 comprises material derived from the semiconductor layer 104 and the first or second source / drain terminals 118, 122. The second portion of the first and second oxide layers 120, 124 located between the first and second source / drain terminals 118, 122 and the insulating layer 202 comprises material derived from the insulating layer 202 and the first or second source / drain terminals 118, 122.

[0033] In some embodiments, the gate stack 112 is located directly below the semiconductor layer 104 and the first and second source / drain terminals 118, 122. The first and second source / drain terminals 118, 122 are located directly above the semiconductor layer 104 and extend above the topmost surface of the semiconductor layer 104. The topmost surface of the first source / drain terminal 118 is flush with the topmost surface of the second source / drain terminal 122, and the outer sidewall of the first source / drain terminal 118 faces the outer sidewall of the second source / drain terminal 122.

[0034] like Figure 2B As shown in the three-dimensional view 200b, in some embodiments, the insulating layer 202 has a first length 204 measured in a first direction 206, the first length 204 being between the first source / drain terminal 118 and the second source / drain terminal 122. In some embodiments, the first length 204 is approximately between 25 nm and 150 nm, between 50 nm and 200 nm, between 25 nm and 200 nm, or similar ranges. In some embodiments, the first and second source / drain terminals 118, 122 have a first width 208 measured in a second direction 210 perpendicular to the first direction 206. In some embodiments, the first width 208 is approximately between 30 nm and 150 nm, between 60 nm and 200 nm, between 30 nm and 200 nm, or similar ranges. The first and second source / drain terminals 118, 122 are separated from the gate stack 112 in a third direction 212 perpendicular to the first direction 206 and the second direction 210.

[0035] In some embodiments, the oxygen vacancy concentrations in the first and second source / drain regions 108, 110 are substantially uniform across the thicknesses of the first and second source / drain regions 108, 110 as measured on a third direction 212 (e.g., the average oxygen vacancy concentration variation is within 10%). In other embodiments, the oxygen vacancy concentrations in the first and second source / drain regions 108, 110 exhibit a gradient variation, with a higher oxygen vacancy concentration at the interface between the first and second oxide layers 120, 124 and the semiconductor layer 104, and a lower oxygen vacancy concentration at the interface between the gate stack 112 and the semiconductor layer 104.

[0036] In some embodiments, an intermediate region 214 surrounds the first and second source / drain regions 108, 110. The intermediate region 214 extends into the channel 106 and has an average oxygen vacancy concentration between the oxygen vacancy concentrations of the first and second source / drain regions 108, 110 and the oxygen vacancy concentration of the channel 106. In some embodiments, the oxygen vacancy concentration in the intermediate region 214 exhibits a gradient between the oxygen vacancy concentrations of the first and second source / drain regions 108, 110 and the oxygen vacancy concentration of the channel 106.

[0037] In some embodiments, oxygen-vacancy regions 216 surround the sidewalls of the first and second oxide layers 120, 124 in the outer region of the insulating layer 202. The oxygen-vacancy regions 216 have a higher oxygen-vacancy concentration than the inner region of the insulating layer 202. In some embodiments, the oxygen-vacancy concentration exhibits a gradient distribution between the highest oxygen-vacancy concentration near the interface between the first and second oxide layers 120, 124 and the lower oxygen-vacancy concentration at the edge of the oxygen-vacancy region furthest from this interface.

[0038] Figure 3A and Figure 3B Cross-sectional view 300a and three-dimensional view 300b of some embodiments of a transistor are shown. The transistor includes a semiconductor layer with varying concentrations of oxygen vacancies and a gate stack extending from between the inner sidewalls of a first source / drain terminal to a second source / drain terminal.

[0039] like Figure 3A As shown in cross-sectional view 300a, in some embodiments, a first source / drain terminal 118 extends directly below a second source / drain terminal 122. A gate terminal 114 extends through an opening in the second source / drain terminal 122 and extends between the first source / drain terminal 118 and the second source / drain terminal 122. A semiconductor layer 104 also extends through an opening in the second source / drain terminal 122, such that the first source / drain region 108 is located directly below the bottom surface of the gate terminal 114. A second source / drain region 110 surrounds the gate terminal 114 in a continuous ring and extends above the upper surface of the second source / drain terminal 122. A channel 106 extends in a continuous ring between the first source / drain region 108 and the second source / drain region 110. An insulating layer 202 is flush with the channel 106, and an oxygen vacancy region 216 liner the upper and lower surfaces of the insulating layer 202. In some embodiments, the intermediate region 214 extends in the semiconductor layer 104 between the first and second source / drain regions 108, 110 and the channel 106. A gate dielectric layer 116 surrounds the bottom surface of the gate terminal 114 and extends from below to above the second source / drain terminal 122. A first oxide layer 120 covers the top surface of the first source / drain terminal 118, while a second oxide layer 124 covers the top surface, bottom surface, and inner sidewalls of the second source / drain terminal 122.

[0040] like Figure 3BAs shown in the three-dimensional view 300b, in some embodiments, the gate terminal 114 has a circular cross-section in a plane aligned with the first direction 206 and the second direction 210. In other embodiments, the gate terminal may have a square cross-section, a rectangular cross-section, a hexagonal cross-section, etc. The gate terminal 114 passes through the second source / drain terminal 122 along a third direction 212. In some embodiments, the gate terminal 114 has an upper portion extending above and covering the upper surface of the gate dielectric layer 116, and a lower portion extending below the upper surface of the gate dielectric layer 116. In some embodiments, the upper portion of the gate terminal 114 has a diameter 302, which is approximately between 30 nanometers and 80 nanometers, approximately between 50 nanometers and 100 nanometers, approximately between 30 nanometers and 100 nanometers, etc.

[0041] Figure 4A and Figure 4B Cross-sectional view 400a and three-dimensional view 400b of some embodiments of a transistor are shown. The transistor includes a semiconductor layer with varying concentrations of oxygen vacancies, and a gate stack extending around the outer walls of the first source / drain terminals and the second source / drain terminals.

[0042] like Figure 4AAs shown in the cross-sectional view, in some embodiments, semiconductor layer 104 and first source / drain terminals 118 cover the upper surface of second insulating layer 402. In some embodiments, second insulating layer 402 comprises the same material as insulating layer 202. Semiconductor layer 104 extends from the lowermost surface of first source / drain terminal 118 over the uppermost surface of second source / drain terminal 122. Semiconductor layer 104 extends along a third direction 212 and covers the first and second source / drain terminals 118, 122, and surrounds the outer walls of the first and second source / drain terminals 118, 122 in a first direction 206. Insulating layer 202 extends along a third direction 212 between the first source / drain terminal 118 and the second source / drain terminal 122, and channel 106 liner the outer walls of insulating layer 202. First source / drain region 108 liner the outer walls of first source / drain terminal 118 along the first direction 206. The second source / drain region 110 liner the outer wall and upper surface of the second source / drain terminal 122. In some embodiments, the first and second oxide layers 120, 124 completely surround the first and second source / drain terminals 118, 122, respectively. The gate terminal 114 extends over and surrounds the outer wall of the semiconductor layer 104, while the gate dielectric layer 116 extends over and surrounds the outer wall of the semiconductor layer 104, wherein the outer wall of the semiconductor layer 104 is located between the semiconductor layer 104 and the gate terminal 114. The oxygen vacancy region 216 liner the upper and lower surfaces of the insulating layer 202 and extends into the second insulating layer 402 below the first source / drain terminal 118. In some embodiments, the intermediate region 214 extends between the channel 106 and the first and second source / drain regions 108, 110.

[0043] like Figure 4B As shown in the three-dimensional view 400b, in some embodiments, the transistor has a length 406 between approximately 50 nanometers and 120 nanometers, between approximately 80 nanometers and 150 nanometers, between approximately 50 nanometers and 150 nanometers, or similar dimensions. In some embodiments, the first source / drain terminal 118 and the first oxide layer 120 have a combined width 404 between approximately 20 nanometers and 80 nanometers, between approximately 40 nanometers and 100 nanometers, between approximately 20 nanometers and 100 nanometers, or similar dimensions. In some embodiments, the gate terminal 114 and the gate dielectric layer 116 extend over the first direction 206, the second direction 210, and the third direction 212 and beyond the outer wall of the first oxide layer 120.

[0044] Figure 5 Figure 500 shows the current density of a transistor using metal terminals with low oxide formation energy compared to a transistor using metal terminals with higher oxide formation energy.

[0045] Figure 500 shows the current density versus voltage relationship of two transistors; the first transistor has first and second source / drain terminals as described in this disclosure (see Figure 500). Figure 1 (118, 122), the second transistor has third and fourth source / drain terminals made of titanium nitride (TiN). Except for the materials of the source / drain terminals and as described below, the first and second transistors are substantially the same.

[0046] First and second source / drain terminals (see Figure 1 The materials (118, 122) have lower oxide formation energies than titanium nitride (e.g., lower Gibbs free energy per mole of O2 for the formation of metal oxides), resulting in the use of first and second oxide layers formed by first annealing (see [reference]). Figure 1 The thickness of the oxide layers (120, 124) is greater than the thickness of the third and fourth oxide layers of the second transistor formed using the same annealing as the first annealing. In some embodiments, the thickness of the third and fourth oxide layers after annealing is approximately 1.4 nanometers, while the thickness of the first and second oxide layers after the first annealing (see [reference]). Figure 1 The thickness of the 120 and 124 oxide layers is approximately 3.7 nanometers. In other embodiments, the third and fourth oxide layers have different thicknesses, while the first and second oxide layers (see [reference]) have different thicknesses. Figure 1 The thickness of (120, 124) is approximately 200% to 300% of the thickness of the third or fourth oxide layer. During the first annealing, the first and second oxide layers (see...) are... Figure 1 The increased growth rate (120, 124) indicates that more oxygen is fixed in the first and second oxide layers, resulting in the first and second source / drain regions (see [reference]). Figure 1 The 108 and 110 transistors have higher oxygen vacancy concentrations than the third and fourth source / drain regions of the second transistor.

[0047] Line 502 represents the input current density of the first transistor. Line 504 represents the output current density of the first transistor. Line 506 represents the input current density of the second transistor. Line 508 represents the output current density of the second transistor. As shown in Figure 500, the input and output current densities of the first transistor exceed those of the second transistor. In some embodiments, when in the "on" state, the current density difference between the first and second transistors is greater than an order of magnitude when the gate voltage is less than 1 volt. The first transistor is arranged in first and second oxide layers (see Figure 500). Figure 1The increased oxygen vacancy concentration (120, 124) reduces the contact resistance within the first transistor, thereby increasing the current density. It is noteworthy that substantially similar techniques (e.g., utilizing a conductive material with low oxidation energy in the contact, followed by annealing to form an oxide layer to increase the oxygen vacancy concentration in the semiconductor layer near the oxide layer) can be applied to the formation of Schottky diodes, gate-all-around (GAA) devices, or other integrated devices utilizing metal-oxide-semiconductor materials and metal terminals to reduce contact resistance and increase the current density of these devices.

[0048] Figures 6-13 A series of cross-sectional views 600-1300 illustrate some embodiments of a method for forming a transistor, the transistor including a semiconductor layer with varying concentrations of oxygen vacancies, a gate stack located below the semiconductor layer, and first and second source / drain terminals located above the semiconductor layer. Although Figures 6-13 The actions are described as a series of actions, but it should be understood that these actions are not limited, as the order of these actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted in whole or in part.

[0049] like Figure 6 As shown in cross-sectional view 600, a gate terminal 114 is formed on a substrate 102. In some embodiments, the gate terminal 114 may be a conductive material or include conductive materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or similar materials. In some embodiments, the gate terminal 114 is formed on and coupled to an interconnect structure formed in a back-end process (BEOL). The gate terminal 114 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or similar methods.

[0050] like Figure 7 As shown in the cross-sectional view 700, a gate dielectric layer 116 is formed on the gate terminal 114. In some embodiments, the gate dielectric layer 116 is an insulating material or includes insulating materials, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), or similar materials. The gate terminal 114 is formed using one or more of PVD, ALD, CVD, or similar methods. In some embodiments, the thickness of the gate dielectric layer 116 is between about 2 nanometers and 8 nanometers, between about 5 nanometers and 10 nanometers, between about 2 nanometers and 10 nanometers, or similar ranges.

[0051] like Figure 8As shown in cross-sectional view 800, a semiconductor layer 104 is formed on the gate dielectric layer 116. In some embodiments, the semiconductor layer 104 is an oxide semiconductor material or includes oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium oxide (In2O3), indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), nickel oxide (NiO), copper oxide (Cu2O), or similar materials. In some embodiments, the semiconductor layer 104 is an n-type metal oxide semiconductor material. In other embodiments, the semiconductor layer 104 is a p-type metal oxide semiconductor material. In some embodiments, the thickness of the semiconductor layer 104 is between approximately 10 nanometers and 50 nanometers, between approximately 20 nanometers and 80 nanometers, between approximately 10 nanometers and 100 nanometers, or similar ranges. The semiconductor layer 104 is formed using one or more of PVD, ALD, CVD, or similar methods.

[0052] like Figure 9 As shown in cross-sectional view 900, an insulating layer 202 is formed on the semiconductor layer 104. In some embodiments, the insulating layer 202 is an insulating material or includes an insulating material, such as silicon dioxide (SiO2) or a similar material. The oxygen-to-silicon ratio of the silicon dioxide material in the insulating layer 202 is 1.5 or higher. In some embodiments, the thickness of the insulating layer 202 is between approximately 10 nanometers and 40 nanometers, between approximately 20 nanometers and 50 nanometers, between approximately 10 nanometers and 50 nanometers, or similar ranges. The semiconductor layer 104 is formed using one or more of PVD, ALD, CVD, or similar methods.

[0053] like Figure 10 As shown in the cross-sectional view 1000, a first mask layer 1004 is formed on the insulating layer 202. In some embodiments, the first mask layer 1004 is a photoresist or includes photoresist and is patterned using photolithography. The first mask layer 1004 is formed using one or more of PVD, ALD, CVD, spin coating, immersion coating, or similar methods. After the first mask layer 1004 is formed and patterned, a first etching 1002 is performed on the insulating layer 202. In some embodiments, the first etching 1002 is an anisotropic dry etching process. The first etching 1002 causes an opening 1006 to be formed in the insulating layer 202, which corresponds to the first and second source / drain terminals to be formed subsequently (see...). Figure 2A Positions 118 and 122). Then remove the first mask layer 1004.

[0054] like Figure 11As shown in the cross-sectional view 1100, a conformal metal layer 1102 is formed over the insulating layer 202. In some embodiments, the conformal metal layer 1102 is a conductive material or includes conductive materials such as tantalum nitride (TaN), tantalum (Ta), titanium (Ti), ruthenium (Ru), combinations of the foregoing, or similar materials. The conformal metal layer 1102 can also be any conductive metal with a low oxide formation energy (e.g., a formation Gibbs free energy of less than -400 kJ / mol per mole of oxygen), wherein the oxide formed using the conductive metal has a low bulk resistivity (e.g., a bulk resistivity less than about 0.5 kΩ-μm). A bulk resistivity higher than 0.5 kΩ-μm would result in an oxide to be formed subsequently (see...). Figure 13 The resistor unnecessarily reduces the current density of the component and degrades the overall performance of the transistor.

[0055] like Figure 12 As shown in the cross-sectional view 1200, the conformal metal layer above the upper surface of the insulating layer 202 is removed (see...). Figure 11 A portion of 1102) is such that the first source / drain terminal 118 and the second source / drain terminal 122 remain on the semiconductor layer 104. The conformal metal layer is removed using a planarization process (e.g., chemical mechanical planarization). (See [reference]) Figure 11 This part of 1102). The first source / drain terminal 118 and the second source / drain terminal 122 are separated by an insulating layer 202.

[0056] like Figure 13 As shown in cross-sectional view 1300, annealing is performed such that first and second oxide layers 120, 124 are formed along the lower surfaces and outer walls of first and second source / drain terminals 118, 122. In some embodiments, the annealing includes heating the structure to a temperature between 250 and 300 degrees Celsius in a nitrogen atmosphere. In some embodiments, the duration of the annealing is between approximately 1 minute and 60 minutes, approximately 5 minutes and 50 minutes, approximately 3 minutes and 70 minutes, or another similar range. The first and second oxide layers 120, 124 respectively comprise materials from the first and second source / drain terminals 118, 122, semiconductor layer 104, and insulating layer 202. That is, the first oxide layer 120 comprises materials from the first source / drain terminal 118 and semiconductor layer 104, while the second oxide layer 124 comprises materials from the second source / drain terminal 122 and semiconductor layer 104.

[0057] In some embodiments, the thicknesses of the first and second oxide layers 120, 124 are between approximately 3 nanometers and 5 nanometers, between approximately 2.5 nanometers and 4 nanometers, between approximately 3 nanometers and 6 nanometers, or in another similar range. The thicknesses of the first and second oxide layers 120, 124 correspond to the amount of oxygen isolated from the semiconductor layer 104. Therefore, thicknesses below the provided range indicate a lower amount of oxygen removed from the semiconductor layer 104, resulting in the transistor maintaining a higher contact resistance.

[0058] The first and second oxide layers 120, 124 comprise a combination of conductive metal and oxygen from the first and second source / drain terminals 118, 122. For example, the first and second oxide layers 120, 124 may be or comprise one or more of the following: tantalum oxynitride, tantalum oxide (Ta2O5), titanium oxide, ruthenium oxide (RuO2), combinations thereof, or a material with low bulk resistivity (e.g., less than 0.5 kΩ-μm) formed from a conductive metal having low oxide formation energy (e.g., a Gibbs free energy of formation per mole of oxygen below -400 kJ / mol). Oxygen is attracted from the semiconductor layer 104 into the first and second oxide layers 120, 124. In some embodiments, the oxygen content of the first and second oxide layers 120, 124 varies along their thicknesses. For example, the oxygen content of the first oxide layer 120 has a gradient between a first edge and a second edge, wherein the first edge is closer to the insulating layer 202, and the second edge is closer to the first source / drain terminal 118. Furthermore, the oxygen content of the second oxide layer 124 has a gradient change between the first edge and the second edge, wherein the first edge is closer to the semiconductor layer 104, while the second edge is closer to the second source / drain terminal 122.

[0059] Due to the formation of the first and second oxide layers 120, 124, the annealing further results in the first and second source / drain regions 108, 110 having a higher oxygen vacancy concentration than the channel 106. In some embodiments, the oxygen vacancy concentration in the first and second source / drain regions 108, 110 is greater than 50%, while the oxygen vacancy concentration in the channel 106 is less than 40%. The increased oxygen vacancy concentration in the first and second source / drain regions 108, 110 leads to a decrease in the contact resistance between the first and second source / drain regions 108, 110 and the first and second oxide layers 120, 124. The annealing also results in the formation of oxygen vacancy regions 216 in the insulating layer 202 lining the outer walls of the first and second oxide layers 120, 124.

[0060] Figures 14-20A series of cross-sectional views 1400-2000 illustrate some embodiments of a method for forming a transistor, the transistor including a semiconductor layer with varying concentrations of oxygen vacancies, and a gate stack extending from between the inner sidewalls of a first source / drain terminal to a second source / drain terminal.

[0061] like Figure 14 As shown in cross-sectional view 1400, a first source / drain terminal 118 and a second source / drain terminal 122 are formed on a substrate 102. An insulating layer 202 is formed between the first source / drain terminal 118 and the second source / drain terminal 122. The first source / drain terminal 118, the insulating layer 202, and the second source / drain terminal 122 are each formed using PVD, ALD, CVD, or one or more similar methods.

[0062] like Figure 15 As shown in the cross-sectional view 1500, a second mask layer 1504 is formed on the second source / drain terminal 122. In some embodiments, the second mask layer 1504 is or includes photoresist and is patterned using photolithography. The second mask layer 1504 is formed using PVD, ALD, CVD, spin coating, immersion coating, or one or more similar processes. After the second mask layer 1504 is formed and patterned, a second etching 1502 is performed on the second source / drain terminal 122 and the insulating layer 202. In some embodiments, the second etching 1502 is an anisotropic dry etching process. The second etching 1502 causes an opening 1506 to extend through the second source / drain terminal 122 and the insulating layer 202 and expose the first source / drain terminal 118. The second mask layer 1504 is then removed. In some embodiments, the opening 1506 is circular and has a diameter 1508 of approximately 30 to 80 nanometers, approximately 50 to 100 nanometers, approximately 30 to 100 nanometers, or similar at its widest point. In other embodiments, the opening 1506 is square, hexagonal, or another shape, with a width of approximately 30 to 80 nanometers, approximately 50 to 100 nanometers, approximately 30 to 100 nanometers, or similar at its widest point.

[0063] like Figure 16As shown in cross-sectional view 1600, a semiconductor layer 104 is formed over the second source / drain terminal 122. The semiconductor layer 104 has a liner opening 1506 that covers the inner sidewalls of the second source / drain terminal 122 and the insulating layer 202. In some embodiments, the semiconductor layer 104 is formed using PVD, ALD, CVD, or one or more similar methods. In some embodiments, the semiconductor layer 104 is or includes an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium oxide (In2O3), indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), nickel oxide (NiO), copper oxide (Cu2O), or similar materials.

[0064] like Figure 17 As shown in cross-sectional view 1700, a gate dielectric layer 116 is formed over semiconductor layer 104. Gate dielectric layer 116 has a liner opening 1506 that covers the inner sidewalls and lowest upper surface of semiconductor layer 104. In some embodiments, gate dielectric layer 116 is formed using PVD, ALD, CVD, or one or more similar methods.

[0065] like Figure 18 As shown in the cross-sectional view 1800, a second conformal metal layer 1802 is formed over the gate dielectric layer 116. The second conformal metal layer 1802 fills the opening 1506 and covers the inner sidewall and the lowest upper surface of the gate dielectric layer 116. In some embodiments, the second conformal metal layer 1802 is formed using PVD, ALD, CVD, or one or more similar methods.

[0066] like Figure 19 As shown in the cross-sectional view 1900, in the second conformal metal layer (see...) Figure 19 A third mask layer 1904 is formed on the second conformal metal layer (see 1802). In some embodiments, the third mask layer 1904 is or includes photoresist and is patterned using photolithography. The third mask layer 1904 is formed using PVD, ALD, CVD, spin coating, immersion coating, or one or more similar processes. After forming and patterning the third mask layer 1904, the second conformal metal layer (see 1802) is then applied. Figure 19 The third etching 1902 is performed (1802). In some embodiments, the third etching 1902 is an anisotropic dry etching process. The third etching 1902 causes a portion of the second conformal metal layer (see 1802) to be etched. Figure 19 The 1802 layer is removed, leaving the gate terminal 114 on the substrate 102. Then the third mask layer 1904 is removed.

[0067] like Figure 20As shown in cross-sectional view 2000, annealing is performed such that first and second oxide layers 120, 124 are formed along the surfaces and sidewalls of first and second source / drain terminals 118, 122. In some embodiments, the annealing includes heating the structure to a temperature between 250 and 300 degrees Celsius in a nitrogen atmosphere. In some embodiments, the duration of annealing is between approximately 1 minute and 60 minutes, approximately 5 minutes and 50 minutes, approximately 3 minutes and 70 minutes, or another similar range. The first and second oxide layers 120, 124 respectively comprise material from the first and second source / drain terminals 118, 122, semiconductor layer 104, and / or insulating layer 202. That is, the first oxide layer 120 comprises material from the first source / drain terminal 118 and insulating layer 202, while the second oxide layer 124 comprises material from the second source / drain terminal 122 and semiconductor layer 104.

[0068] In some embodiments, the thicknesses of the first and second oxide layers 120, 124 are between approximately 3 nanometers and 5 nanometers, between approximately 2.5 nanometers and 4 nanometers, between approximately 3 nanometers and 6 nanometers, or in another similar range. The thicknesses of the first and second oxide layers 120, 124 correspond to the amount of oxygen isolated from the semiconductor layer 104. Therefore, thicknesses below the provided range indicate a lower amount of oxygen removed from the semiconductor layer 104, resulting in the transistor maintaining a higher contact resistance.

[0069] The first and second oxide layers 120, 124 comprise a combination of conductive metal and oxygen from the first and second source / drain terminals 118, 122. For example, the first and second oxide layers 120, 124 may be or comprise one or more of the following: tantalum oxynitride, tantalum oxide (Ta2O5), titanium oxide, ruthenium oxide (RuO2), combinations thereof, or a material with low bulk resistivity (e.g., less than 0.5 kΩ-μm) formed from a conductive metal having low oxide formation energy (e.g., a Gibbs free energy of formation per mole of oxygen below -400 kJ / mol). Oxygen is attracted from the semiconductor layer 104 into the first and second oxide layers 120, 124. In some embodiments, the oxygen content of the first and second oxide layers 120, 124 varies along the thickness of the first and second oxide layers 120, 124. For example, the oxygen content of the first oxide layer 120 has a gradient change between a first edge and a second edge, wherein the first edge is closer to the insulating layer 202 and the second edge is closer to the first source / drain terminal 118. Furthermore, the oxygen content of the second oxide layer 124 has a gradient change between the first edge and the second edge, wherein the first edge is closer to the semiconductor layer 104 and the second edge is closer to the second source / drain terminal 122.

[0070] Due to the formation of the first and second oxide layers 120, 124, the annealing further results in the first and second source / drain regions 108, 110 having a higher oxygen vacancy concentration than the channel 106. In some embodiments, the oxygen vacancy concentration in the first and second source / drain regions 108, 110 is greater than 50%, while the oxygen vacancy concentration in the channel 106 is less than 40%. The increased oxygen vacancy concentration in the first and second source / drain regions 108, 110 leads to a decrease in the contact resistance between the first and second source / drain regions 108, 110 and the first and second oxide layers 120, 124. The annealing also results in the formation of oxygen vacancy regions 216 in the insulating layer 202 lining the outer walls of the first and second oxide layers 120, 124.

[0071] Figures 21-26 A series of cross-sectional views 2100-2600 show some embodiments of a method for forming a transistor, the transistor including a semiconductor layer with varying concentrations of oxygen vacancies, and a gate stack extending around the outer walls of the first source / drain terminals and the second source / drain terminals.

[0072] like Figure 21 As shown in cross-sectional view 2100, a first metal layer 2102 and a second metal layer 2104 are formed on a substrate 102 and a second insulating layer 402. An insulating layer 202 is formed between the first metal layer 2102 and the second metal layer 2104. The first metal layer 2102, the insulating layer 202, and the second metal layer 2104 are each formed using one or more of PVD, ALD, CVD, or similar methods.

[0073] like Figure 22 As shown in the cross-sectional view 2200, in the second metal layer (see...) Figure 21 A fourth mask layer 2204 is formed on the second metal layer (see 2104). In some embodiments, the fourth mask layer 2204 is or includes photoresist and is patterned using photolithography. The fourth mask layer 2204 is formed using one or more of PVD, ALD, CVD, spin coating, immersion coating, or similar methods. After the fourth mask layer 2204 is formed and patterned, the second metal layer (see 2104) is then... Figure 21 2104), insulating layer 202 and first metal layer (see 2104), insulating layer 202 and first metal layer (see Figure 21 (2102) Performs a fourth etching 2202. In some embodiments, the fourth etching 2202 is an anisotropic dry etching process. The fourth etching 2202 causes the second metal layer (see 2102) to undergo a fourth etching 2202. Figure 21 2104), insulating layer 202 and first metal layer (see 2104), insulating layer 202 and first metal layer (see Figure 21 Part of 2102 is removed, exposing the second insulating layer 402 and defining the first and second source / drain terminals 118, 122. Then the fourth mask layer 2204 is removed.

[0074] like Figure 23 As shown in cross-sectional view 2300, a semiconductor layer 104 is formed over the second insulating layer 402. The semiconductor layer 104 liner the outer walls of the second source / drain terminal 122, the insulating layer 202, and the first source / drain terminal 118. In some embodiments, the semiconductor layer 104 is formed using one or more of PVD, ALD, CVD, or similar methods. In some embodiments, the semiconductor layer 104 is or includes an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium oxide (In2O3), indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), nickel oxide (NiO), copper oxide (Cu2O), or similar materials.

[0075] like Figure 24 As shown in cross-sectional view 2400, a gate dielectric layer 116 is formed over a semiconductor layer 104. The gate dielectric layer 116 clads the outer sidewalls and uppermost surface of the semiconductor layer 104. In some embodiments, the gate dielectric layer 116 is formed using one or more of PVD, ALD, CVD, or similar methods. The semiconductor layer 104 separates the gate dielectric layer 116 from the second insulating layer 402.

[0076] like Figure 25 As shown in cross-sectional view 2500, a gate terminal 114 is formed on the gate dielectric layer 116. The gate terminal 114 liner the outer sidewalls and uppermost surface of the gate dielectric layer 116 and extends along the outer sidewalls of the first source / drain terminal 118 and the second source / drain terminal 122. In some embodiments, the second conformal metal layer 1802 is formed using one or more of PVD, ALD, CVD, or similar methods.

[0077] like Figure 26 As shown in cross-sectional view 2600, annealing is performed such that first and second oxide layers 120, 124 surround first and second source / drain terminals 118, 122. In some embodiments, the annealing includes heating the structure to a temperature between 250 and 300 degrees Celsius in a nitrogen atmosphere. In some embodiments, the duration of annealing is between approximately 1 minute and 60 minutes, approximately 5 minutes and 50 minutes, approximately 3 minutes and 70 minutes, or another similar range. The first and second oxide layers 120, 124 respectively comprise materials from the first and second source / drain terminals 118, 122, semiconductor layer 104, and insulating layer 202. That is, the first oxide layer 120 comprises materials from the first source / drain terminal 118 and semiconductor layer 104, while the second oxide layer 124 comprises materials from the second source / drain terminal 122 and semiconductor layer 104.

[0078] In some embodiments, the thicknesses of the first and second oxide layers 120, 124 are approximately between 3 nanometers and 5 nanometers, approximately 2.5 nanometers and 4 nanometers, approximately 3 nanometers and 6 nanometers, or in another similar range. The thicknesses of the first and second oxide layers 120, 124 correspond to the amount of oxygen isolated from the semiconductor layer 104. Therefore, thicknesses below the provided range indicate a lower amount of oxygen removed from the semiconductor layer 104, resulting in the transistor maintaining a higher contact resistance.

[0079] The first and second oxide layers 120, 124 comprise a combination of conductive metal and oxygen in the first and second source / drain terminals 118, 122. For example, the first and second oxide layers 120, 124 are or comprise one or more of the following: tantalum oxynitride, tantalum oxide (Ta2O5), titanium oxide, ruthenium oxide (RuO2), tungsten oxide (WO2), combinations of the foregoing, or a material with low bulk resistivity (e.g., less than 0.5 kΩ-μm) formed from a conductive metal having low oxide formation energy (e.g., a Gibbs free energy of formation per mole of oxygen below -400 kJ / mol). Oxygen is attracted from the semiconductor layer 104 into the first and second oxide layers 120, 124. In some embodiments, the oxygen content of the first and second oxide layers 120, 124 varies along the thickness of the first and second oxide layers 120, 124. For example, the oxygen content of the first oxide layer 120 has a gradient change between a first edge and a second edge, wherein the first edge is closer to the insulating layer 202 and the second edge is closer to the first source / drain terminal 118. Furthermore, the oxygen content of the second oxide layer 124 has a gradient change between the first edge and the second edge, wherein the first edge is closer to the semiconductor layer 104 and the second edge is closer to the second source / drain terminal 122.

[0080] Due to the formation of the first and second oxide layers 120, 124, the annealing further results in the first and second source / drain regions 108, 110 having a higher oxygen vacancy concentration than the channel 106. In some embodiments, the oxygen vacancy concentration in the first and second source / drain regions 108, 110 is greater than 50%, while the oxygen vacancy concentration in the channel 106 is less than 40%. The increased oxygen vacancy concentration in the first and second source / drain regions 108, 110 leads to a decrease in the contact resistance between the first and second source / drain regions 108, 110 and the first and second oxide layers 120, 124. The annealing also results in the formation of oxygen vacancy regions 216 in the insulating layer 202 lining the outer walls of the first and second oxide layers 120, 124.

[0081] Figure 27A flowchart 2700 illustrates some embodiments of a method for forming a transistor, the transistor comprising a semiconductor layer having varying concentrations of oxygen vacancies, a gate stack below the semiconductor layer, and first and second source / drain terminals above the semiconductor layer. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the order of the shown actions or events. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, while other actions or events not shown may be included.

[0082] In step 2702, a gate terminal and a gate dielectric layer are formed on the substrate. An exemplary diagram of this step can be found in... Figures 6-7 Found it.

[0083] In step 2704, a semiconductor layer is formed on the gate dielectric layer. This semiconductor layer includes a first source / drain region, a second source / drain region, and a semiconductor channel located between the first source / drain region and the second source / drain region. An exemplary diagram of this step can be found in... Figure 8 Found it.

[0084] In step 2706, an insulating layer is formed and patterned on the semiconductor layer, and the resulting openings expose the first source / drain region and the second source / drain region of the semiconductor layer. An exemplary diagram of this step can be found in... Figures 9-10 Found it.

[0085] In step 2708, conformal metal layers are formed in the openings above the first and second source / drain regions, respectively. An exemplary diagram of this step can be found in... Figure 11 Found it.

[0086] In step 2710, the conformal metal layer is planarized, and the resulting first and second source / drain terminals are separated by an insulating layer remaining on the semiconductor layer. An exemplary diagram of this step can be found in... Figure 12 Found it.

[0087] In step 2712, annealing is performed to grow a first oxide layer between the first source / drain terminal and the first source / drain region, and a second oxide layer between the second source / drain terminal and the second source / drain region, thereby increasing the oxygen vacancy concentration at the first and second source / drain regions. An exemplary diagram of this step can be found in... Figure 13 Found it.

[0088] Figure 28 A flowchart 2800 illustrates some embodiments of a method for forming a transistor, the transistor comprising a semiconductor layer having varying concentrations of oxygen vacancies, and a gate stack extending from between the inner sidewalls of a first source / drain terminal to a second source / drain terminal. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the order of the shown actions or events. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, while other actions or events not shown may be included.

[0089] In step 2802, a first metal layer, an insulating layer, and a second metal layer are formed on the substrate. An exemplary diagram of this step can be found in... Figure 14 Found it.

[0090] In step 2804, etching is performed to remove a portion of the second metal layer and the insulating layer, forming an opening that exposes the first metal layer. An exemplary diagram of this step can be found in... Figure 15 Found it.

[0091] In step 2806, a semiconductor layer is formed on the second metal layer and within the opening. This semiconductor layer includes a first source / drain region located above the first metal layer, a second source / drain region flush with the second metal layer, and a semiconductor channel located between the first and second source / drain regions. An exemplary diagram of this step can be found in... Figure 16 Found it.

[0092] In step 2808, a gate dielectric layer is formed to cover the upper surface of the semiconductor layer. An exemplary diagram of this step can be found in... Figure 17 Found it.

[0093] In step 2810, a gate terminal is formed on the gate dielectric layer and the opening is filled. An exemplary diagram of this step can be found in... Figure 18 and Figure 19 Found it.

[0094] In step 2812, annealing is performed to grow a first oxide layer between the first source / drain terminal and the first source / drain region, and a second oxide layer between the second source / drain terminal and the second source / drain region, thereby increasing the oxygen vacancy concentration at the first and second source / drain regions. An exemplary diagram of this step can be found in... Figure 20 Found it.

[0095] Figure 29 A flowchart 2900 illustrates some embodiments of a method for forming a transistor, the transistor comprising a semiconductor layer having varying concentrations of oxygen vacancies, and a gate stack extending around the outer walls of a first source / drain terminal and a second source / drain terminal. Although the methods and other methods shown and / or described herein are depicted as a series of actions or events, it should be understood that this disclosure is not limited to the order of the shown actions or events. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, while other actions or events not shown may be included.

[0096] In step 2902, a first metal layer, an insulating layer, and a second metal layer are formed on the second insulating layer and the substrate. An exemplary diagram of this step can be found in... Figure 21 Found it.

[0097] In step 2904, etching is performed to remove a portion of the second metal layer, the insulating layer, and the first metal layer, and to define the first source / drain terminals and the second source / drain terminals. An exemplary diagram of this step can be found in... Figure 22 Found it.

[0098] In step 2906, a semiconductor layer is formed over the first and second source / drain terminals. This semiconductor layer includes a first source / drain region flush with the first source / drain terminal, a second source / drain region flush with the second source / drain terminal, and a semiconductor channel located between the first and second source / drain regions. An exemplary diagram of this step can be found in... Figure 23 Found it.

[0099] In step 2908, a gate dielectric layer is formed to cover the upper surface of the semiconductor layer. An exemplary diagram of this step can be found in... Figure 24 Found it.

[0100] In step 2910, a gate terminal is formed to cover the upper surface of the gate dielectric layer. An exemplary diagram of this step can be found in... Figure 25 Found it.

[0101] In step 2912, annealing is performed to grow a first oxide layer between the first source / drain terminal and the first source / drain region, and a second oxide layer between the second source / drain terminal and the second source / drain region, thereby increasing the oxygen vacancy concentration at the first and second source / drain regions. An exemplary diagram of this step can be found in... Figure 26 Found it.

[0102] Some embodiments relate to an integrated device including: a semiconductor layer including a semiconductor channel; a gate located on the semiconductor channel; a first source / drain region located on a first side of the semiconductor channel; and a second source / drain region located on a second side of the semiconductor channel opposite to the first side; wherein the first source / drain region and the second source / drain region have oxygen vacancies of a first concentration, and the semiconductor channel has oxygen vacancies of a second concentration less than the first concentration of oxygen vacancies.

[0103] In some embodiments, the system further includes: a first source / drain terminal electrically coupled to the first source / drain region; a first oxide layer spaced between the first source / drain terminal and the first source / drain region; a second source / drain terminal electrically coupled to the second source / drain region; and a second oxide layer spaced between the second source / drain terminal and the second source / drain region. In some embodiments, the system further includes: a gate dielectric layer located on a third side of the semiconductor channel, wherein the first source / drain terminal and the second source / drain terminal are located on a fourth side of the semiconductor channel relative to the third side. In some embodiments, the first oxide layer and the second oxide layer extend into the semiconductor layer and have a bulk resistivity of less than 0.5 kΩ-μm. In some embodiments, the first concentration of oxygen vacancies is greater than 50%, and the second concentration of oxygen vacancies is less than 40%. In some embodiments, the first source / drain region extends from between the inner sidewalls of the second source / drain region to the outer sidewall of the gate.

[0104] Other embodiments relate to an integrated device including: a semiconductor layer including a semiconductor channel; a gate located on the semiconductor channel; a first source / drain region located on a first side of the semiconductor channel; a first source / drain terminal electrically coupled to the first source / drain region; a first oxide layer spaced between the first source / drain terminal and the first source / drain region, and including material from the first source / drain terminal and the first source / drain region; a second source / drain region located on a second side of the semiconductor channel opposite to the first side; a second source / drain terminal electrically coupled to the second source / drain region; and a second oxide layer spaced between the second source / drain terminal and the second source / drain region, and including material from the second source / drain terminal and the second source / drain region.

[0105] In some embodiments, a first portion of the semiconductor layer located directly below the first source / drain terminal and a second portion of the semiconductor layer located directly below the second source / drain terminal have oxygen vacancies of a first concentration; wherein the semiconductor channel has oxygen vacancies of a second concentration; and wherein the first concentration is greater than the second concentration. In some embodiments, an insulating layer is further included, extending directly between the first source / drain terminal and the second source / drain terminal; wherein a first oxide layer spaces the insulating layer from the first source / drain terminal; and wherein a second oxide layer spaces the insulating layer from the second source / drain terminal. In some embodiments, an outer region of the insulating layer has oxygen vacancies of a third concentration, and an inner region of the insulating layer has oxygen vacancies of a fourth concentration, the fourth concentration being smaller than the third concentration. In some embodiments, the semiconductor layer includes an inner sidewall surrounding and flush with the first source / drain terminal and the second source / drain terminal, wherein the first source / drain terminal is located directly above the second source / drain terminal. In some embodiments, the semiconductor layer extends from above the first source / drain region to the upper surface of the second oxide layer, and wherein the first source / drain terminal has an inner sidewall that surrounds the semiconductor channel and the first source / drain region to form a continuous ring.

[0106] However, other embodiments relate to a method of forming an integrated device, including: forming a first metal layer on a substrate; forming a semiconductor layer over the first metal layer, including a first source / drain region, a second source / drain region, and a semiconductor channel located between the first source / drain region and the second source / drain region; forming a second metal layer over the semiconductor layer; and performing annealing such that: a first oxide layer is grown at a surface contact of the first metal layer or the second metal layer at a location where the first source / drain region is contacted, the first oxide layer lining the interface between the first source / drain region and the first metal layer or between the first source / drain region and the second metal layer, wherein the first oxide layer includes material from the first source / drain region and material from the first metal layer or the second metal layer; and a second oxide layer is grown at a surface contact of the first metal layer or the second metal layer at a location where the second source / drain region is contacted, the second oxide layer lining the interface between the second source / drain region and the first metal layer or between the second source / drain region and the second metal layer, wherein the second oxide layer includes material from the second source / drain region and material from the first metal layer or the second metal layer.

[0107] In some embodiments, the annealing further results in oxygen vacancies in the first source / drain region and the second source / drain region having a first concentration, wherein the semiconductor channel has a second concentration of oxygen vacancies, the second concentration of oxygen vacancies being less than the first concentration of oxygen vacancies. In some embodiments, the annealing is performed at a temperature of 200 to 350 degrees Celsius and occurs in an environment including nitrogen. In some embodiments, the method further includes: forming a first insulating layer before forming the semiconductor layer; forming a third metal layer before forming the semiconductor layer and after forming the first insulating layer; and etching the third metal layer and the first insulating layer before forming the semiconductor layer to form an opening in the third metal layer and the first insulating layer; wherein the semiconductor layer is formed within the opening. In some embodiments, the method further includes forming a second insulating layer over the semiconductor layer before forming the second metal layer, wherein the second insulating layer spacees the second metal layer from the semiconductor layer. In some embodiments, the etching further etches the first metal layer such that the opening extends to the bottom surface of the first metal layer. In some embodiments, the method further includes: forming a first insulating layer before forming the semiconductor layer; forming a second insulating layer after forming the semiconductor layer; patterning the second insulating layer to cover the semiconductor channel and expose the first source / drain region and the second source / drain region; wherein, after forming the second metal layer, the second metal layer covers the first source / drain region and the second source / drain region; and performing a planarization process to remove a portion of the second metal layer above the upper surface of the second insulating layer, thereby forming a first source / drain terminal and a second source / drain terminal, respectively, over the first source / drain region and the second source / drain region. In some embodiments, the annealing further causes the first oxide layer and the second oxide layer to be formed along the interfaces between the first source / drain terminal and the second insulating layer and between the second source / drain terminal and the second insulating layer.

[0108] It should be understood that in this written description and the following claims, terms such as “first,” “second,” and “third” are merely general identifiers used for ease of description to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of these elements and are not intended to describe corresponding elements in different exemplary embodiments and / or embodiments not shown. For example, “first dielectric layer” described in conjunction with the first figure may not correspond to “first dielectric layer” described in conjunction with another figure, and may not correspond to “first dielectric layer” in embodiments not shown.

[0109] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or to achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this invention, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this invention.

Claims

1. An integrated component, characterized in that, include: Semiconductor layer, including semiconductor channel; The gate is located on the semiconductor channel; The first source / drain region is located on the first side of the semiconductor channel; as well as The second source / drain region is located on the second side of the semiconductor channel relative to the first side; The first source / drain region and the second source / drain region have oxygen vacancies of a first concentration, and the semiconductor channel has oxygen vacancies of a second concentration, wherein the oxygen vacancies of the second concentration are less than the oxygen vacancies of the first concentration.

2. The integrated component according to claim 1, characterized in that, Also includes: The first source / drain terminal is electrically coupled to the first source / drain region; A first oxide layer separates the first source / drain terminal from the first source / drain region; The second source / drain terminal is electrically coupled to the second source / drain region; as well as The second oxide layer separates the second source / drain terminal from the second source / drain region.

3. The integrated component according to claim 2, characterized in that, It also includes: a gate dielectric layer located on a third side of the semiconductor channel, wherein the first source / drain terminal and the second source / drain terminal are located on a fourth side of the semiconductor channel relative to the third side.

4. The integrated component according to claim 1, characterized in that, The oxygen vacancy at the first concentration is greater than 50%, and the oxygen vacancy at the second concentration is less than 40%.

5. The integrated component according to claim 1, characterized in that, The first source / drain region extends from the inner sidewalls of the second source / drain region to the outer sidewall of the gate.

6. An integrated component, comprising: Semiconductor layer, including semiconductor channel; The gate is located on the semiconductor channel; The first source / drain region is located on the first side of the semiconductor channel; The first source / drain terminal is electrically coupled to the first source / drain region; A first oxide layer separates the first source / drain terminal from the first source / drain region and includes material from the first source / drain terminal and the first source / drain region; The second source / drain region is located on the second side of the semiconductor channel relative to the first side; The second source / drain terminal is electrically coupled to the second source / drain region; as well as The second oxide layer separates the second source / drain terminal from the second source / drain region and includes material from the second source / drain terminal and the second source / drain region.

7. The integrated component according to claim 6, characterized in that, The first portion of the semiconductor layer located directly below the first source / drain terminal and the second portion of the semiconductor layer located directly below the second source / drain terminal have oxygen vacancies of a first concentration. The semiconductor channel has a second concentration of oxygen vacancies; and The first concentration is greater than the second concentration.

8. The integrated component according to claim 6, characterized in that, It also includes an insulating layer that extends directly between the first source / drain terminal and the second source / drain terminal; The first oxide layer separates the insulating layer from the first source / drain terminal; and The second oxide layer separates the insulating layer from the second source / drain terminal.

9. The integrated component according to claim 6, characterized in that, The semiconductor layer includes an inner sidewall that surrounds and is flush with the first source / drain terminal and the second source / drain terminal, wherein the first source / drain terminal is located directly above the second source / drain terminal.

10. The integrated element according to claim 6, characterized in that, The semiconductor layer extends from above the first source / drain region to the upper surface of the second oxide layer, and wherein the first source / drain terminal has an inner sidewall that surrounds the semiconductor channel and the first source / drain region to form a continuous ring.

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