Chip packaging structure and electronic device

Abstract

A chip packaging structure and an electronic device, the chip packaging structure comprises: a lead frame comprising a base island functional area; a first insulating adhesive layer arranged above the base island functional area and in contact with the base island functional area; a die bonding insulating adhesive layer arranged above the first insulating adhesive layer and in contact with the first insulating adhesive layer; and a chip arranged above the die bonding insulating adhesive layer and in contact with the die bonding insulating adhesive layer at the bottom. The first insulating adhesive layer separates the die bonding insulating adhesive layer from direct contact with the base island functional area. The above scheme can avoid chip leakage, misdirecting and other situations.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a chip packaging structure and electronic device. Background Technology

[0002] In applications such as solid-state relays and self-generating drivers, ensuring the stability and reliability of chips under specific conditions is crucial.

[0003] In current packaging structures, insulation is typically achieved by relying on the chip's own insulation structure design, combined with the use of insulating adhesive for die bonding, thus insulating the chip from the lead frame.

[0004] However, in some special scenarios, it is necessary to place the chip on the base island functional area with external pins. When using insulating adhesive for die bonding, if the adhesive is too thin or contains air bubbles, complete insulation between the chip and the base island functional area of ​​the lead frame cannot be achieved, which can lead to chip leakage, false continuity, and other issues. Utility Model Content

[0005] The purpose of this utility model embodiment is at least to provide a chip packaging structure that can avoid chip leakage, false connection and other situations.

[0006] In a first aspect, embodiments of the present invention provide a chip packaging structure, comprising: a lead frame including a base island functional region; a first insulating adhesive layer disposed above and in contact with the base island functional region; a die-bonding insulating adhesive layer disposed above and in contact with the first insulating adhesive layer; and a chip disposed above and at the bottom of the die-bonding insulating adhesive layer; wherein the first insulating adhesive layer isolates the die-bonding insulating adhesive layer from direct contact with the base island functional region.

[0007] An additional first insulating layer is provided between the base island functional area and the die-attach insulating layer. This first insulating layer isolates the die-attach insulating layer from direct contact with the base island functional area, achieving insulation between them. This, in turn, achieves complete isolation between the chip and the base island functional area, preventing chip leakage, false continuity, and other issues.

[0008] Optionally, in the vertical direction, the projection area of ​​the first insulating adhesive layer is the first projection area, the projection area of ​​the die-bonding insulating adhesive layer is the second projection area, and the second projection area is located within the first projection area.

[0009] Optionally, in the vertical direction, the projection area of ​​the chip is a third projection area, and the third projection area is located within the second projection area.

[0010] Optionally, the first projection area has an adjacent and perpendicular first side and a second side, the length of the first side being no greater than 2.5 mm and the length of the second side being no greater than 2.5 mm.

[0011] Optionally, the thickness of the first insulating adhesive layer is 0.05 mm to 0.5 mm.

[0012] Optionally, the material of the first insulating adhesive layer is different from the material of the die-bonding insulating adhesive layer.

[0013] Optionally, the material of the first insulating adhesive layer includes polyimide.

[0014] Optionally, the first insulating adhesive layer is a solid polyimide adhesive, and the first insulating adhesive layer is attached to the base island functional area.

[0015] Optionally, the chip includes any one of the following: a solid-state relay chip, a self-generating driver chip, or a self-driven MOSFET driver chip.

[0016] Secondly, embodiments of the present invention also provide an electronic device, including a packaging structure for the chip described above. Attached Figure Description

[0017] Figure 1 This is a top view of a chip packaging structure according to an embodiment of the present utility model;

[0018] Figure 2 This is a cross-sectional schematic diagram of the packaging structure of a chip according to an embodiment of this utility model;

[0019] Figure 3 This is a schematic diagram of a projection area in one embodiment of the present invention;

[0020] Figure 4 This is a cross-sectional schematic diagram of an existing chip packaging structure. Detailed Implementation

[0021] As described in the background section, currently, in chip packaging structures, die-bonding insulating adhesive is placed between the chip and the lead frame to insulate the chip from the lead frame.

[0022] like Figure 4 The figure shows a cross-sectional schematic diagram of an existing chip packaging structure. Figure 4 In the present invention, the existing chip packaging structure includes a chip 13, a die-bonding insulating layer 12 and a lead frame 11 stacked in sequence.

[0023] However, if the die-bonding insulating adhesive layer 12 is too thin, or if there are air bubbles in the die-bonding insulating adhesive layer 12, it will cause the chip 13 to be unable to achieve complete insulation with the base island functional area of ​​the lead frame 11, which will lead to leakage, false connection and other situations in the chip 11.

[0024] In this embodiment of the invention, a first insulating adhesive layer is additionally provided between the base island functional region and the die-bonding insulating adhesive layer. This first insulating adhesive layer isolates the die-bonding insulating adhesive layer from direct contact with the base island functional region, achieving insulation isolation between the two regions. This, in turn, achieves complete isolation between the chip and the base island functional region, preventing chip leakage, false continuity, and other issues.

[0025] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0026] This utility model embodiment provides a chip packaging structure.

[0027] Reference Figure 1 A top view of a chip packaging structure according to an embodiment of this utility model is provided. (Refer to...) Figure 2 A cross-sectional schematic diagram of the packaging structure of a chip according to an embodiment of the present invention is provided.

[0028] The following combination Figure 1 and Figure 2 Please provide an explanation.

[0029] In this embodiment of the invention, the chip packaging structure may include: a lead frame 1, a first insulating layer 2, a die-bonding insulating layer 3, and a chip 4, wherein:

[0030] The lead frame 1 may include a base island functional area;

[0031] The first insulating adhesive layer 2 can be disposed above the base island functional area and in contact with the base island functional area;

[0032] The die-bonding insulating adhesive layer 3 can be disposed above the first insulating adhesive layer 2 and in contact with the first insulating adhesive layer 2;

[0033] Chip 4 can be disposed above die-bonding insulating layer 3, and the bottom of chip 4 is in contact with die-bonding insulating layer 3.

[0034] In practical implementation, the lead frame serves as the chip carrier for integrated circuits. It uses bonding materials (such as gold, aluminum, or copper wires) to achieve electrical connections between the internal circuit leads of the chip and external leads, forming an electrical circuit. The lead frame acts as a bridge connecting the chip to external wires.

[0035] In practical applications, the base island functional area can be the region in the lead frame 1 that has external pins. Different lead frames may have different sizes, shapes, etc., of their corresponding base island functional areas.

[0036] In a specific implementation, the bottom of chip 4 can refer to the side of chip 4 that has external interfaces (such as pins, pads, pads, etc.).

[0037] In practical implementation, the aforementioned chip 4 can be a solid-state relay chip, a self-generating driver chip, a self-driven MOSFET driver chip, or other chips with high insulation requirements. Chip 4 can also be other types of chips or chips that perform other functions.

[0038] Combination Figure 1 and Figure 2 As can be seen, in this embodiment of the present invention, in the vertical direction, the lead frame 1, the first insulating layer 2, the die-bonding insulating layer 3, and the chip 4 are stacked sequentially from bottom to top. The chip 4 is contacted and disposed on the die-bonding insulating layer 3, the die-bonding insulating layer 3 is disposed on the first insulating layer 2, and the first insulating layer 2 is disposed on the base island functional area of ​​the lead frame 1.

[0039] In this embodiment of the invention, the first insulating adhesive layer 2 can isolate the die-bonding insulating adhesive layer 3 from the base island functional area to avoid direct contact between the die-bonding insulating adhesive layer 3 and the base island functional area, thereby ensuring the effectiveness of insulation.

[0040] In this embodiment of the invention, in the vertical direction, the projection area of ​​the first insulating adhesive layer 2 is the first projection area, the projection area of ​​the die-bonding insulating adhesive layer 3 is the second projection area, and the projection area of ​​the chip 4 is the third projection area. The aforementioned vertical direction can be the vertical direction towards the lead frame 1.

[0041] In practice, the area of ​​the first projection area can be larger than the area of ​​the second projection area, and the area of ​​the second projection area can be larger than the area of ​​the third projection area.

[0042] In other words, the area of ​​chip 4 can be smaller than the area of ​​die-bonding insulating layer 3, and the area of ​​die-bonding insulating layer 3 can be smaller than the area of ​​first insulating layer 2.

[0043] Specifically, such as Figure 3 The diagram shows a projection area in one embodiment of the present invention. Figure 3 In the projection, the third projection region is located within the second projection region, and the second projection region is located within the first projection region.

[0044] Therefore, the bottom of chip 4 can make complete contact with die-bonding insulating layer 3, and die-bonding insulating layer 3 can make complete contact with first insulating layer 2.

[0045] In some embodiments, the first projection area can be rectangular, such as... Figure 3 The square shown is an example. In other embodiments, the first projection area can be a circle, an ellipse, or other shapes. The second projection area can also be a rectangle, a circle, or other shapes. This invention does not limit the specific shapes of the first and second projection areas.

[0046] In a specific implementation, the first projection area may have an adjacent first side and a second side, with the first side perpendicular to the second side. The lengths of the first side and the second side are related to the size of chip 4. The larger the size of chip 4, the larger the dimensions of the first and second sides need to be; conversely, the smaller the size of chip 4, the smaller the dimensions of the first and second sides can be.

[0047] In some embodiments, in the first projection area, the length of the first side may not exceed 2.5 millimeters (mm), and the length of the second side may not exceed 2.5 millimeters. That is, the first projection area may be an area with an area not exceeding 2.5 mm × 2.5 mm.

[0048] In this embodiment of the invention, the thickness of the first insulating adhesive layer 2 can be set based on the actual application scenario and application requirements. The minimum thickness of the first insulating adhesive layer 2 is preferably sufficient to isolate the die-bonding insulating adhesive layer 3 from direct contact with the base island functional area. Furthermore, the maximum thickness of the first insulating adhesive layer 2 also needs to be less than a set value to reduce the overall thickness of the chip 4's packaging architecture.

[0049] In specific implementation, the thickness of the first insulating adhesive layer 2 can be between 0.05 mm and 0.5 mm. Specifically, a thickness value between 0.05 mm and 0.5 mm can be selected as the thickness of the first insulating adhesive layer 2.

[0050] In some embodiments, the thickness of the first insulating adhesive layer 2 is 0.1 mm. In other embodiments, the thickness of the first insulating adhesive layer 2 is 0.15 mm.

[0051] In this embodiment of the invention, the material of the first insulating adhesive layer 2 is different from that of the die-bonding insulating adhesive layer 3. In other words, the first insulating adhesive layer 2 and the die-bonding insulating adhesive layer 3 are made of different insulating adhesive materials.

[0052] In specific implementations, the die-bonding insulating adhesive layer 3 is made of die-bonding adhesive and is used to fix the chip 4 or other electronic components onto the lead frame 1. In some embodiments, the die-bonding adhesive is an insulating die-bonding adhesive, and the material of the insulating die-bonding adhesive layer 3 can be epoxy resin-based die-bonding adhesive, etc.

[0053] In specific implementations, the first insulating adhesive layer 2 can be made of polyimide (PI adhesive). The first insulating adhesive layer 2 can be made of liquid polyimide adhesive or solid polyimide adhesive.

[0054] In some embodiments, polyimide adhesive is applied to the base island functional area by dot coating to form a first insulating adhesive layer 2.

[0055] In other embodiments, the first insulating layer 2 is a solid polyimide tape. The polyimide tape can be attached to the base island functional area by adhesive bonding. The die-bonding insulating layer 3 can be bonded to the first insulating layer 2.

[0056] In specific implementations, other types of insulating adhesives can also be used for the first insulating layer to achieve complete insulation isolation between the die-bonding insulating layer 3 and the base island functional region. In this embodiment of the present invention, polyimide is used as the first insulating adhesive layer for illustration.

[0057] The production process of the chip packaging structure provided in the above embodiments of this utility model will be described below.

[0058] Step 1) For the lead frame, first define the base island functional area on the lead frame, and then determine the area on the base island functional area to attach the polyimide tape.

[0059] Step 2), attach solid polyimide tape to the base island functional area.

[0060] In practice, the area of ​​the base island functional area is larger than the area of ​​the polyimide tape.

[0061] Specifically, based on the area of ​​the base island functional area, a polyimide tape of appropriate size can be selected and applied to the base island functional area by means of adhesion.

[0062] Step 3): After the polyimide tape is applied, apply die-bonding insulating adhesive in dots over the polyimide tape to form a die-bonding insulating adhesive layer.

[0063] Step 4): After the die-bonding insulating layer is formed, place the chip on top of the die-bonding insulating layer, and then bake and cure the lead frame with the chip placed on it.

[0064] Step 5), after baking and curing, the above-mentioned chip packaging structure can be obtained.

[0065] In this embodiment of the invention, "A is disposed on B" can mean that A is disposed above B and in contact with B. For example, "the chip is disposed on the die-bonding insulating layer" means that the chip is disposed above the die-bonding insulating layer and in contact with the die-bonding insulating layer.

[0066] In summary, in this embodiment of the invention, a first insulating layer is additionally provided between the base island functional region and the die-bonding insulating layer. This first insulating layer isolates the die-bonding insulating layer from direct contact with the base island functional region, achieving insulation between them. This, in turn, achieves complete isolation between the chip and the base island functional region, preventing chip leakage, mis-conduction, and other issues. Furthermore, it increases the safety margin for the chip packaging structure design.

[0067] This utility model embodiment also provides an electronic device, including the chip packaging structure provided in any of the above embodiments.

[0068] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip packaging structure, characterized in that, include: Lead frame, including base island functional area; A first insulating adhesive layer is disposed above and in contact with the functional area of ​​the base island; A die-bonded insulating adhesive layer disposed above and in contact with the first insulating adhesive layer; A chip disposed above the die-bonding insulating layer and whose bottom is in contact with the die-bonding insulating layer; The first insulating adhesive layer isolates the die-bonding insulating adhesive layer from direct contact with the base island functional area.

2. The chip packaging structure as described in claim 1, characterized in that, In the vertical direction, the projection area of ​​the first insulating adhesive layer is the first projection area, the projection area of ​​the die-bonding insulating adhesive layer is the second projection area, and the second projection area is located within the first projection area.

3. The chip packaging structure as described in claim 2, characterized in that, In the vertical direction, the projection area of ​​the chip is a third projection area, and the third projection area is located within the second projection area.

4. The chip packaging structure as described in claim 2, characterized in that, The first projection area has an adjacent and perpendicular first side and a second side, the length of the first side being no greater than 2.5 mm and the length of the second side being no greater than 2.5 mm.

5. The chip packaging structure as described in claim 1, characterized in that, The thickness of the first insulating adhesive layer is 0.05 mm to 0.5 mm.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that, The material of the first insulating adhesive layer is different from that of the die-bonding insulating adhesive layer.

7. The chip packaging structure as described in claim 6, characterized in that, The first insulating adhesive layer is a solid polyimide adhesive, and the first insulating adhesive layer is attached to the base island functional area.

8. The chip packaging structure as described in claim 1, characterized in that, The chip includes any one of the following: a solid-state relay chip, a self-generating driver chip, or a self-driven MOSFET driver chip.

9. An electronic device, characterized in that, include: The chip packaging structure as described in any one of claims 1 to 8.

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