Intelligent Image Recognition Integrated Circuit Chipset

Abstract

A smart image recognition integrated circuit chipset is a single chipset disposed in an image acquisition device, serving as a replacement for an image acquisition chip, an image front-end processing chip, and a back-end device image recognition chip. The smart image recognition integrated circuit chipset includes: a dynamic random access memory (DRAM) wafer layer; and a logic wafer layer disposed on the DRAM wafer layer. The logic wafer layer includes a redistribution layer at the bottom and a logic circuit layer above the redistribution layer. The logic circuit layer has a multiply-accumulate operation structure and a static random access memory (SRAM) structure. The DRAM wafer layer and the redistribution layer of the logic wafer layer are interconnected by hybrid bonding.

Description

Technical Field

[0001] This utility model relates to a chipset, and more particularly to an intelligent image recognition integrated circuit chipset disposed in an image acquisition device. Background Technology

[0002] Traditional AI image recognition mainly consists of front-end image acquisition and back-end processing. Front-end image acquisition uses an image acquisition device to obtain image data, which is then transmitted to the back-end processing device for AI processing to complete the AI ​​recognition of the image. For example, a complementary metal-oxide-semiconductor image sensor (CMOS Image Sensor, CIS) in the front-end image acquisition device converts light signals into electrical signals, which are then processed by an IP camera system-on-chip (IPC SoC) in the front-end image acquisition device. Finally, the processed image signal is transmitted to the AI ​​chip in the back-end processing device for further processing.

[0003] However, such an AI image recognition architecture suffers from several problems: massive image data volume leading to extremely high data transmission bandwidth requirements; long-distance transmission resulting in transmission delays; increased cost of transmission equipment; uneven distribution of data between the front-end and back-end; and excessive image compression at the front-end leading to reduced recognition accuracy at the back-end. Furthermore, traditional AI chips also suffer from issues such as excessive size, high power consumption, high heat generation, and heavy weight. Utility Model Content

[0004] Therefore, based on the above-mentioned technical problems, this utility model provides an intelligent image recognition integrated circuit chipset to solve the technical defects of the prior art.

[0005] The present invention addresses the deficiencies of existing technologies by providing an intelligent image recognition integrated circuit chipset. This chipset is installed in an image acquisition device and serves as a single chipset replacing the image acquisition chip, image front-end processing chip, and back-end image recognition chip of the image acquisition device. Its main feature is that the intelligent image recognition integrated circuit chipset includes: a dynamic random access memory (DRAM) wafer layer; and a logic wafer layer disposed above the DRAM wafer layer. The logic wafer layer includes a redistribution layer at the bottom and a logic circuit layer above the redistribution layer. The logic circuit layer has a multiply-accumulate operation structure and a static random access memory (SRAM) structure. The DRAM wafer layer and the redistribution layer of the logic wafer layer are interconnected through hybrid bonding.

[0006] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is provided with a central processing unit.

[0007] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is further provided with a neural network processing unit.

[0008] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is provided with a graphics processing unit.

[0009] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is provided with an image signal processing unit.

[0010] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is provided with a deep learning acceleration unit.

[0011] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, wherein the logic wafer layer is provided with two or more computing units among a central processing unit, a neural network processing unit, a graphics processing unit, an image signal processing unit, and a deep learning acceleration unit, and each computing unit has its own static random access memory structure.

[0012] In one embodiment of this utility model, an intelligent image recognition integrated circuit chipset is provided, which includes multiple dynamic random access memory wafer layers.

[0013] Through the technical means adopted in this utility model, the intelligent image recognition integrated circuit chipset of this utility model has: a dynamic random access memory wafer layer, on which a logic wafer layer is disposed. The logic wafer layer includes a redistribution layer at the bottom and a logic circuit layer above the redistribution layer. The logic circuit layer has a three-dimensional integrated architecture of a multiply-accumulate operation structure and a static random access memory structure. In this way, a single chipset can realize the functions of an image acquisition chip, an image front-end processing chip, and an image recognition chip for a back-end device. Furthermore, by using hybrid bonding to tightly combine the dynamic random access memory wafer layer and the logic wafer layer, the data transmission bandwidth requirements and latency can be effectively reduced, system costs can be reduced, image compression distortion can be avoided from affecting recognition accuracy, and the problems of traditional artificial intelligence chips such as large size, high power consumption, high heat generation, and high weight can be overcome. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating an intelligent image recognition integrated circuit chipset according to an embodiment of the present invention.

[0015] Figure 2 This is a schematic diagram illustrating an intelligent image recognition integrated circuit chipset according to an embodiment of the present invention.

[0016] Figure 3 This is a schematic diagram illustrating an intelligent image recognition integrated circuit chipset according to another embodiment of the present invention.

[0017] Figure 4 This is a schematic diagram illustrating an intelligent image recognition integrated circuit chipset according to another embodiment of the present invention.

[0018] Figure 5 This is a schematic diagram illustrating an intelligent image recognition integrated circuit chipset according to another embodiment of the present invention.

[0019] Figure Labels

[0020] 100, 200, 300 Intelligent Image Recognition Integrated Circuit Chipsets 10 Dynamic Random Access Memory Wafer Layer 20 logic wafer layers 21 Rerouting layer 22 Logic Circuit Layer 221 Multiplication-Accumulation Operation Structure 222 Static Random Access Memory Structure 23 Central Processing Unit 24 Neural Network Processing Units 25 graphics processing units 26 Image Signal Processing Unit 27 Deep Learning Acceleration Unit B Mixed Bonding Detailed Implementation

[0021] The following is based on Figures 1 to 5 This description illustrates one embodiment of the present invention. This description is not intended to limit the implementation of the present invention, but rather to provide one possible embodiment.

[0022] like Figures 1 to 5 As shown, an intelligent image recognition integrated circuit chipset 100 according to an embodiment of the present invention includes a dynamic random access memory wafer layer 10 and a logic wafer layer 20.

[0023] Specifically, the intelligent image recognition integrated circuit chipset 100 of this utility model is disposed in an image acquisition device and serves as a single chipset that replaces the image acquisition chip, image front-end processing chip and back-end device image recognition chip of the image acquisition device.

[0024] In detail, the dynamic random-access memory (DRAM) is formed in the dynamic random-access memory wafer layer 10 to provide a large amount of storage space to store image data acquired by the image acquisition device or to store the calculation results obtained by the logic wafer layer 20 described later.

[0025] Furthermore, in the intelligent image recognition integrated circuit chipset 100 according to the present invention, the logic wafer layer 20 is disposed on the dynamic random access memory wafer layer 10. The logic wafer layer 20 includes a redistribution layer 21 located at the bottom and a logic circuit layer 22 located on the redistribution layer 21. The logic circuit layer 22 is provided with a multiply-accumulate operation structure 221 and a static random access memory structure 222.

[0026] In detail, the logic wafer layer 20 is used for logic operations, control, data processing, etc.

[0027] The redistribution layer 21 (RDL) of the logic wafer layer 20 is a metal conductor layer formed at the bottom of the logic wafer layer 20. It is used to redistribute the electrodes output from the logic circuit layer 22 to new positions, thereby reorganizing the signals to form a suitable output interface.

[0028] In the logic circuit layer 22 of the logic wafer layer 20, the multiply-accumulate (MAC) operation structure 221 performs MAC operations as a MAC array. Multiplication is performed by the multiplier, addition by the adder, and the results are accumulated by the accumulator, forming the operational core to complete the numerous mathematical operations required for image recognition. Furthermore, the static random-access memory (SRAM) structure 222 of the logic wafer layer 20 reads and writes data, providing the MAC for the MAC operations of the multiply-accumulate (MAC) operation structure 221.

[0029] like Figure 2As shown, in the intelligent image recognition integrated circuit chipset 100 according to this utility model, the dynamic random access memory wafer layer 10 and the redistribution layer 21 of the logic wafer layer 20 are interconnected by hybrid bonding (B). Through hybrid bonding (B), combining both a metal (conductive) and a dielectric material (insulating layer), the dynamic random access memory wafer layer 10 and the logic wafer layer 20 are directly bonded together, enabling them to be interconnected in a small-pitch, high-density, and low-latency manner.

[0030] According to the intelligent image recognition integrated circuit chipset 100 of this utility model, the dynamic random access memory wafer layer 10 is directly connected to the logic wafer layer 20, which is provided with a multiply-accumulate operation structure 221 and a static random access memory structure 222, through hybrid bonding B. This can significantly shorten the data transmission path and solve the problems of traditional bandwidth bottlenecks and high latency.

[0031] In a preferred embodiment of the present invention, the intelligent image recognition integrated circuit chipset 200 of the present invention includes a central processing unit (CPU) 23 on the logic wafer layer 20. However, the present invention is not limited to this; the logic wafer layer 20 may also include a neural network processing unit (NPU), a graphics processing unit (GPU), an image signal processing unit (ISP), or a deep learning acceleration unit (DLA).

[0032] In a preferred embodiment of this invention, the central processing unit 23 is capable of control and general-purpose computation, as well as system scheduling, process control, and post-processing. The neural network processing unit 24 is capable of deep learning model inference, such as object detection, face recognition, and license plate recognition. The graphics processing unit 25 is capable of performing a large number of parallel computations, processing image convolutions, and performing large-scale feature extraction and classification. The image signal processing unit 26 is capable of image front-end signal processing. The deep learning acceleration unit 27 is capable of deep learning model inference.

[0033] As a preferred embodiment of this utility model, such as Figure 3As shown, the intelligent image recognition integrated circuit chip group 200 according to the present invention has two or more computing units among the following: central processing unit 23, neural network processing unit 24, graphics processing unit 25, image signal processing unit 26 and deep learning acceleration unit 27, and each computing unit has its own static random access memory structure 222.

[0034] Of course, this utility model is not limited to this. The intelligent image recognition integrated circuit chipset 200 of this utility model can be equipped with any processing unit on the logic wafer layer 20 according to the usage requirements, such as: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), Vision Processing Unit (VPU), Tensor Processing Unit (TPU), etc.

[0035] As a preferred embodiment of this utility model, such as Figure 4 As shown, the intelligent image recognition integrated circuit chipset 300 according to this invention includes multiple dynamic random access memory wafer layers 10. Therefore, it can improve the data access capacity and memory bandwidth of the intelligent image recognition integrated circuit chipset 100, and reduce latency and power consumption.

[0036] An application example of the intelligent image recognition integrated circuit chipset 100 according to the present invention is shown in Figure 5 .like Figure 5 As shown, the intelligent image recognition integrated circuit chipset 100 according to the present invention includes a dynamic random access memory wafer layer 10 and a logic wafer layer 20. The logic wafer layer 20 is disposed on the dynamic random access memory wafer layer 10, and the logic wafer layer 20 includes a redistribution layer 21 located at the bottom and a logic circuit layer 22 located on the redistribution layer 21. The logic circuit layer 22 is provided with a multiply-accumulate operation structure 221 and a static random access memory structure 222. The dynamic random access memory wafer layer 10 and the redistribution layer 21 of the logic wafer layer 20 are interconnected by hybrid bonding B.

[0037] First, such as Figure 5 As shown to the left of the middle arrow, the image sensor of the image acquisition device (e.g., a complementary metal-oxide-semiconductor image sensor (CMOS Image Sensor, CIS)) converts light signals into electrical signals and then into image data, which is then input into the intelligent image recognition integrated circuit chipset 100.

[0038] Next, the intelligent image recognition integrated circuit chipset 100 stores image data through the dynamic random access memory wafer layer 10, performs basic processing such as noise reduction, image enhancement, and format conversion on the image data through the logic wafer layer 20 (image signal processing unit 26), and then performs core artificial intelligence operations through the multiply-accumulate operation structure 221 and the static random access memory structure 222 of the logic wafer layer 20.

[0039] Then as Figure 5 As shown to the right of the middle arrow, the recognition results and / or image data generated by the logic wafer layer 20 will be output.

[0040] Through the technical means adopted in this utility model, the intelligent image recognition integrated circuit chipset 100 of this utility model has: a dynamic random access memory wafer layer 10, and a logic wafer layer 20 disposed thereon. The logic wafer layer 20 includes a redistribution layer 21 located at the bottom and a logic circuit layer 22 located above the redistribution layer 21. The logic circuit layer 22 is provided with a three-dimensional integrated architecture of a multiply-accumulate operation structure 221 and a static random access memory structure 222. Therefore, a single chipset is realized that combines the functions of an image acquisition chip of an image acquisition device, an image front-end processing chip of an image acquisition device, and an image recognition chip of a back-end device. Furthermore, by using hybrid bonding B to tightly combine the dynamic random access memory wafer layer 10 and the logic wafer layer 20, the data transmission bandwidth requirements and latency can be effectively reduced, system costs can be reduced, image compression distortion can be avoided from affecting recognition accuracy, and the problems of traditional artificial intelligence chips such as excessive size, high power consumption, high heat generation, and high weight can be overcome.

[0041] The above description and explanation are merely illustrative of preferred embodiments of the present utility model. Those skilled in the art can make other modifications based on the protection scope defined above and the above description, but these modifications should still be within the protection scope of the present utility model and in line with its spirit.

Claims

1. A smart image recognition integrated circuit chipset, disposed in an image acquisition device as a single chipset replacing the image acquisition chip, image front-end processing chip, and back-end device image recognition chip of the image acquisition device, characterized in that, The intelligent image recognition integrated circuit chipset includes: Dynamic random access memory wafer layer; and A logic wafer layer is disposed above the dynamic random access memory wafer layer. The logic wafer layer includes a redistribution layer at the bottom and a logic circuit layer above the redistribution layer. The logic circuit layer has a multiply-accumulate operation structure and a static random access memory structure. The dynamic random access memory wafer layer and the redistribution layer of the logic wafer layer are interconnected through hybrid bonding.

2. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer is equipped with a central processing unit.

3. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer also includes a neural network processing unit.

4. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer is equipped with a graphics processing unit.

5. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer is equipped with an image signal processing unit.

6. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer is equipped with a deep learning acceleration unit.

7. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, The logic wafer layer is provided with two or more of the following computing units: a central processing unit, a neural network processing unit, a graphics processing unit, an image signal processing unit, and a deep learning acceleration unit, and each of the computing units has the aforementioned static random access memory structure.

8. The intelligent image recognition integrated circuit chipset according to claim 1, characterized in that, It contains multiple of the aforementioned dynamic random access memory wafer layers.

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