Semiconductor device

Abstract

A trench is formed using a metal-containing mask layer for a trench capacitor structure. The metal-containing mask layer enables etching of layers of a semiconductor device to form a trench in a manner that reduces and / or minimizes rounding at the top of the trench. In particular, the metal-containing mask layer inhibits etching at the corners of the top of the trench because the metal-containing mask layer can be used for multiple etching operations and does not need to be removed between etching operations because of contamination issues. This enables the metal-containing mask layer to be used to form the trench completely, which enables the metal-containing mask layer to protect the top of the trench from rounding.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor device. Background Technology

[0002] A semiconductor device may include one or more capacitor structures in an interconnect layer above the device layer (e.g., a back end of line (BEOL) region or a back-end region). The capacitor structures may perform and / or support one or more functions in the semiconductor device, such as memory (e.g., dynamic random access memory (DRAM)), charge decoupling, analog-to-digital (A / D) conversion, and / or other functions.

[0003] new content

[0004] Some embodiments of this utility model provide a semiconductor device, including: a device layer; one or more integrated circuit devices in the device layer; an interconnect layer on the device layer; and a trench capacitor structure in the interconnect layer, wherein the trench capacitor structure includes: a bottom electrode layer along the sidewalls and bottom surface of a plurality of trenches in the interconnect layer; an insulating layer on the bottom electrode layer; a top electrode layer on the insulating layer; and a metal-containing layer between the plurality of trenches. Attached Figure Description

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be increased or decreased arbitrarily.

[0006] Figure 1A and 1B This is a diagram of the exemplary semiconductor device described in this article.

[0007] Figures 2A-2E This is a diagram illustrating an exemplary embodiment of the semiconductor device described herein.

[0008] Figures 3A-3P This is a diagram illustrating an example implementation of the trench capacitor structure described herein.

[0009] Figure 4 This is a flowchart of an exemplary manufacturing process related to the formation of the semiconductor device described in this article.

[0010] Figure 5 This is a flowchart of an exemplary manufacturing process related to the formation of the semiconductor device described in this article. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second features. The first and second features are arranged such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0013] Capacitor structures can include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the area of ​​the conductive electrode layers, the greater the capacitance. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0014] Increasing the lateral dimensions of capacitor structures directly conflicts with semiconductor design principles in the semiconductor industry, which aim to reduce semiconductor device size to achieve lower power consumption, higher operational performance and efficiency, and / or enable semiconductor devices for increasingly smaller applications. Therefore, in some cases, the size of the capacitor structure can be increased in the vertical direction within the semiconductor device, allowing the capacitor structure to extend through multiple layers. A deep trench capacitor (DTC) is a capacitor structure formed in a deep trench within a semiconductor device, such that the electrode layers and insulating layers extend along and conform to the contour of the deep trench. This allows for an increase in the area of ​​the conductive electrode layers (which increases capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure.

[0015] DTC (Distributed Turbine Control) trenches are typically formed with a high aspect ratio between their depth and width. However, forming high aspect ratio trenches for DTC structures through etching is difficult and can present challenges, such as controlling the trench width (leading to increased critical dimension (CD) width) and the corner rounding at the trench top, as etching occurs at the top of the trench. Among other things, these challenges can lead to increased width and reduced density of DTC structures in semiconductor devices.

[0016] In some embodiments described herein, a metal-containing mask layer is used to form the trenches of the trench capacitor structure (e.g., a DTC structure). The metal-containing mask layer enables the etching of layers of the semiconductor device to form the trench in a manner that reduces and / or minimizes the rounded corners at the top of the trench. Specifically, the metal-containing mask layer suppresses etching at the corners at the top of the trench because it can be used for multiple etching operations and does not need to be removed between etching operations due to contamination issues. This allows the metal-containing mask layer to be used to form the trench completely to the bottom contact, where other types of mask layers may need to be removed.

[0017] In this way, the metal mask layer can protect the top of the trench from the effects of the rounded corners and enhance critical dimension control at the top of the trench, enabling the trench to achieve a high aspect ratio while having minimal or no rounded corners. Smaller rounded corners and a higher aspect ratio allow the trench capacitor structure to be formed smaller (e.g., with a smaller top width or critical dimension) while achieving similar capacitance, and / or allowing for an increase in the capacitance of the trench capacitor structure. Specifically, less rounding reduces the divergence of the MIM layer of the trench capacitor structure at the top of the trench, thereby achieving greater utilization of the area within the trench, which increases the capacitance of the trench capacitor structure.

[0018] Figure 1A and Figure 1BThis is a diagram of the exemplary semiconductor device 100 described herein. The semiconductor device 100 may include a system-on-chip (SoC) device, a logic device such as a central processing unit (CPU) or a graphics processing unit (GPU), a memory component (e.g., a high bandwidth memory (HBM) device), such as an image sensor component (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor component), and / or another type of semiconductor device.

[0019] Figure 1A A cross-sectional view of the semiconductor device 100 is shown. (As shown) Figure 1A As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 disposed in the semiconductor device 100 along the z-direction on the device layer 102. For example, the interconnect layer 104 may be located above the device layer 102. As another example, the interconnect layer 104 may be located below the device layer 102.

[0020] Device layer 102 may also be referred to as the front end of line (FEOL) region of semiconductor device 100. Inline layer 104 may also be referred to as the back end of line (BEOL) region of semiconductor device 100 and may include conductive structures configured to transmit signals and / or provide power distribution throughout semiconductor device 100. In some embodiments, semiconductor device 100 includes inline layers 104 above and below device layer 102. A first inline layer 104 on a first side of device layer 102 may be used for signal propagation throughout semiconductor device 100, and a second inline layer 104 on an opposite second side of device layer 102 may be used for power distribution within semiconductor device 100.

[0021] Device layer 102 includes a substrate 106 of semiconductor device 100. Substrate 106 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of substrate. Substrate 106 may extend in the x and / or y directions of semiconductor device 100 such that the top and bottom surfaces of substrate 106 are approximately orthogonal to the z direction of semiconductor device 100.

[0022] Integrated circuit device 108 may be included in device layer 102 and / or on substrate 106 of semiconductor device 100. Integrated circuit device 108 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices.

[0023] The front-end transistor structure may include multiple source / drain regions, which may correspond to doped regions of substrate 106 and are separated by channel regions in substrate 106. In some embodiments, the source / drain regions are doped with a type-1 dopant (e.g., p-type dopant such as boron (B) and / or gallium (Ga), n-type dopant such as phosphorus (P) and / or arsenic (As)), and the channel regions are doped with a type-2 dopant different from the type-1 dopant. The front-end transistor structure may include a gate structure above and / or around the channel regions. The gate dielectric layer of the front-end transistor structure may be included between the gate structure and the channel regions. The gate structure may include a polysilicon gate, a metal gate (e.g., hafnium oxide (HfO)) having a high dielectric constant (high k) gate dielectric layer. x For example, HfO2) and / or another type of gate structure.

[0024] A dielectric layer 110 is contained on the substrate 106. The dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 110 includes a dielectric material that allows for selective etching or prevents etching of various portions of the substrate 106 and / or the integrated circuit device 108, and / or the integrated circuit device 108 in the electrical isolation layer 102. The dielectric layer 110 includes silicon nitride (Si). x Ny ), oxides (e.g., silicon dioxide (S) i O x The dielectric layer 110 may extend in the semiconductor device 100 along the x-direction and / or y-direction. A contact 112 (e.g., a source / drain contact, a gate contact) may extend through the dielectric layer 110 and between the integrated circuit device 108 and the interconnect layer 104. The contact can electrically connect the integrated circuit device 108 to the interconnect layer 104. The contact 112 may include vias, plugs, and / or another type of elongated conductive structure. The contact 112 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au) and other conductive materials.

[0025] The interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) configured along a direction generally perpendicular to the top surface of the substrate 106 (e.g., the z-direction). The dielectric layers may include ILD layers 114 and ESL layers 116 configured alternately in the z-direction. ILD layers 114 and ESL layers 116 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0026] ILD layers 114 may each comprise a low dielectric constant (low k) oxide material, such as silicon oxide (S). i O x The ILD layer 114 may comprise borosilicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric. In some embodiments, the ILD layer 114 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (CS₂). i O x amorphous fluorinated carbon (aC) x F y), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silica (SiOC) polymers, porous HSQ, porous methylsilsesquioxane (MSQ), porous polyarylene ethers (PAE) and / or porous silica (S i O x )wait.

[0027] ESL 116 may each include silicon nitride (Si) x N y The dielectric material can be silicon carbide (SiC), silicon oxynitride (SiON), or another suitable dielectric material. In some embodiments, ILD layers 114 and ESL 116 comprise different dielectric materials to provide etching selectivity, thereby enabling the formation of various structures in the interconnect layer 104. For example, ILD layers 114 may each comprise a low-k dielectric material such as USG, and ESL 116 may each comprise a low-k dielectric material such as silicon nitride (SiO2). x N y High-k dielectric materials such as silicon carbide (SiC) or other high-k dielectric materials may be used. Additionally and / or alternatively, two or more ESL 116s may comprise different materials. For example, one or more first ESL116s may comprise silicon nitride (SiC). x N y One or more second ESL 116 may include silicon carbide (SiC).

[0028] The interconnect layer 104 includes a plurality of conductive structures arranged in multiple layers. The conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 108 in the device layer 102. The conductive structures provide electrical wiring so that signals and / or power can be provided to and / or from the integrated circuit device 108.

[0029] The conductive layer structure may include a plurality of layers 118a-118d arranged vertically and alternating (e.g., vertically alternating) with a plurality of layers 120a-120c in the z-direction. Each of layers 118a-118d includes a layer or metallization structure 122, and each of layers 120a-120c includes a layer or interconnection structure 124.

[0030] Layers 118a-118d in the metallization structure 122 can be referred to as M-layers. For example, layer 118a or metallization structure 122 (referred to as metal-0 (M0) layer) can be located at the bottom of the interconnect layer 104 and can be coupled to the device layer 102. Specifically, the metallization structure 122 in the M0 layer can be coupled to the contact 112 of the integrated circuit device 108 in the device layer 102 (e.g., a contact layer referred to as the "CO" layer). The metallization structure 122 of layer 118b (referred to as metal-1 layer (M1) layer) can be located above layer 118a or metallization structure 122 in the interconnect layer 104, and the metallization structure 122 of layer 118c (referred to as metal-2 layer (M2) layer) can be located above layer 118b, metallization structure 122, and so on.

[0031] Layer 120a (referred to as via-1 (V0) layer) of inline structure 124 may be included between layer M0 and layer M1 to interconnect layer M0 and layer M1, layer 120b (referred to as via-2 (V1) layer) of inline structure 124 may be included between layer M1 and layer M2 to interconnect layer M1 and layer M2, and so on.

[0032] Metallization structure 122 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Inline structure 124 may include vias, interconnects, and / or combinations of other types of conductive structures. Metallization structure 122 and inline structure 124 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, one or more liner layers are included between inline layer 104 and the dielectric layer of metallization structure 122, and / or between inline layer 104 and the dielectric layer of inline structure 124. One or more pad layers may include barrier pads, adhesive pads, and / or another type of pad. Examples of materials used for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0033] In some embodiments, the topmost conductive structure (e.g., the topmost metallization structure 122, the topmost inline structure 124) may be coupled to a connection structure at the top of the semiconductor device 100. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures. In some embodiments, the topmost layer of the conductive structure (e.g., the topmost layer of the metallization structure 122, the topmost layer of the inline structure 124) may be coupled to a bonding structure, such as bonding pads and / or bonding vias.

[0034] like Figure 1A As further shown, the interconnect layer 104 of the semiconductor device 100 includes a trench capacitor structure 126. The trench capacitor structure 126 may extend through one or more dielectric layers in the interconnect layer 104 and / or may be included in one or more dielectric layers in the interconnect layer 104, such as one or more ILD layers 114 and / or one or more ESL layers 116. In some embodiments, an integrated circuit device 108 is electrically coupled to the trench capacitor structure 126 to form a memory cell (e.g., a dynamic random access memory (DRAM) cell or another type of capacitor-based memory cell) in the semiconductor device 100. In some implementations, the trench capacitor structure 126 is configured to provide charge decoupling for one or more integrated circuit devices 108. In some embodiments, the trench capacitor structure 126 is configured to store charge (e.g., photocurrent) of the integrated circuit device 108 (e.g., a pixel sensor) in the semiconductor device 100. In some implementations, the trench capacitor structure 126 is configured to perform another function in the semiconductor device 100.

[0035] The trench capacitor structure 126 may be electrically and / or physically coupled to a bottom contact 128 at its bottom and electrically and / or physically coupled to a top contact 130 at its top. Alternatively, the trench capacitor structure 126 may be electrically and / or physically coupled to multiple top contacts at its top. The bottom contact 128 and the top contact 130 may each include one or more conductive structures in the inline layer 104, such as one or more metallized structures 122 and / or one or more inline structures 124, etc.

[0036] Figure 1B A detailed cross-sectional view of the trench capacitor structure 126 is shown. (See attached image.) Figure 1B As shown, the trench capacitor structure 126 includes one or more trenches 132 on a bottom contact 128. The bottom contact 128 may be included in an ILD layer 114a in the interconnect layer 104 of the semiconductor device 100. The trenches 132 of the trench capacitor structure 126 may extend through one or more dielectric layers in the interconnect layer 104 of the semiconductor device 100, including through ESL 116a, ILD layer 114a, ESL 116b, ILD layer 114c, ESL 116c and / or ILD layer 114d, among other things. In some embodiments, the trench(s) 132 may have a high aspect ratio, which is the ratio of the depth (or height) of the trench(s) 132 to the lateral width (or critical dimension) of the trench(s). Therefore, the trench capacitor structure 126 may be referred to as a DTC structure. In some embodiments, the aspect ratio of the trench 132 may be approximately 10:1 or greater. In some embodiments, trench 132 may have an aspect ratio ranging from about 20:1 to about 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0037] like Figure 1B As further shown, the trench capacitor structure 126 includes a plurality of conformal layers conforming to the contour of the trench 132. The conformal layers may include an adhesive layer 134, a bottom electrode layer 136 on the adhesive layer 134, and an insulating layer 138 on the bottom electrode layer 136. The adhesive layer 134, the bottom electrode layer 136, and the insulating layer 138 may each conform to the contour of the trench 132 such that the adhesive layer 134, the bottom electrode layer 136, and the insulating layer 138 conform to the sidewalls and bottom surface of the trench 132. The trench capacitor structure 126 also includes a top electrode layer 140 located on the insulating layer 138. In some embodiments, the top electrode layer 140 is a filler layer filling the remaining area of ​​the trench 132. Alternatively, the top electrode layer 140 may also be a conformal layer conforming to the sidewalls and bottom surface of one or more trenches 132, and may also include a dielectric plug layer or a filler layer in the remaining area of ​​one or more trenches 132.

[0038] The adhesive layer 134 may also be referred to as an adhesive layer and may include components to facilitate adhesion of the bottom electrode layer 136 to the dielectric layer (e.g., ILD layers 114b, 114c and 114d, ESL 116a, 116b and 116c) and / or the bottom contact 128. The adhesive layer 134 may include tantalum (Ta), tantalum nitride (TaN) and / or other suitable adhesive materials.

[0039] The bottom electrode layer 136, insulating layer 138, and top electrode layer 140 correspond to the MIM structure of the trench capacitor structure 126. Therefore, the trench capacitor structure 126 can also be referred to as an MIM capacitor structure. The bottom electrode layer 136 (also called capacitor bottom metal (CBM)) and the top electrode layer 140 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive ceramic materials, and / or other types of conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 136 and the top electrode layer 140 include the same material or the same material composition. In some embodiments, the bottom electrode layer 136 and the top electrode layer 140 include different materials or different material compositions.

[0040] The insulating layer 138 may include one or more electrically insulating materials. In some embodiments, the insulating layer 138 includes one or more low-k dielectric materials, such as silicon oxide (SiO2). i O x For example, S i O2). Additionally and / or alternatively, the insulating layer 138 may comprise one or more high-k dielectric materials, such as zirconium oxide (ZrO2). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x N y For example, Si3N4), yttrium oxide (Y) x O y For example, Y2O3), lanthanum oxide (La) x O y For example, La2O3) and / or hafnium oxide (HfO) x For example, HfO2, etc. In some embodiments, insulating layer 138 is a stack of multiple layers containing multiple dielectric layers. For example, insulating layer 138 may include a ZrO2 / Al2O3 / ZrO2 (ZAZ) stack.

[0041] In some embodiments, the trench capacitor structure 126 includes a plurality of trenches 132, and the MIM structure of the trench capacitor structure 126 (e.g., bottom electrode layer 136, insulating layer 138, and top electrode layer 140) can extend along the sidewalls and bottom surface of the plurality of trenches 132, and in the plurality of trenches 132. The trenches 132 can be laterally arranged and spaced apart in the x-direction by a certain distance (in Figure 1B The dimension is indicated as D1. Thus, including multiple trenches 132 in the trench capacitor structure 126 allows the length (and therefore area) of the MIM structure of the trench capacitor structure 126 (e.g., bottom electrode layer 136, insulating layer 138, and top electrode layer 140) to be extended, thereby increasing the capacitance of the trench capacitor structure 126.

[0042] like Figure 1B As further shown, the trench capacitor structure 126 may include one or more capping layers over the trench 132 and over the MIM structure of the trench capacitor structure 126. The one or more capping layers may include an oxide capping layer 142, an oxide nitride capping layer 144, and / or a nitride capping layer 146, etc. The capping layers may provide electrical isolation for the MIM structure of the trench capacitor structure 126, and / or may also serve as a hard mask layer stack for forming the top contact 130. The oxide capping layer 142 may include an oxide-containing dielectric material, such as silicon oxide (SiO2). i O x For example, S i O2), etc. The oxynitride capping layer 144 may include an oxynitride-containing dielectric material, such as silicon oxynitride (SiON). The nitride capping layer 146 may include a nitride-containing dielectric material, such as silicon nitride (SiO2). x N y For example, Si3N4, etc.

[0043] like Figure 1B As further shown, the trench capacitor structure 126 may include one or more sidewall spacers 148 and / or 150 on the sidewalls of the capping layers 142-146 and / or on the sidewalls of the top electrode layer 140 above the trench 132. When the adhesive layer 134, bottom electrode layer 136, insulating layer 138, and / or top electrode layer 140 are etched to define the MIM structure of the trench capacitor structure 126, the combination of the capping layers 142-146 and the sidewall spacers 148 and 150 can be used as a self-aligning mask. The sidewall spacers 148 may include an oxide-containing dielectric material, such as silicon oxide (SiO2). i O x For example, S i O2), etc. The sidewall separator 150 may include a nitride-containing dielectric material, such as silicon nitride (SiO2). x N y For example, Si3N4, etc.

[0044] like Figure 1B As further shown, the trench capacitor structure 126 includes a metal-containing layer 152. The metal-containing layer 152 may include multiple segments laterally adjacent to opposite sides of the trench 132. Thus, segments of the metal-containing layer 152 may be included between laterally adjacent trenches 132 of the trench capacitor structure 126. The adhesive layer 134, the bottom electrode layer 136, the insulating layer 138, and / or the top electrode layer 140 may extend continuously over the metal-containing layer 152 between the trenches 132.

[0045] The metal layer 152 is located at the top of the trench 132 and below a portion of the adhesive layer 134 at the top of the trench 132. A portion of the bottom electrode layer 136, a portion of the insulating layer 138, and a portion of the top electrode layer 140 spanning the space between the trenches 132 may also be located on and / or above the metal layer 152. The adhesive layer 134 electrically isolates the bottom electrode layer 136 from the metal layer 152.

[0046] A metal-containing layer 152 is included in the trench capacitor structure 126 as a mask layer for etching ILD layers 114b, 114c, 114d and ESL layers 116a, 116b, 116c to form trenches 132 of the trench capacitor structure 126. The metal-containing layer 152 can remain in the trench capacitor structure 126 after the trenches 132 are formed because it does not pose a risk of carbon (C), oxygen (O), and / or hydrogen (H) contamination to the trench capacitor structure 126 and / or to other layers and / or structures in the semiconductor device 100, since it undergoes minimal or no breakdown over time (and therefore, minimal or no release of organic contaminants). In this way, retaining the metal-containing layer 152 in the trench capacitor structure 126 reduces the cost, time, and / or complexity of forming the trench capacitor structure 126, because the trench capacitor structure 126 can be formed with fewer processing operations, since the mask layer ashing operation can be omitted for the metal-containing layer 152. Among other examples, combined with Figures 3A-3P , Figure 4 and / or Figure 5 The use of a metal layer 152 as a metal mask layer for forming trench 132 is described.

[0047] like Figure 1BAs further shown, the ends of the metal-containing layer 152 are substantially perpendicularly aligned with the ends of the adhesive layer 134, the bottom electrode layer 136, and the insulating layer 138. This may occur, for example, because the metal-containing layer 152 is etched together with the adhesive layer 134, the bottom electrode layer 136, and the insulating layer 138 in the same etching operation to define the MIM structure of the trench capacitor structure 126. The etching operation may be referred to as a CBM etching operation. The metal-containing layer 152 may be etched in a CBM etching operation to reduce the possibility of electrical short circuits between the metal-containing layer 152 and other structures and / or layers.

[0048] The metal layer 152 may include one or more metals, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), etc. In some embodiments, the metal layer 152 includes a metal nitride material, such as titanium nitride (TiN) and / or tantalum nitride (TaN). In some embodiments, the metal layer 152 includes a metal carbide material, such as tungsten carbide (WC).

[0049] As mentioned above, providing Figure 1A and 1B As an example. Other examples can be found related to... Figure 1A and 1B The descriptions are different.

[0050] Figures 2A-2E This is a diagram illustrating an exemplary embodiment 200 of the semiconductor device 100 described herein. In some embodiments, combined with Figures 2A-2E One or more of the described semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / wafer transport tools and / or another type of semiconductor processing tool.

[0051] Turning Figure 2A A substrate 106 is provided. The substrate 106 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces. The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0052] like Figure 2BAs shown, integrated circuit device 108 can be formed in and / or on substrate 106 in device layer 102 of semiconductor device 100. One or more semiconductor processing tools can be used to form one or more portions of integrated circuit device 108. For example, ion implantation tools can be used to dope one or more regions in substrate 106 with one or more types of dopants to form well regions, implantation regions, and / or other types of doped regions in substrate 106 of integrated circuit device 108. As another example, deposition tools can be used to perform various deposition operations to deposit layers and / or structures of integrated circuit device 108, and / or deposit photoresist layers to etch substrate 106 and / or portions of the deposited layers. As another example, exposure tools can be used to expose photoresist layers to form patterns in the photoresist layers. As another example, development tools can develop patterns in photoresist layers. As another example, etching tools can be used to etch substrate 106 and / or portions of the deposited layers to form integrated circuit device 108. As another example, planarization tools can be used to planarize portions of integrated circuit device 108. As another example, electroplating tools can be used to deposit metal structures and / or layers or integrated circuit devices 108.

[0053] Further as Figure 2B As shown, the deposition tool is used to deposit a dielectric layer 110 over and / or on a substrate 106 and over and / or on an integrated circuit device 108. The deposition tool can be used to deposit the dielectric layer 110 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or another suitable deposition technique. In some embodiments, a planarization tool can be used to perform a planarization operation, such as chemical mechanical planarization (CMP), to planarize the dielectric layer 110 after deposition.

[0054] like Figure 2BAs further shown, contacts 112 of the integrated circuit device 108 can be formed through the dielectric layer 110. Contacts 112 can be formed as recesses in the dielectric layer 110. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 110 to form the recesses. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 110. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer on top of the pattern to form the recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 110 to form the recesses.

[0055] Contact 112 may be formed in a recess. In some embodiments, contact 112 (e.g., a gate contact) is formed on the gate structure of integrated circuit device 108. In some embodiments, contact 112 (e.g., a source / drain contact) is formed on the source / drain region of integrated circuit device 108. Deposition tools may be used to deposit material of contact 112 in the recess using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. Material of contact 112 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and material of contact 112 is deposited on the seed layer. In some embodiments, planarization tools are used to perform a planarization operation (e.g., a CMP operation) to planarize contact 112 after deposition, such that the top of contact 112 is substantially coplanar with the top of dielectric layer 110.

[0056] like Figure 2C As shown, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed over the dielectric layer 110. One or more deposition tools are used to deposit alternating ILD layers 114 and ESL layers 116 in the first portion of the interconnect layer 104 of the semiconductor device 100. In this way, the ILD layers 114 and ESL layers 116 can be configured in the z-direction of the semiconductor device 100. One or more deposition tools can be used to deposit each ILD layer 114 and each ESL layer 116 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, after depositing the ILD layers 114 and / or ESL layers 116, a planarization tool can be used to planarize the ILD layers 114 and / or ESL layers 116.

[0057] like Figure 2C As further shown, various operations can be performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form the metallization structure 122 and thereby form the interconnect structure 124 in the first portion of the interconnect layer 104 of the semiconductor device 100. The bottom contact 128 of the trench capacitor structure 126 can also be formed in the first portion of the interconnect layer 104.

[0058] In some embodiments, the first portion of the inline layer 104 may be formed as multiple layers. For example, ILD layers 114 and ESL 116 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), and recesses may be formed in and / or through ILD layers 114 and ESL 116 (e.g., using one or more deposition tools and / or one or more planarization tools). Layer 118a of the metallization structure 122 (e.g., an MO layer) may be formed in one ILD layer 114 and one ESL 116 or (e.g., using one or more deposition tools and / or one or more planarization tools). Layer 120a of the inline structure 124 (e.g., a VO layer) may be formed in ILD layers 114 and ESL 116. Layers 118b, 118c, 120b, and 120c may be formed in a similar manner.

[0059] One or more deposition tools can be used to deposit the metallized structure 122, the inline structure 124, and / or the bottom contact 128 using PVD, ALD, CVD, electroplating (e.g., electrochemical electroplating) techniques and / or other methods. In some embodiments, a planarization tool can be used to planarize the metallized structure 122, the inline structure 124, and / or the bottom contact 128 after deposition.

[0060] like Figure 2D As shown, the trench capacitor structure 126 can be formed in one or more dielectric layers within the interconnect layer 104. The trench capacitor structure 126 can be formed such that one or more trenches 132 of the trench capacitor structure 126 fall on the bottom contact 128 in the interconnect layer 104. Figures 3A-3P An exemplary fabrication process for forming the trench capacitor structure 126 is shown and described.

[0061] like Figure 2E As shown, a second portion of the interconnect layer 104 of the semiconductor device 100 is formed over the first portion of the interconnect layer 104, including over the trench capacitor structure 126. The second portion of the interconnect layer 104 can be bonded to... Figure 2CThe first portion of the described interconnect layer 104 is formed in a similar manner. The top contact 130 of the trench capacitor structure 126 may be formed in the second portion of the interconnect layer 104.

[0062] As mentioned above, providing Figures 2A-2E As an example. Other examples can be found related to... Figures 2A-2E The descriptions are different.

[0063] Figures 3A-3P This is a diagram of an exemplary embodiment 300 that forms the trench capacitor structure 126 described herein. In some embodiments, combined with Figures 3A-3P One or more of the described semiconductor processing operations can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, wafer / wafer transport tools, and / or another type of semiconductor processing tool. In some embodiments, combined with Figures 3A-3P One or more of the described semiconductor processing operations can be used as a means of forming a bond. Figures 2A-2E The process of manufacturing the described semiconductor device 100 is performed as part of the manufacturing process.

[0064] like Figure 3A As shown, a mask layer can be formed on the ILD layer 114d in the interconnect layer 104 of the semiconductor device 100. For example, a metal-containing layer 152 (e.g., a metal-containing mask layer) can be formed on the ILD layer 114d, and a dielectric mask layer 302 can be formed over the ILD layer 114d on the metal-containing layer 152. The dielectric mask layer 302 may comprise silicon oxynitride (SiON) material and / or other suitable dielectric materials.

[0065] The deposition tools can be used to deposit the material containing the metal layer 152 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, after depositing the metal layer 152, a planarization tool is used to perform a planarization operation (e.g., CMP) to planarize the metal layer 152. The deposition tools can be used to deposit the dielectric mask layer 302 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, after depositing the dielectric mask layer 302, a planarization tool is used to perform a planarization operation (e.g., CMP) to planarize the dielectric mask layer 302.

[0066] The metal layer 152 can be formed to have a thickness ranging from about 400 angstroms to about 600 angstroms. Figure 3A(The reference is to dimension D2). If the thickness of the metal layer 152 is less than about 400 angstroms, the metal layer 152 may be easily etched when forming the trench 132 of the trench capacitor structure 126, resulting in etching down to the underlying ILD layer 114d. A thickness of the metal layer 152 greater than about 600 angstroms may result in reduced control over the width or critical dimension of the trench 132, and may also result in insufficient etching of the metal layer 152 in subsequent CBM etching operations to define the MIM structure of the trench capacitor structure 126. If the thickness of the metal layer 152 is included in the range of about 400 angstroms to about 600 angstroms, sufficient control over the width or critical dimension of the trench(one or more) 132 can be achieved while reducing the likelihood of metal etching. However, other values ​​for the thickness of the metal layer 152, and ranges other than about 400 angstroms to about 600 angstroms, are also within the scope of this disclosure.

[0067] like Figure 3B As shown, a photoresist layer 304 can be formed over the metal layer 152 and the dielectric mask layer 302, and a pattern 306 can be formed in the photoresist layer 304. A deposition tool can be used to form the photoresist layer on the dielectric mask layer 302 (e.g., using spin coating or another suitable deposition technique). In some embodiments, a bottom antireflective coating (BARC) is first deposited on the dielectric mask layer 302, and then the photoresist layer 304 is deposited on the BARC. An exposure tool can be used to expose the photoresist layer 304 to a radiation source to the pattern. A development tool can be used to develop and remove portions of the photoresist layer 304 to expose the pattern 306.

[0068] like Figure 3C As shown, an etching tool can be used to etch the dielectric mask layer 302 and the metal-containing layer 152 based on the pattern 306 in the photoresist layer 304 to transfer the pattern 306 to the dielectric mask layer 302 and the metal-containing layer 152. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0069] In some embodiments, the etching operation includes a gas-based etching operation, wherein pattern 306 is transferred to the metal-containing layer 152 using a chlorine-based etchant. Chlorine-based etchants may include chlorine-based (Cl...) xA gas-based etchant (e.g., Cl2 gas) is used. Compared to the dielectric material of the underlying ILD layer 114d, the chlorine-based gas etchant can achieve a higher etching rate on the metal-containing layer 152. Therefore, gas-based etching operations can be stopped on the ILD layer 114d with minimal etching of the ILD layer 114d.

[0070] like Figure 3D As shown, another etching operation is performed to etch through ILD layers 114b, 114c, 114d and through ESL 116b and ESL 116c to form one or more trenches 132 of the trench capacitor structure 126. The etching operation may include another gas-based etching operation, wherein a different type of gas-based etchant is used compared to the gas-based etchant used to transfer the pattern 306 to the metal-containing layer 152. Therefore, the semiconductor device 100 can be transferred from a first etching tool (where the pattern 306 is transferred to the metal-containing layer 152) to a second etching tool (where ILD layers 114b, 114c, 114d and ESL 116b and 116c are etched using a wafer / wafer transfer tool) to reduce the possibility of cross-contamination between the first and second etching tools. Alternatively, an etching tool with multiple processing chambers (e.g., a cluster tool) can be used, and the semiconductor device 100 can be transferred between the processing chambers of the etching tool to etch using different types of gas-based etchants.

[0071] Gas-based etchants used for etching ILD layers 114b, 114c, 114d and ESL layers 116b, 116c may include fluorine-based gas etchants that exhibit high etching rates to the dielectric materials of ILD layers 114b, 114c, 114d, comparing the etching rates of ESL layers 116b, 116c with those of the metal-containing layer 152. This allows for the etching of ILD layers 114b, 114c, 114d and ESL layers 116b, 116c with minimal etching of the metal-containing layer 152 (and therefore, minimal to no increase in the width or critical dimension at the top of trench 132). Fluorine-based etchants may include fluorinated carbon-based (CF3) etchants. x Gas etchants, such as carbon tetrafluoride (CF4) gas etchant.

[0072] In some embodiments, multiple etching operations (e.g., multiple gas-based etching operations using a fluorine-based etchant) are performed to form one or more trenches 132 of the trench capacitor structure 126. For example, a first etching operation (referred to as a "master etching" operation) may be performed to form trench 132 of ESL 116a. In other words, the etching in the first etching operation stops at ESL 116a, such that ESL 116a remains between the bottom of trench 132 and the underlying bottom contact 128. ESL 116a remains above the bottom contact 128 to prevent the bottom contact 128 from being exposed to oxygen and other contaminants that could otherwise cause oxidation of the bottom contact 128. After the first etching operation, trench 132 may have tapered sidewalls, resulting in the lateral width of trench 132 decreasing from the top to the bottom of trench 132.

[0073] A second etching operation (referred to as an "over-etching" operation) can be performed after the first etching operation to shape the bottom portion of trench(s) 132. Specifically, the second etching operation can be performed to increase the verticality of the sidewalls of trench(s) 132, thereby reducing the taper in the sidewalls of trench(s) 132. During the first and second etching operations, a metal-containing layer 152 remains on the ILD layer 114d to form and shape the trench 132, such that the metal-containing layer 152 protects the ILD layer 114d from etching, which reduces the likelihood of critical dimension widening and the likelihood of rounded corners at the top of the trench 132.

[0074] like Figure 3E As shown, a third etching operation (referred to as a "linear removal" etching operation) is performed to etch the ESL 116a through the bottom of trench(s)132, thereby extending trench(s)132 through the ESL 116a and the underlying bottom contact 128. Therefore, after the third etching operation, the bottom contact 128 is exposed through the trench 132. A second etching tool can be used and a fluorine-based etchant (e.g., fluorinated carbon-based etchant) can be used. x For example, CF4 gas etchant is used to perform the third etching operation.

[0075] During the third etching operation, the metal-containing layer 152 remains on the ILD layer 114d to etch through the ESL 116a, such that the metal-containing layer 152 protects the ILD layer 114d from etching, which reduces the likelihood of critical dimension widening and reduces / or the amount of fillet radius at the top of the trench 132. For example, the top of one or more trenches 132 may have rounded edges, and the angle of the rounded edges of the trench 132 relative to the sidewalls of the trench 132 (in Figure 3EThe angle (indicated as dimension D3) may be between approximately 100 degrees and approximately 110 degrees, while when the trench 132 is formed, without the use of the metal layer 152, the angle may additionally be approximately 130 degrees or greater. However, other values ​​and ranges are also within the scope of this disclosure.

[0076] like Figure 3E Further shown, the metal-containing layer 152 after the formation of trench 132 (in) Figure 3E The thickness (denoted as dimension D4) ranges from about 150 angstroms to about 350 angstroms. In other words, the thickness of the metal-containing layer 152 in the trench capacitor structure 126 is less than the thickness of the metal-containing layer 152 at the time of its formation, because some of the metal-containing layer 152 is consumed during the formation of the trench 132.

[0077] like Figure 3F As shown, the adhesive layer 134 can be deposited on the sidewalls and bottom surface of the trench 132. The bottom surface of the trench 132 corresponds to the top surface of the bottom contact 128, so the adhesive layer 134 can be in physical contact with the top surface of the bottom contact 128. The adhesive layer 134 can also be deposited on the top surface of the metal-containing layer 152 between adjacent trenches 132, such that the adhesive layer 134 can be in physical contact with the top surface of the metal-containing layer 152. In some embodiments, a deposition tool is used to conformally deposit the adhesive layer 134, such that the adhesive layer 134 conforms to the contour of the trench 132. In some embodiments, conformal CVD technology and / or ALD technology are used to deposit the adhesive layer 134.

[0078] like Figure 3G As shown, the bottom electrode layer 136 can be deposited on the adhesive layer 134. Therefore, the bottom electrode layer 136 is deposited on the sidewalls and bottom surface (which corresponds to the top surface of the bottom contact 128) of trench(s) 132. The bottom electrode layer 136 can also be deposited on the top surface of the metal-containing layer 152 between adjacent trenches 132. In some embodiments, a deposition tool is used to conformally deposit the bottom electrode layer 136 such that the bottom electrode layer 136 conforms to the contour of the trench 132. In some embodiments, conformal CVD and / or ALD techniques are used to deposit the bottom electrode layer 136.

[0079] like Figure 3HAs shown, an insulating layer 138 can be deposited on the bottom electrode layer 136. Therefore, the insulating layer 138 is deposited on the sidewalls and bottom surface (which corresponds to the top surface of the bottom contact 128) of trench(s) 132. The insulating layer 138 can also be deposited on the top surface of the metal-containing layer 152 between adjacent trenches 132. In some embodiments, a deposition tool is used to conformally deposit the insulating layer 138 such that the insulating layer 138 conforms to the contour of the trench 132. In some embodiments, conformal CVD and / or ALD techniques are used to deposit the insulating layer 138.

[0080] like Figure 3I As shown, a top electrode layer 140 can be deposited on an insulating layer 138. The top electrode layer 140 can be deposited such that it fills the remaining area of ​​the trench 132. The top electrode layer 140 can also be deposited on the top surface of a metal-containing layer 152 between adjacent trenches 132. In some embodiments, deposition tools are used to conformally deposit the top electrode layer 140 using PVD, CVD, ALD, and / or another suitable deposition technique.

[0081] like Figure 3J As shown, a capping layer is formed over trench 132 of trench capacitor structure 126. For example, among other examples, oxide capping layer 142 may be formed over and / or on top electrode layer 140, oxynitride capping layer 144 may be formed over and / or on oxide capping layer 142, and / or nitride capping layer 146 may be formed over and / or on oxynitride capping layer 144.

[0082] Deposition tools can be used to deposit oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. Oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146 can be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146 after deposition.

[0083] like Figure 3KAs shown, capping layers (e.g., oxide capping layer 142, oxide oxynitride capping layer 144, and / or nitride capping layer 146) can be used to etch and define the top electrode layer 140 of the trench capacitor structure 126. In some embodiments, patterns in the photoresist layer are used to etch the oxide capping layer 142, oxide oxynitride capping layer 144, and / or nitride capping layer 146 to form a hard mask over the top electrode layer 140. In these embodiments, a photoresist layer can be formed on the nitride capping layer 146 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the oxide capping layer 142, oxide oxynitride capping layer 144, and / or nitride capping layer 146 based on the pattern to define the hard mask layer. In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). The top electrode layer 140 can then be etched using an etching tool based on a hard mask layer (e.g., based on a pattern in oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146) to define the top electrode layer 140.

[0084] like Figure 3L As shown, spacer layers 308 and 310 are formed over the capping layers (e.g., oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146). Spacer layers 308 and 310 extend along the ends of the capping layers (e.g., along the ends of oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146) and along the ends of the top electrode layer 140. Furthermore, spacer layers 308 and 310 are formed in the exposed portions of the insulating layer 138.

[0085] Deposition tools can be used to deposit spacer layers 308 and / or 310 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. Spacer layers 308 and / or 310 can be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize spacer layers 308 and / or 310 after deposition.

[0086] like Figure 3MAs shown, spacer layers 308 and 310 are etched together with portions of insulating layer 138, bottom electrode layer 136, adhesive layer 134, and metal-containing layer 152 to define the bottom electrode layer 136 of the MIM structure of trench capacitor structure 126. The etching operation may be referred to as a CBM etching operation. In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or another type of etching operation. The etching of spacer layers 308 and 310 removes portions of spacer layers 308 and 310 from the top of nitride capping layer 146, thereby creating sidewall separators 148 and 150 at the ends of oxide capping layer 142, oxide oxy nitride capping layer 144, nitride capping layer 146, and nitride capping layer 146. Furthermore, the etching of the spacer wall layer 308 and the spacer wall layer 310 results in the sidewall spacer 150 having a circular outer surface.

[0087] Etching agents (e.g., gas-based etchants, plasma-based etchants) can be used to achieve anisotropic etching of spacer layers 308 and 310. Spacer layers 308 and 310 can be etched together with portions of insulating layer 138, bottom electrode layer 136, adhesive layer 134, and metal-containing layer 152. Anisotropic etching is performed primarily in the z-direction of the semiconductor device 100, enabling minimal lateral etching of the bottom electrode layer 136 and insulating layer 138. The etchant used can have different etching rates for the metal-containing layer 152 and the bottom electrode layer 136. For example, the ratio of the etching rate of the bottom electrode layer 136 to the etching rate of the metal-containing layer 152 can be in the range of about 50:1 to about 150:1. If the ratio is too low (meaning the etching rates of the metal layer 152 and the bottom electrode layer 136 are too similar), the metal layer 152 may be etched too quickly, increasing the likelihood of etching into the underlying ILD layer 114d. If the ratio is too high (meaning the etching rate of the bottom electrode layer 136 is much higher than the etching rate of the metal layer 152), the likelihood of residual material in the metal layer 152 remaining exposed increases (which may increase the likelihood of the metal layer 152 causing an electrical short circuit in the semiconductor device 100). If the ratio is in the range of about 50:1 to about 150:1, the likelihood of completely removing the exposed portion of the metal layer 152 with minimal etching into the ILD layer 114d increases. However, other values ​​and ranges of ratios other than about 50:1 to about 150:1 are also within the scope of this disclosure.

[0088] like Figure 3NAs shown, additional material can be formed on the ILD layer 114d to encapsulate the trench capacitor structure 126. Deposition tools can be used to deposit the additional material on the ILD layer 114d using PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique. The additional material on the ILD layer 114d can be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., CMP operation) to planarize the ILD layer 114d after the deposition of the additional material.

[0089] like Figure 3O As shown, the recess 312 can be formed in the ILD layer 114d, passing through the capping layers 142-146, and reaching the top electrode layer 140 of the trench capacitor structure 126. Therefore, the top electrode layer 140 can be exposed through the recess 312.

[0090] In some embodiments, the pattern in the photoresist layer is used to etch the ILD layer 114d, oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146 to form a recess 312. In these embodiments, a deposition tool may be used to form the photoresist layer on the ILD layer 114d. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the ILD layer 114d, oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146 based on the pattern to form the recess 312. In some embodiments, one or more etching operations are performed to etch the ILD layer 114d, oxide capping layer 142, oxynitride capping layer 144, and / or nitride capping layer 146. In some embodiments, one or more etching operations may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remainder of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to pattern-forming recess 312.

[0091] like Figure 3PAs shown, the top contact 130 can be formed in the recess 312. Deposition tools can be used to deposit material for the top contact 130 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The top contact 130 can be deposited in one or more deposition operations. In some embodiments, a first seed layer is deposited, and the top contact 130 is deposited on the seed layer. In some embodiments, after depositing the top contact 130, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the top contact 130.

[0092] As mentioned above, providing Figures 3A-3P As an example. Other examples can be found related to... Figures 3A-3P The descriptions are different.

[0093] Figure 4 This is a flowchart of an exemplary process 400 associated with forming the semiconductor device described herein. In some embodiments, Figure 4 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, annealing tools, wafer / wafer transport tools, and / or another type of semiconductor processing tool.

[0094] like Figure 4 As further shown, process 400 may include forming a pattern in a metal-containing mask layer on a first dielectric layer of the semiconductor device (block 410). For example, one or more semiconductor processing tools may be used to form a pattern (e.g., pattern 306) in a metal-containing mask layer (e.g., metal-containing layer 152) on the first dielectric layer (e.g., ILD layer 114d). 100), as described herein.

[0095] like Figure 4 As further shown, process 400 may include pattern-based formation of trenches (132) through a first dielectric layer and multiple second dielectric layers to a conductive structure (block 420). For example, one or more semiconductor processing tools may be used to form, as described herein, patterns, trenches (e.g., trench 132) to the first dielectric layer and multiple second dielectric layers (e.g., ESL 116a, ILD layer 114b, ESL 116b), connecting ILD layer 114c, ESL 116c to a conductive structure (e.g., bottom contact 128).

[0096] like Figure 4 As further shown, process 400 may include forming a MIM capacitor structure of a semiconductor device in a trench (block 430). For example, one or more semiconductor processing tools may be used to form the MIM capacitor structure of the semiconductor device in the trench (e.g., trench capacitor structure 126), as described herein.

[0097] Process 400 may include other implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0098] In a first embodiment, forming a MIM capacitor structure includes forming a portion of a MIM capacitor structure (e.g., a portion of the adhesive layer 134 of the trench capacitor structure 126, a portion of the bottom electrode layer 136 of the trench capacitor structure 126, a portion of the insulating layer 138 of the trench capacitor structure 126, a top electrode layer 140 on the metal mask layer, or a portion of the trench capacitor structure 126).

[0099] In the second embodiment, patterning in a metal-containing mask layer, alone or in combination with the first embodiment, includes using a chlorine-based etchant (e.g., a Cl-containing etchant). x An etchant, such as a Cl2-containing etchant, is used to etch the metal-containing mask layer to transfer a pattern from the photoresist layer (e.g., photoresist layer 304) to the metal-containing mask layer.

[0100] In the third embodiment, patterning, alone or in combination with one or more of the first and second embodiments, includes using a fluorinated carbon-based etchant (e.g., CF2-containing etchant). x Etching agents, such as CF4-containing etchants.

[0101] In the fourth embodiment, the metal mask layer, alone or in combination with one or more of the first to third embodiments, includes at least one of a metal nitride material (e.g., titanium nitride (TiN) material) or a nitride.

[0102] In the fifth embodiment, forming a metal-containing mask layer, alone or in combination with one or more of the first to fourth embodiments, includes forming the metal-containing mask layer to a thickness (e.g., dimension D2) ranging from about 400 angstroms to about 600 angstroms.

[0103] In the sixth embodiment, the thickness (e.g., dimension D4) of the metal mask layer after the trench is formed, alone or in combination with one or more of the first to fifth embodiments, includes a range of about 150 angstroms to about 350 angstroms.

[0104] although Figure 4 An example block of process 400 is shown, but in some embodiments, process 400 includes... Figure 4 The blocks depicted here are those that are additional, fewer, different, or have different configurations. Alternatively, two or more of the blocks or processes in 400 can be executed in parallel.

[0105] Figure 5 This is a flowchart of an exemplary process 500 related to the formation of the semiconductor device described herein. In some embodiments, Figure 5 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, annealing tools, wafer / wafer transport tools and / or another type of semiconductor processing tool.

[0106] like Figure 5 As shown, process 500 may include forming a metal-containing mask layer on a first dielectric layer of a semiconductor device (block 510). For example, one or more semiconductor processing tools may be used to form a metal-containing mask layer (e.g., metal layer 152) on a first dielectric layer (e.g., ILD layer 114d) of a semiconductor device (e.g., semiconductor device 100).

[0107] like Figure 5 As further shown, process 500 may include forming a pattern in a metal-containing mask layer (block 520). For example, one or more semiconductor processing tools may be used to form a pattern (e.g., pattern 306) in the metal-containing mask layer, as described herein.

[0108] like Figure 5 As further shown, process 500 may include performing one or more first etching operations based on a pattern in a metal-containing mask layer to form trenches through a first dielectric layer and a plurality of second dielectric layers (block 530). For example, one or more semiconductor processing tools may be used to perform one or more first etching operations based on a pattern in a metal-containing mask layer to form trenches (e.g., trench 132) through the first dielectric layer and a plurality of second dielectric layers (e.g., ESL 116a, ILD layer 114b, ESL 116b, ILD layer 114c, ESL 116c), as described herein. In some embodiments, the trench is formed over a conductive structure (e.g., bottom contact 128) in a semiconductor device. In some embodiments, after one or more first etching operations, a third dielectric layer (e.g., ESL 116a) is located between the bottom of the trench and the conductive structure.

[0109] like Figure 5 As further shown, process 500 may include performing a second etching operation to etch through the third dielectric layer, such that the trench extends through the third dielectric layer and reaches the conductive structure (block 540). For example, one or more semiconductor processing tools may be used to perform the second etching operation to etch through the third dielectric layer, such that the trench extends through the third dielectric layer and reaches the conductive structure, as described herein.

[0110] like Figure 5As further shown, process 500 may include forming a DTC structure of a semiconductor device in a trench (block 550). For example, one or more semiconductor processing tools may be used to form a DTC structure of a semiconductor device in a trench (e.g., trench capacitor structure 126), as described herein.

[0111] Process 500 may include other implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0112] In a first embodiment, forming a pattern in a metal-containing mask layer includes etching the metal-containing mask layer with a first etchant to form a pattern, and performing one or more first etching operations includes performing one or more first etching operations using a second etchant, wherein the first etchant and the second etchant are different etchants.

[0113] In the second embodiment, alone or in combination with the first embodiment, the first etchant includes a chlorine-based etchant (e.g., containing Cl). x The first etchant is a Cl2-containing etchant, and the second etchant includes a fluorine-based etchant (e.g., a CF2-containing etchant). x Etching agents, such as CF4-containing etchants.

[0114] In a third embodiment, performing the second etching operation, alone or in combination with one or more of the first and second embodiments, includes performing the second etching operation based on a pattern in a metal-containing mask layer, without removing the metal-containing mask. A masking layer is placed between one or more first etching operations and the second etching operation.

[0115] In the fourth embodiment, forming a DTC structure, alone or in combination with one or more of the first to third embodiments, includes forming a DTC structure such that a layer of the DTC structure is formed on a metal-containing mask layer.

[0116] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 500 includes performing a third etching operation to define a top electrode layer (e.g., top electrode layer 140) of the layer defining the DTC structure, and performing a fourth etching operation to define a bottom electrode layer (e.g., bottom electrode layer 136) of the layer defining the DTC structure, wherein the metal mask layer is etched in the fourth etching operation.

[0117] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the ratio of the etching rate of the metal mask layer to the etching rate of the bottom electrode layer in the fourth etching operation is included in a range of about 50:1 to about 150:1.

[0118] although Figure 5 An example block of process 500 is shown, but in some embodiments, process 500 includes... Figure 5 The blocks depicted in the diagram are those that are additional, fewer, different, or have different configurations compared to other blocks. Alternatively, two or more of the blocks or processes in 500 can be executed in parallel.

[0119] In this manner, a metal-containing mask layer is used to form the trench of a trench capacitor structure. The metal-containing mask layer allows for the etching of the semiconductor device layers to form the trench with reduced and / or minimized corner fillets at the top of the trench. Specifically, the metal-containing mask layer suppresses etching at the corners at the top of the trench because it can be used for multiple etching operations and does not need to be removed between operations due to contamination issues. This allows the metal-containing mask layer to be used to fully form the trench to the bottom contact, protecting the top of the trench from the effects of corner fillets. In this way, using a metal-containing mask layer allows for enhanced critical dimension control at the top of the trench and a higher aspect ratio for the trench, with minimal or no corner fillets.

[0120] As described in more detail above, some embodiments described herein provide a method. This method includes forming a metal-containing mask layer on a first dielectric layer of a semiconductor device. This method includes forming a pattern in the metal-containing mask layer. This method includes forming a conductive structure based on the pattern, trenches to the first dielectric layer, and a plurality of second dielectric layers. This method includes forming a MIM capacitor structure of the semiconductor device in the trenches.

[0121] In an embodiment of this utility model, forming the MIM capacitor structure includes forming a portion of the MIM capacitor structure on the metal mask layer.

[0122] In an embodiment of this invention, forming the pattern in the metal-containing mask layer includes: etching the metal-containing mask layer using a chlorine-based etchant to transfer the pattern from the photoresist layer to the metal-containing mask layer.

[0123] In embodiments of this invention, forming the pattern includes: using fluorocarbon-based (CF) x The etchant etches the first dielectric layer and the plurality of second dielectric layers.

[0124] In embodiments of this invention, the metal-containing mask layer includes at least one of the following: a metal nitride material or a metal carbide material.

[0125] In an embodiment of the present invention, forming the metal-containing mask layer includes forming the metal-containing mask layer to have a thickness ranging from about 400 angstroms to about 600 angstroms.

[0126] In embodiments of this invention, the thickness of the metal mask layer after the trench is formed ranges from about 150 angstroms to about 350 angstroms.

[0127] As described in more detail above, some embodiments described herein provide a method. This method includes forming a metal-containing mask layer on a first dielectric layer of a semiconductor device. This method includes forming a pattern in the metal-containing mask layer. This method includes performing one or more first etching operations based on the pattern in the metal-containing mask layer to form trenches through the first dielectric layer and a plurality of second dielectric layers, wherein the trenches are formed over a conductive structure in the semiconductor device, and wherein, after one or more first etching operations, a third dielectric layer is located at the bottom of the trenches and between the conductive structure. This method includes performing a second etching operation to etch through the third dielectric layer, such that the trenches extend through the third dielectric layer and reach the conductive structure. This method includes forming a DTC structure of the semiconductor device in the trenches.

[0128] In an embodiment of the present invention, forming the pattern in the metal-containing mask layer includes: etching the metal-containing mask layer using a first etchant to form the pattern; wherein performing the one or more first etching operations includes: performing the one or more first etching operations using a second etchant; and wherein the first etchant and the second etchant are different etchants.

[0129] In embodiments of the present invention, the first etchant comprises a chlorine-based etchant; and the second etchant comprises a fluorine-based etchant.

[0130] In an embodiment of the present invention, performing the second etching operation includes: performing the second etching operation based on the pattern in the metal-containing mask layer, and not removing the metal-containing mask layer between the one or more first etching operations and the second etching operation.

[0131] In an embodiment of this utility model, forming the DTC structure includes: forming the DTC structure such that a layer of the DTC structure is formed on the metal-containing mask layer.

[0132] In an embodiment of the present invention, the method further includes: performing a third etching operation to define a top electrode layer of the layer defining the DTC structure; and performing a fourth etching operation to define a bottom electrode layer of the layer defining the DTC structure, wherein the metal mask layer is etched in the fourth etching operation.

[0133] In embodiments of this invention, the ratio of the etching rate of the bottom electrode layer to the etching rate of the metal-containing mask layer in the fourth etching operation is within the range of about 50:1 to about 150:1.

[0134] As described in more detail above, some implementations described herein provide a semiconductor device. This semiconductor device includes a device layer. This semiconductor device includes one or more integrated circuit devices within the device layer. This semiconductor device includes an interconnect layer located above the device layer. This semiconductor device includes a trench capacitor structure within the interconnect layer. The trench capacitor structure includes a bottom electrode layer along the sidewalls and bottom surface of a plurality of trenches in the interconnect layer, an insulating layer on the bottom electrode layer, a top electrode layer on the insulating layer, and a metal-containing layer between the plurality of trenches.

[0135] In embodiments of this invention, the metal-containing layer includes at least one of the following: titanium nitride (TiN) or tungsten carbide (WC).

[0136] In an embodiment of the present invention, the metal-containing layer has a rounded edge between the sidewall of the metal-containing layer and the top of the metal-containing layer; and the angle of the rounded edge relative to the sidewall is in the range of about 100 degrees to about 110 degrees.

[0137] In embodiments of this invention, the bottom electrode layer, the insulating layer, and the top electrode layer extend continuously over the metal-containing layer between the trenches.

[0138] In an embodiment of this utility model, the trench capacitor structure further includes an adhesive layer between the metal layer and the bottom electrode layer.

[0139] In an embodiment of this utility model, the adhesive layer and the top surface of the metal-containing layer are in physical contact with the sidewall of the metal-containing layer.

[0140] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not intended to be limiting. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0141] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Device layer; One or more integrated circuit devices in the device layer; The interconnect layer on the device layer; and The trench capacitor structure in the interconnect layer. The trench capacitor structure includes: Bottom electrode layer along the sidewalls and bottom surface of the multiple trenches in the inline layer; The insulating layer on the bottom electrode layer; The top electrode layer on the insulating layer; and The metal layer between the plurality of trenches.

2. The semiconductor device according to claim 1, wherein The metal-containing layer has a rounded edge between the sidewall and the top of the metal-containing layer; and The angle between the circular edge and the sidewall is in the range of 100 to 110 degrees.

3. The semiconductor device according to claim 1, wherein The bottom electrode layer, the insulating layer, and the top electrode layer extend continuously over the metal-containing layer between the plurality of trenches.

4. The semiconductor device according to claim 1, wherein The trench capacitor structure also includes: The adhesive layer between the metal layer and the bottom electrode layer.

5. The semiconductor device according to claim 4, wherein The adhesive layer is in physical contact with the top surface of the metal-containing layer and the sidewall of the metal-containing layer.

6. The semiconductor device according to claim 4, wherein The adhesive layer is in physical contact with the top surface of the bottom joint.

7. The semiconductor device according to claim 1, wherein The thickness of the metal-containing layer between the plurality of trenches is in the range of 150 angstroms to 350 angstroms.

8. The semiconductor device according to claim 1, wherein The depth-to-width ratio of the trench is 10:1 or greater.

9. The semiconductor device according to claim 1, wherein Including: A top cover layer above the trench and above the trench capacitor structure.

10. The semiconductor device according to claim 1, wherein The ends of the metal layer, the bottom electrode layer, and the insulating layer are generally vertically aligned.

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