Multilayer epitaxial super junction semiconductor structure

Abstract

The utility model relates to a kind of super-junction semiconductor structures of multilayer epitaxy, it includes first conductive type substrate, first conductive type epitaxial layer, second conductive type column and first conductive type attraction area, first conductive type epitaxial layer is set in the front of the first conductive type substrate and is provided with multilayer, second conductive type column is at least provided with two and is set in the first conductive type epitaxial layer, and from the front to back of the first conductive type epitaxial layer extends, first conductive type attraction area, it is set in the second conductive type column, the utility model has the effect that current is attracted close to change the concentration area of current, so that larger electric field shielding area is formed in the first conductive type epitaxial layer between two second conductive type columns, to optimize EAS avalanche, improve the reliability of device.

Description

Technical Field

[0001] This utility model relates to the technical field of power devices, and in particular to a multilayer epitaxial superjunction semiconductor structure. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage, and high-reliability power semiconductor devices. Among them, superjunction devices, as a new type of power device, are widely used in high-voltage and high-power power electronic equipment due to their advantages of low on-resistance and high breakdown voltage.

[0003] Existing superjunction semiconductor structures typically include a substrate and an epitaxial layer. Alternating, charge-balanced P-pillars and N-pillars are formed within the epitaxial layer of the device. When the device is in reverse blocking state, the P-pillars and N-pillars deplete each other, forming a near-ideal lateral electric field distribution. Based on charge balancing technology, high voltage withstand capability is achieved while reducing the on-resistance of the device.

[0004] The current path of the aforementioned super semiconductor structure is usually from the substrate to the epitaxial layer, and then along the P-pillar into the bulk region, and into the source region, and finally to the surface electrode. However, this current path is fixed, and the optimization of EAS avalanche capability is limited. Utility Model Content

[0005] In view of this, the purpose of this utility model is to provide a multilayer epitaxial superjunction semiconductor structure to solve the technical problem of fixed current path trend and limited EAS avalanche capability in the prior art.

[0006] This invention provides a multilayer epitaxial superjunction semiconductor structure, comprising: First conductivity type substrate; The first conductivity type epitaxial layer is disposed on the front side of the first conductivity type substrate and has multiple layers. The second conductive type pillars are provided in at least two and are disposed within the first conductive type epitaxial layer, extending from the front side to the back side of the first conductive type epitaxial layer; The first conductivity type attraction area is located within the second conductivity type column.

[0007] Optionally, each of the second conductive type pillars is provided with at least two first conductive type attraction regions, which are respectively located in adjacent first conductive type epitaxial layers.

[0008] Optionally, multiple first-conductive-type attraction regions within each first-conductive-type column are connected sequentially.

[0009] Optionally, the first conductive type attraction area is located in the middle region of the second conductive type column along the second direction.

[0010] Optionally, the ion concentration of the first conductivity type in the first conductivity type attraction region is higher than the ion concentration of the first conductivity type in the first conductivity type epitaxial layer.

[0011] Optionally, the length of the first conductive type attraction region along the second direction is less than the length of the second conductive type pillar along the second direction.

[0012] Optionally, n conductive epitaxial layers are stacked sequentially from the front side of the first conductive substrate, wherein the thickness of the nth conductive epitaxial layer is not greater than the thickness of the (n-1)th conductive epitaxial layer, and the thickness of the nth conductive epitaxial layer is less than the thickness of the first conductive epitaxial layer.

[0013] Optionally, the first conductivity type epitaxial layer is provided with 7-13 layers.

[0014] Optionally, it also includes: The second conductivity type body region is disposed on the front side of the first conductivity type epitaxial layer and located within the first conductivity type epitaxial layer; A gate structure is disposed between two adjacent pillars of the second conductivity type; The first conductivity type source region is disposed on the front side of the second conductivity type body region and located within the second conductivity type body region; An insulating dielectric layer is disposed on the front side of the second conductive type body region, and a plurality of metal contact through holes corresponding to the second conductive type pillars are formed in the insulating dielectric layer; A front metal layer is disposed on the front side of the insulating dielectric layer and extends into the metal contact via until it fills the metal contact via. A back metal layer is disposed on the back side of the first conductivity type substrate.

[0015] Optionally, the gate structure includes a trench formed on the front side of the first conductivity type epitaxial layer, a gate is disposed in the trench, a gate oxide layer is disposed between the gate and the inner wall of the trench, and one or two gates are disposed.

[0016] The technical solution of this utility model has the following advantages: 1. The multilayer epitaxial superjunction semiconductor structure provided by this utility model can attract current to the first conductivity type attraction region by setting a first conductivity type attraction region in the second conductivity type pillar, thereby changing the current concentration area and forming a large electric field shielding region in the first conductivity type epitaxial layer between the two second conductivity type pillars, thereby optimizing EAS avalanche and improving the reliability of the device.

[0017] 2. The multilayer epitaxial superjunction semiconductor structure provided by this utility model has a first conductivity type attraction region. At this time, the first conductivity type attraction region will also form a PN junction between the second conductivity type pillar, thereby reducing the area of ​​the original second conductivity type pillar depletion layer region and thus improving the voltage withstand capability of the superjunction semiconductor structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the overall structure of the multilayer epitaxial superjunction semiconductor structure in this utility model; Figure 2 This is a schematic diagram of another embodiment of the multilayer epitaxial superjunction semiconductor structure of this utility model.

[0020] Explanation of reference numerals in the attached figures: 1. Substrate of first conductivity type; 2. Epitaxial layer of first conductivity type; 3. Attractor region of first conductivity type; 4. Pillar of second conductivity type; 41. Pillar region of second conductivity type; 5. Gate structure; 51. Trench; 52. Gate; 53. Gate oxide layer; 54. Shielding gate; 6. Body region of second conductivity type; 7. Source region of first conductivity type; 8. Insulating dielectric layer; 9. Front metal layer; 10. Back metal layer; 11. Metal contact via. Detailed Implementation

[0021] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of this utility model. Based on the description of this utility model, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this utility model.

[0022] Unless otherwise explicitly specified and limited, the terms "setup," "installation," and "connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms based on the specific circumstances.

[0023] The terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of description and simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0024] The terms “first,” “second,” “third,” etc., are used merely to distinguish elements with similar properties, not to indicate or imply relative importance or a specific order.

[0025] In the diagram, arrow X points in the first direction, and arrow Y points in the second direction.

[0026] The terms “include,” “comprising,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0027] Example Reference Figure 1 and Figure 2 As shown, this utility model provides a multilayer epitaxial superjunction semiconductor structure, including a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a second conductivity type pillar 4, and a first conductivity type attraction region 3. The first conductivity type substrate 1 is selected as N-type silicon as the substrate. The first conductivity type epitaxial layer 2 is disposed on the front side of the first conductivity type substrate 1 and is stacked in multiple layers. The concentration of first conductivity type ions in the first conductivity type substrate 1 is greater than the concentration of first conductivity type ions in the first conductivity type epitaxial layer 2.

[0028] Each first conductivity type epitaxial layer 2 is grown on the front side of the first conductivity type substrate 1 through an epitaxial process. Multiple first conductivity type epitaxial layers 2 are arranged and epitaxially grown sequentially along the first direction. At least two second conductivity type pillars 4 are provided and disposed within the first conductivity type epitaxial layers 2, extending from the front side to the back side of the first conductivity type epitaxial layers 2. Second conductivity type ions are implanted in a portion of each first conductivity type epitaxial layer 2, thereby forming multiple second conductivity type pillar regions 41. The second conductivity type pillar regions 41 within the multiple first conductivity type epitaxial layers 2 are correspondingly arranged, thereby forming at least two rows of second conductivity type pillar regions 41 along the first direction. Each row of second conductivity type pillar regions 41 is advanced by high temperature, causing each row of second conductivity type pillar regions 41 to diffuse, thereby forming multiple second conductivity type pillars 4.

[0029] The first conductivity type attraction region 3 is disposed within the first conductivity type pillar and located within the second conductivity type pillar region 41. Each second conductivity type pillar 4 is provided with at least one first conductivity type attraction region 3. By providing the first conductivity type attraction region 3 within the second conductivity type pillar region 41, current can be attracted to the first conductivity type attraction region 3, thereby changing the current concentration area. This results in a larger electric field shielding area being formed within the first conductivity type epitaxial layer 2 between the two second conductivity type pillars 4, thereby optimizing EAS avalanche and improving the reliability of the device.

[0030] As one specific implementation method, refer to Figure 1 As shown, each second conductive type column 4 is provided with at least two first conductive type attraction regions 3. In this embodiment, each second conductive type column 4 is provided with two first conductive type attraction regions 3. The two first conductive type attraction regions 3 are respectively located within the second conductive type column regions 41 of two adjacent first conductive type epitaxial layers 2, thereby ensuring that the attraction current of the first conductive type attraction region 3 reaches the best effect, increasing the attraction current, changing the current concentration area, and avoiding excessive attraction current. Furthermore, the two first conductive type attraction regions 3 in each row of second conductive type columns 4 are connected in sequence. After first conductive type ions are injected into the two second conductive type column regions 41 to form the first conductive type attraction region 3, high temperature propulsion is used to diffuse the two first conductive type attraction regions 3, thereby connecting the two first conductive type attraction regions 3.

[0031] In this embodiment, the ion concentration of the first conductivity type in the first conductivity type attraction region 3 is higher than that in the first conductivity type epitaxial layer 2, ensuring its current attraction effect. The length of the first conductivity type attraction region 3 along the second direction is less than the length of the second conductivity type pillar region 41 along the second direction, and there is a certain distance between both sides of the first conductivity type attraction region 3 along the second direction and the first conductivity type epitaxial layer 2, so that both sides of the first conductivity type attraction region 3 along the second direction are located in the second conductivity type pillar region 41, and will not protrude from the second conductivity type pillar region 41 and connect with the first conductivity type epitaxial layer 2. Due to this configuration of the first conductivity type attraction region 3, the first conductivity type attraction region 3 will also form a PN junction with the second conductivity type pillar 4, thereby reducing the area of ​​the depletion layer region at the original second conductivity type pillar 4, and thus improving the voltage withstand capability of the superjunction semiconductor structure.

[0032] Furthermore, the first conductivity type attraction region 3 is located in the middle region of the second conductivity type pillar 4 along the first direction. By placing the first conductivity type attraction region 3 in the middle region close to the superjunction semiconductor structure, it is ensured that it can attract current in the middle region, thereby maximizing the electric field shielding area formed. In one specific implementation, n layers of the first conductivity type epitaxial layer 2 are stacked sequentially from bottom to top starting from the front side of the first conductivity type substrate 1. The thickness of the nth first conductivity type epitaxial layer 2 is not greater than the thickness of the (n-1)th first conductivity type epitaxial layer 2, and the thickness of the nth first conductivity type epitaxial layer 2 is less than the thickness of the first first conductivity type epitaxial layer 2. In this embodiment, the first conductive type epitaxial layer 22 is provided with 7-13 layers. In a further embodiment, the first conductive type epitaxial layer 2 is provided with 10 layers. The two first conductive type attraction regions 3 are respectively provided in the second conductive type pillar regions 41 within the 5th and 6th layers of the first conductive type epitaxial layer 2 from bottom to top. By gradually reducing the thickness of the multiple first conductive type epitaxial layers 2 from bottom to top, the electric field is uniformly distributed, making the electric field more uniformly distributed throughout the entire first conductive type epitaxial layer 2, improving the withstand voltage capability of the device, effectively controlling the electric field gradient of each first conductive type epitaxial layer 2, so that the electric field changes gradually between different layers, avoiding the possible abrupt change in electric field in a single first conductive type epitaxial layer 2, refining the current carrying capacity, and achieving charge balance.

[0033] As one specific implementation method, refer to Figure 1As shown, the superjunction semiconductor structure also includes a second conductivity type body region 6, a first conductivity type source region 7, a gate structure 5, an insulating dielectric layer 8, a front metal layer 9, and a back metal layer 10. The second conductivity type body region 6 is disposed on the front side of the first conductivity type epitaxial layer 2 and located within the first conductivity type epitaxial layer 2. The gate structure 5 is disposed on the front side of the first conductivity type epitaxial layer 2 and is disposed between two adjacent second conductivity type pillars 4.

[0034] Specifically, at least one gate structure 5 is provided, and a gate structure 5 is provided between each of two adjacent second conductivity type pillars 4. The gate structure 5 also extends from the front side of the first conductivity type epitaxial layer 2 with the second conductivity type body region 6 to the back side of the first conductivity type epitaxial layer 2, until it extends from the second conductivity type body region 6 into the first conductivity type epitaxial layer 2 below the second conductivity type body region 6. The gate structure 5 is not limited to being a trench gate, but can also be a planar gate, which can be directly provided on the front side of the first conductivity type epitaxial layer 2. The first conductivity type source region 7 is provided on the front side of the second conductivity type body region 6 and is located in the second conductivity type body region 6. In this embodiment, multiple first conductivity type source regions 7 are provided. Two first conductivity type source regions 7 are provided at each gate structure 5, respectively located on both sides of the gate structure 5 facing the second conductivity type pillar 4, and extending in the direction of the second conductivity type pillar 4.

[0035] Specifically, the gate structure 5 includes a trench 51 formed on the front side of the first conductivity type epitaxial layer 2. The trench 51 extends from the front side of the first conductivity type epitaxial layer 2 with the second conductivity type body region 6 to the back side of the first conductivity type epitaxial layer 2, until it extends into the first conductivity type epitaxial layer 2 on the back side of the second conductivity type body region 6. A gate 52 is disposed in the trench 51. A gate oxide layer 53 is disposed between the gate 52 and the inner wall of the trench 51. The gate 52 is separated from the inner wall of the trench 51 by the gate oxide layer 53. The gate 52 is made of conductive polysilicon. The thickness of the gate oxide layer 53 between the gate 52 and the inner bottom wall of the trench 51 is greater than the thickness of the gate oxide layer 53 between the gate 52 and the inner side wall of the trench 51. The thicker gate oxide layer 53 at the bottom can improve the gate oxide reliability of the device.

[0036] In another embodiment, the gate structure 5 also includes a shielding gate 54 disposed in the trench 51. The shielding gate 54 is located below the gate 52. The depth of the shielding gate 54 in the trench 51 is greater than the depth of the gate 52 in the trench 51. The shielding gate 54 and the inner wall of the trench 51 are also separated by the gate oxide layer 53. There is a gap between the shielding gate 54 and the gate 52, which is also separated by the gate oxide layer 53. By providing the shielding gate 54, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0037] As another implementation method, refer to Figure 2 As shown, the gate structure 5 has two gates 52, and a shielding gate 54 is located between the two gates 52. Both the gates 52 and the shielding gate 54 extend from the opening of the trench 51 into the trench 51. Gaps are left between the gates 52 and the inner wall of the trench 51, as well as between the shielding gate 54 and the gates 52. Gate oxide layers 53 are provided between the shielding gate 54 and the gates 52, between the gates 52 and the inner sidewall of the trench 51, and between the shielding gate 54 and the bottom wall of the trench 51, which serve as separations. The depth of the trench 51 is set to 1.5μm-3μm, and the depth of the shielding gate 54 in the trench 51 is greater than the depth of the gates 52 in the trench 51. In another embodiment, the number of gates 52 is not uniquely limited and can also be multiple.

[0038] An insulating dielectric layer 8 is disposed on the front side of the second conductive type body region 6 and covers the entire second conductive type body region 6. Multiple metal contact vias 11 are formed in the insulating dielectric layer 8. The metal contact vias 11 are correspondingly disposed with the second conductive type pillar 4. The metal contact vias 11 extend into the second conductive type body region 6 above the second conductive type pillar 4 and communicate with the first conductive type source region 7. A front metal layer 9 is disposed on the front side of the insulating dielectric layer 8, and the portion of the front metal layer 9 located at the metal contact via 11 extends into the metal contact via 11 until it fills the metal contact via 11. At this time, a portion of the front metal layer 9 in the metal contact via 11 corresponding to the second conductive type pillar 4 will contact the second conductive type body region 6 and the first conductive type source region 7. A back metal layer 10 is disposed on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0039] When a shielding gate 54 is provided and two gates 52 are provided, a metal contact through hole 11 is also provided at the insulating dielectric layer 8 directly above the shielding gate 54, and the front metal layer 9 will also extend into the metal contact through hole 11 to fill the metal contact through hole 11.

[0040] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

Claims

1. A multilayer epitaxial super junction semiconductor structure, characterized by, include: First conductivity type substrate; The first conductivity type epitaxial layer is disposed on the front side of the first conductivity type substrate and has multiple layers. The second conductive type pillars are provided in at least two and are disposed within the first conductive type epitaxial layer, extending from the front side to the back side of the first conductive type epitaxial layer; The first conductivity type attraction area is located within the second conductivity type column.

2. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, Each of the second conductive type pillars is provided with at least two first conductive type attraction regions, which are respectively located in adjacent first conductive type epitaxial layers.

3. The multilayer epitaxial super junction semiconductor structure of claim 2, wherein, Multiple first-conductive type attraction regions within each first-conductive type column are connected sequentially.

4. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, The first conductive type attraction area is located in the middle region of the second conductive type column along the first direction.

5. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, The concentration of ions of the first conductivity type in the first conductivity type attraction region is higher than the concentration of ions of the first conductivity type in the first conductivity type epitaxial layer.

6. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, The length of the first conductive type attraction region along the second direction is less than the length of the second conductive type pillar along the second direction.

7. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, The first conductivity type epitaxial layer is stacked in n layers starting from the front side of the first conductivity type substrate, wherein the thickness of the nth first conductivity type epitaxial layer is not greater than the thickness of the (n-1)th first conductivity type epitaxial layer, and the thickness of the nth first conductivity type epitaxial layer is less than the thickness of the first first conductivity type epitaxial layer.

8. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, The first type of conductive epitaxial layer has 7-13 layers.

9. The multilayer epitaxial super junction semiconductor structure of claim 1, wherein, Also includes: The second conductivity type body region is disposed on the front side of the first conductivity type epitaxial layer and located within the first conductivity type epitaxial layer; A gate structure is disposed between two adjacent pillars of the second conductivity type; The first conductivity type source region is disposed on the front side of the second conductivity type body region and located within the second conductivity type body region; An insulating dielectric layer is disposed on the front side of the second conductive type body region, and a plurality of metal contact through holes corresponding to the second conductive type pillars are formed in the insulating dielectric layer; A front metal layer is disposed on the front side of the insulating dielectric layer and extends into the metal contact via until it fills the metal contact via. A back metal layer is disposed on the back side of the first conductivity type substrate.

10. The multilayer epitaxial super junction semiconductor structure of claim 9, wherein, The gate structure includes a trench formed on the front side of the first conductivity type epitaxial layer, a gate is disposed in the trench, a gate oxide layer is disposed between the gate and the inner wall of the trench, and one or two gates are disposed.

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