Signal processing circuit and signal detection system

Abstract

This application relates to the field of signal processing technology, and discloses a signal processing circuit and a signal detection system. The signal processing circuit includes a first filter circuit, a transformer, and a second filter circuit. The first filter circuit is configured to filter out interference noise in the signal to be processed. The transformer is configured to receive the signal processed by the first filter circuit and convert the signal processed by the first filter circuit into a differential signal. The second filter circuit is configured to receive the differential signal, filter out interference noise in the differential signal, and output the signal. Embodiments of this application can perform signal processing on analog signals of various frequency bands, exhibiting high adaptability.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a signal processing circuit and a signal detection system. Background Technology

[0002] Analog signals need to undergo appropriate signal processing before being transmitted to the processor's ADC port.

[0003] In related technologies, signal processing for analog signals includes filtering and differential conversion to remove noise and convert the analog signal into a differential form. However, current differential conversion circuit topologies for analog signals are based on operational amplifiers, which can only perform differential processing on low-frequency analog signals, resulting in poor applicability. Utility Model Content

[0004] The purpose of this application is to provide a signal processing circuit and a signal detection system that can perform signal processing on analog signals of multiple frequency bands and has high adaptability.

[0005] This application provides a signal processing circuit, including: The first filtering circuit is configured to filter out interference noise in the signal to be processed; The transformer is configured to receive the signal processed by the first filter circuit and to convert the signal processed by the first filter circuit into a differential signal. The second filtering circuit is configured to receive the differential signal, filter out interference noise in the differential signal, and output the signal.

[0006] In some embodiments, the first filter circuit includes at least one LC parallel resonant topology, through which a signal whose frequency is within the operating frequency range of the transformer is extracted from the signal to be processed and output.

[0007] In some embodiments, the LC parallel resonant topology includes a first capacitor and a first inductor connected in parallel. The first filter circuit further includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to the first terminal of the first inductor, and the first terminal of the third capacitor is connected to the second terminal of the first inductor. The second terminals of the second capacitor and the second terminal of the third capacitor are grounded.

[0008] In some embodiments, the second filtering circuit includes at least one RC low-pass filter topology, which suppresses differential-mode interference noise and high-frequency interference noise in the differential signal.

[0009] In some embodiments, the RC low-pass filter topology includes a first resistor, a second resistor, and a fourth capacitor. The second filter circuit further includes a discharge topology. The first end of the first resistor is connected to the first end of the secondary winding of the transformer and the first end of the fourth capacitor. The first end of the second resistor is connected to the second end of the secondary winding of the transformer and the second end of the fourth capacitor. The first end of the discharge topology is connected to the second end of the first resistor, and the second end of the discharge topology is connected to the second end of the second resistor.

[0010] In some embodiments, the signal processing circuit further includes a step-down circuit; the step-down circuit is connected between the first filter circuit and the transformer, and is configured to step down the signal processed by the first filter circuit before outputting it.

[0011] In some embodiments, the step-down circuit includes at least one resistor divider topology, which limits and divides the current of the signal processed by the first filter circuit before outputting it.

[0012] In some embodiments, the signal processing circuit further includes a signal sampling circuit; the signal sampling circuit is connected to the secondary winding of the transformer and is configured to perform current limiting processing on the differential signal before outputting it.

[0013] In some embodiments, the signal sampling circuit includes at least one resistor current limiting topology, through which the differential signal is current limited before being output as a bus.

[0014] This application also provides a signal detection system, including: The aforementioned signal processing circuit; The processor, connected to the second filter circuit, is configured to detect the signal processed by the second filter circuit.

[0015] The beneficial effects of this application are: it eliminates the need for operational amplifiers and instead uses a transformer to convert single-ended signals into differential signals, breaking through the upper limit of the operating frequency of operational amplifiers and adapting to the needs of analog signal processing over a wider frequency range. The pre-stage filter circuit works in conjunction with the transformer to ensure that the effective signal passes through smoothly and to eliminate the negative impact of high-frequency interference on the transformer. The post-stage filter circuit is designed for the characteristics of differential signals and effectively suppresses differential-mode interference introduced during transmission. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the signal processing circuit provided in the first embodiment of this application.

[0017] Figure 2This is a schematic diagram of the signal processing circuit provided in the second embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the signal processing circuit provided in the third embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the signal processing circuit provided in the fourth embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the signal processing circuit provided in the fifth embodiment of this application.

[0021] Figure 6 This is a schematic diagram of the signal detection system provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] It should be noted that the terms "first," "second," "third," "fourth," etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device that includes a series of circuits is not necessarily limited to those explicitly listed, but may include other circuits not explicitly listed or inherent to such systems, products, or devices.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0025] Before being transmitted to the processor's ADC port, analog signals need to undergo corresponding signal processing. For example, in a sensor signal acquisition scenario, the analog sensor signal acquired by the sensor is processed to remove interference noise before being converted from analog to digital. The resulting digital sensor signal is then transmitted to the processor, where the sensor performs signal detection based on this digital signal.

[0026] In related technologies, signal processing for analog signals includes filtering and differential conversion to remove noise and convert the analog signal into a differential form. However, current differential conversion circuit topologies for analog signals are based on operational amplifiers, which can only perform differential processing on low-frequency analog signals, resulting in poor applicability.

[0027] Based on this, embodiments of this application provide a signal processing circuit and a signal detection system that utilizes a transformer to perform differential conversion processing on analog signals, which can adapt to analog signals of various frequency bands.

[0028] See Figure 1 In one embodiment, the signal processing circuit includes a first filter circuit 10, a transformer 20, and a second filter circuit 30, which are connected sequentially.

[0029] The first filter circuit 10 is configured to filter out interference noise in the signal to be processed. It can be understood that the first filter circuit 10 refers to a filter module with frequency selection function, specifically implemented using an LC parallel resonant topology. It filters out interference noise in the signal to be processed by suppressing frequency signals outside the operating frequency band of the transformer 20. The first filter circuit 10 receives the external signal to be processed and performs preliminary filtering to obtain a signal processed by the first filter circuit 10 within the operating frequency band of the transformer 20, matching the resonant frequency.

[0030] Transformer 20 is configured to receive the signal processed by the first filter circuit 10 and to convert the signal processed by the first filter circuit 10 into a differential signal. Transformer 20 can be understood as an electromagnetic energy conversion device, specifically implemented using a magnetic core winding structure. The signal processed by the first filter circuit 10, received by transformer 20, is converted into a symmetrical differential signal through electromagnetic induction, transforming it from a single-ended signal.

[0031] The second filter circuit 30 is configured to receive the differential signal, filter out interference noise from the differential signal, and output the signal. It can be understood that the second filter circuit 30 refers to a filter module with differential mode suppression function, specifically implemented using an RC low-pass filter topology, which attenuates high-frequency interference components through a resistor-capacitor network. The second filter circuit 30 receives the differential signal processed by transformer 20 and filters out interference noise. The signal processed by the second filter circuit 30 is then transmitted to an external processor for signal detection.

[0032] In practical applications, the signal to be processed first enters the first filter circuit 10, which filters out noise outside the target frequency band. The signal processed by the first filter circuit 10 is then coupled through the windings of the transformer 20 to form a differential signal with opposite phase. The differential signal is transmitted to the second filter circuit 30, which suppresses residual differential-mode noise and high-frequency interference before finally outputting it to the processor for sampling and detection. Thus, by using the transformer 20 instead of an operational amplifier for differential conversion, the upper frequency limit of traditional circuits is broken, allowing signal processing for analog signals across multiple frequency bands. The first filter circuit 10 and the transformer 20 work together to ensure the smooth passage of the effective signal while eliminating the negative impact of high-frequency interference on the transformer 20. The second filter circuit 30 is designed specifically for the characteristics of differential signals, effectively suppressing common-mode interference introduced during transmission.

[0033] In some embodiments, the first filter circuit 10 includes at least one LC parallel resonant topology. The first filter circuit 10 extracts signals whose frequencies are within the operating frequency range of the transformer 20 from the signal to be processed through the LC parallel resonant topology and outputs them.

[0034] An LC parallel resonant topology refers to a resonant circuit formed by connecting capacitors and inductors in parallel. Specifically, it can be implemented using a combination of metallized polypropylene film capacitors and ferrite core inductors. The resonant frequency of the LC parallel resonant topology is determined by the capacitance and inductance values ​​of both components. The operating frequency range of transformer 20 refers to the frequency range within which transformer 20 can effectively perform signal conversion, specifically from 400kHz to 60MHz. This range is set based on the core material and winding parameters of transformer 20.

[0035] The LC parallel resonant topology exhibits high impedance at its resonant frequency, suppressing frequency signals within its operating frequency range while allowing signals outside this range to pass through. When the signal to be processed is input to the first filter circuit 10, the LC parallel resonant topology filters the signal through impedance matching, allowing only valid signals within its operating frequency range to reach the transformer 20. Therefore, by configuring the LC parallel resonant topology, a frequency selection structure composed of passive components, it can achieve wideband signal filtering without external power supply, making it particularly suitable for industrial environments with strong electromagnetic interference.

[0036] See also Figure 1 and Figure 2In one embodiment, the LC parallel resonant topology includes a first capacitor C1 and a first inductor L1 connected in parallel. The first filter circuit 10 further includes a second capacitor C2 and a third capacitor C3. The first terminal of the second capacitor C2 is connected to the first terminal of the first inductor L1, the first terminal of the third capacitor C3 is connected to the second terminal of the first inductor L1, and the second terminals of the second capacitor C2 and the third capacitor C3 are grounded.

[0037] When the signal to be processed is input to the first filter circuit 10, the LC parallel resonant topology suppresses interference components outside the operating frequency range of the transformer 20 through the impedance characteristics of the first capacitor C1 and the first inductor L1. The second capacitor C2 and the third capacitor C3 are respectively connected across the first inductor L1 and grounded, forming a low-impedance path for high-frequency noise. The first filter circuit 10 filters out interference noise in two stages before it enters the transformer 20. The LC parallel resonant topology filters out interference outside the main frequency band, while the grounded second capacitor C2 and third capacitor C3 further absorb residual high-frequency noise. Thus, the signal to be processed has undergone two filtering processes before entering the transformer 20 for differential conversion. This not only expands the suppression range of high-frequency noise but also balances the high-frequency potential difference across the first inductor L1, avoiding resonant frequency shift caused by parasitic parameters and effectively improving signal purity.

[0038] In some embodiments, the second filter circuit 30 includes at least one RC low-pass filter topology, which suppresses differential-mode interference noise and high-frequency interference noise in the differential signal.

[0039] An RC low-pass filter topology refers to a filter network composed of resistors and capacitors. Specifically, it can be implemented using a series resistor and parallel capacitor topology. Its cutoff frequency is determined by the product of the resistance and capacitance values, and it is used to filter out interference components in the signal that are higher than a set frequency. Differential-mode interference noise refers to inverse noise signals of the same amplitude existing between the two transmission lines of a differential signal. It can be suppressed by setting a symmetrical RC network along the differential signal transmission path. High-frequency interference noise refers to electromagnetic interference whose frequency exceeds the effective detection range of the back-end processor. It can be filtered out by adjusting the cutoff frequency of the RC low-pass filter topology.

[0040] After the differential signal conversion is completed by transformer 20, the differential signal is transmitted to an RC low-pass filter topology. The filter network, composed of resistors and capacitors, symmetrically processes the two transmission paths of the differential signal. The resistors limit the rate of change of current in the high-frequency signal, while the capacitors suppress differential-mode interference noise. During this process, the differential-mode interference noise, due to its symmetrical distribution along the two transmission paths, has its energy dissipated by the resistors and absorbed by the capacitors, while the high-frequency interference noise is filtered out by the low-impedance path of the capacitors. Finally, the purified differential signal is output to the back-end processor. Thus, the symmetrical RC low-pass filter topology simultaneously achieves differential-mode suppression and high-frequency filtering, simplifying the circuit structure while avoiding the introduction of additional power consumption. This is particularly suitable for industrial testing scenarios with limited space and high electromagnetic compatibility requirements.

[0041] See also Figure 1 and Figure 3 In one embodiment, the RC low-pass filter topology includes a first resistor R1, a second resistor R2, and a fourth capacitor C4. The second filter circuit 30 also includes a discharge topology. The first terminal of the first resistor R1 is connected to the first terminal of the secondary winding of the transformer 20 and the first terminal of the fourth capacitor C4. The first terminal of the second resistor R2 is connected to the second terminal of the secondary winding of the transformer 20 and the second terminal of the fourth capacitor C4. The first terminal of the discharge topology is connected to the second terminal of the first resistor R1, and the second terminal of the discharge topology is connected to the second terminal of the second resistor R2.

[0042] In this embodiment, the discharge topology includes a third resistor R3 and a fifth capacitor C5. The first end of the third resistor R3 is connected to the two ends of the first resistor R1, the second end of the third resistor R3 is connected to the second end of the second resistor R2, and the fifth capacitor C5 is connected in parallel with the third resistor R3.

[0043] When the differential signal is output through the secondary winding of transformer 20, the first resistor R1 and the second resistor R2 are connected in series in the two transmission paths of the differential signal, respectively, and the fourth capacitor C4 is connected across the two paths to form a common-mode filter circuit. High-frequency components in the differential signal are bypassed through the low-impedance circuit formed by the fourth capacitor C4, while the low-frequency effective signal is transmitted with current limiting through the resistor. A discharge topology is connected across the ends of the two signal paths. When transient overvoltage or electrostatic accumulation occurs, the third resistor R3 and the fifth capacitor C5 in the discharge topology can quickly conduct to form a discharge path, preventing signal distortion caused by charge accumulation. Thus, filtering and discharge protection are integrated into the same topology, achieving real-time noise suppression through the synergistic effect of resistors and capacitors, while simultaneously improving circuit reliability by utilizing the dynamic response characteristics of the discharge topology.

[0044] See Figure 4 In one embodiment, the signal processing circuit further includes a buck circuit 40.

[0045] The step-down circuit 40 is connected between the first filter circuit 10 and the transformer 20. The step-down circuit 40 is configured to step down the signal processed by the first filter circuit 10 before outputting it.

[0046] The step-down circuit 40 refers to a circuit module that reduces the voltage amplitude. Specifically, it can be implemented using a voltage divider network to adjust the signal processed by the pre-stage to a voltage level suitable for the operating range of the transformer 20.

[0047] After the first filter circuit 10 filters out interference noise, the signal processed by the first filter circuit 10 is transmitted to the step-down circuit 40. The step-down circuit 40 attenuates the signal processed by the first filter circuit 10 according to a preset ratio. For example, when the voltage of the signal processed by the first filter circuit 10 exceeds the withstand threshold of the transformer 20, the step-down circuit 40 can reduce the voltage to a safe range. The voltage-divided signal is transmitted to the primary winding of the transformer 20 through the connection node, avoiding core saturation or winding breakdown due to overvoltage. This process achieves voltage adaptation through passive components while maintaining the integrity of the signal waveform, and signal conditioning can be completed without additional power supply. Therefore, by adding a voltage divider step-down structure to the signal transmission path, the signal amplitude is actively adjusted through physical voltage division, which avoids the bandwidth limitation caused by active components and expands the circuit's adaptability to different input voltages.

[0048] In some embodiments, the buck circuit 40 includes at least one resistor divider topology, which limits and divides the current of the signal processed by the first filter circuit 10 before outputting it.

[0049] A resistor voltage divider topology refers to a voltage divider module formed by two or more resistors connected in series. Specifically, it can be implemented by connecting two resistors with different resistance values ​​in series, and the voltage division ratio can be controlled by adjusting the resistance ratio.

[0050] The signal processed by the first filter circuit 10 is divided by resistors in the voltage divider topology of the step-down circuit 40. For example, the voltage divider topology could include a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The fourth resistor R4 is connected between the first filter circuit 10 and the transformer 20. The first terminal of the fifth resistor R5 is connected to the first terminal of the fourth resistor R4, and the first terminal of the sixth resistor R6 is connected to the second terminal of the fourth resistor R4. The second terminals of the fifth resistor R5 and the sixth resistor R6 are grounded. By adjusting the resistance ratio among the three resistors, the voltage of the divided signal can be adjusted to a range suitable for the amplitude conversion of the transformer 20. Simultaneously, the total resistance of the voltage divider topology forms a current-limiting impedance, suppressing transient current spikes in the signal. The divided signal is electromagnetically coupled through the primary winding of the transformer 20 and converted into a differential signal, which is then output to the second filter circuit 30. Therefore, by actively adjusting the signal amplitude through the resistor divider topology, the signal input to transformer 20 is always within its linear conversion range, avoiding signal distortion. In addition, the resistor divider topology does not rely on active devices such as operational amplifiers and can adapt to the step-down processing of higher frequency signals.

[0051] See Figure 5 In one embodiment, the signal processing circuit further includes a signal sampling circuit 50.

[0052] The signal sampling circuit 50 is connected to the secondary winding of the transformer 20. The signal sampling circuit 50 is configured to output the differential signal after current limiting.

[0053] The signal sampling circuit 50 is a circuit module used to limit the current of the differential signal output from the transformer 20. Specifically, it can be implemented using a resistor current-limiting topology to prevent damage to subsequent circuits due to overcurrent by limiting the current intensity. The bus output refers to the process of merging the two current-limited differential signals into a single output signal. This can be achieved through a parallel resistor network, which reduces signal distortion while maintaining the symmetry of the signal transmission path.

[0054] The signal sampling circuit 50 is connected to both ends of the secondary winding of the transformer 20. After the differential signal passes through the signal sampling circuit 50, the current amplitude is limited to a safe range. For example, when there is a transient overcurrent in the differential signal, the signal sampling circuit 50 absorbs voltage spikes (such as ESD pulses or sudden changes in inductive loads) in the differential signal, buffers the transient current of the differential signal, and then outputs the current-limited differential signal to the processor or other back-end circuits to protect sensitive devices in the circuit. This process avoids device damage caused by excessive current while maintaining the integrity of the signal waveform. Therefore, by directly limiting the current of the differential signal using the signal sampling circuit 50, the applicable frequency range of the signal processing circuit is expanded.

[0055] In some embodiments, the signal sampling circuit 50 includes at least one resistor current limiting topology, through which the differential signal is current limited before being output as a bus.

[0056] Resistor current limiting topology refers to a circuit structure that uses the impedance characteristics of a resistor to control the current amplitude. Specifically, it can be implemented by using a series resistor. By adjusting the resistance value, the input impedance of the back-end circuit can be matched, thereby avoiding damage to the back-end processor caused by overcurrent.

[0057] In this embodiment, the resistor current-limiting topology includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a sixth capacitor C6. The first terminal of the seventh resistor R7 is connected to the first terminal of the secondary winding of the transformer 20, the first terminal of the eighth resistor R8 is connected to the second terminal of the secondary winding of the transformer 20, the first terminal of the ninth resistor R9 is connected to the second terminals of the seventh resistor R7, the eighth resistor R8, and the sixth capacitor C6, the second terminal of the ninth resistor R9 is connected to an external processor, and the second terminal of the sixth capacitor C6 is grounded.

[0058] When the differential signal is output from the secondary winding of transformer 20, its positive and negative signals flow through the current-limiting paths formed by the seventh resistor R7 and the eighth resistor R8, respectively. Due to the impedance characteristics of the resistors, the signal current is limited to a preset range when flowing through the seventh resistor R7 or the eighth resistor R8, thereby eliminating the threat of transient overshoot current to the back-end processor. The two current-limited signals are combined into a single signal through a parallel bus node, and then subjected to current-limiting processing again by the ninth resistor R9. During this process, the resistor network can balance the impedance difference between the two signals, avoiding common-mode noise caused by impedance mismatch, and the sixth capacitor C6 eliminates bypass noise interference in the signal current. Thus, a passive resistor network is used to achieve the current-limiting function, and the symmetrical layout of the resistor network ensures the stability of signal transmission, making it particularly suitable for reliable transmission of small signals in high-precision detection systems.

[0059] See Figure 6 In one embodiment, the signal detection system includes a signal processing circuit 1 and a processor 2 as provided in the above embodiments. The processor 2 is connected to a second filtering circuit 30, and the processor 2 is configured to detect the signal processed by the second filtering circuit 30.

[0060] The signal to be processed first passes through the first filter circuit 10 to filter out interference noise, and then is converted into a differential signal by the transformer 20. The differential signal is further filtered by the second filter circuit 30 to remove differential-mode noise and high-frequency interference before being output to the processor 2. The processor 2 samples and detects the processed signal, for example, by converting the analog signal into a digital signal through an ADC module and performing algorithm analysis. In this process, the second filter circuit 30 can suppress high-frequency noise through an RC low-pass filter topology to ensure that the signal input to the processor 2 has a low noise floor, thereby improving detection accuracy. Thus, signal conversion is achieved through the transformer 20, and combined with a multi-stage filtering structure, it can adapt to signal processing needs over a wider frequency range. In addition, the filter topology of the second filter circuit 30, designed specifically for the characteristics of differential signals, effectively suppresses differential-mode interference and high-frequency noise, avoiding the introduction of additional distortion before the signal is transmitted to the processor 2.

[0061] In summary, the signal processing circuit and signal detection system provided in this application embodiment do not require the use of operational amplifiers. Instead, they convert single-ended signals into differential signals through transformers, breaking through the upper limit of the operating frequency of operational amplifiers and adapting to the analog signal processing needs of a wider frequency range. The pre-stage filtering circuit works in conjunction with the transformer to ensure that the effective signal passes through smoothly and to eliminate the negative impact of high-frequency interference on the transformer. The post-stage filtering circuit is designed for the characteristics of differential signals and effectively suppresses differential mode interference introduced during transmission.

[0062] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0063] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A signal processing circuit, characterized in that, include: The first filtering circuit is configured to filter out interference noise in the signal to be processed; The transformer is configured to receive the signal processed by the first filter circuit and to convert the signal processed by the first filter circuit into a differential signal. The second filtering circuit is configured to receive the differential signal, filter out interference noise in the differential signal, and output the signal.

2. The signal processing circuit according to claim 1, characterized in that, The first filtering circuit includes at least one LC parallel resonant topology, which extracts signals whose frequencies are within the operating frequency range of the transformer from the signal to be processed and outputs them.

3. The signal processing circuit according to claim 2, characterized in that, The LC parallel resonant topology includes a first capacitor and a first inductor connected in parallel. The first filter circuit also includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to the first terminal of the first inductor, and the first terminal of the third capacitor is connected to the second terminal of the first inductor. The second terminals of the second capacitor and the second terminals of the third capacitor are grounded.

4. The signal processing circuit according to claim 1, characterized in that, The second filtering circuit includes at least one RC low-pass filter topology, which suppresses differential-mode interference noise and high-frequency interference noise in the differential signal.

5. The signal processing circuit according to claim 4, characterized in that, The RC low-pass filter topology includes a first resistor, a second resistor, and a fourth capacitor. The second filter circuit also includes a discharge topology. The first end of the first resistor is connected to the first end of the secondary winding of the transformer and the first end of the fourth capacitor. The first end of the second resistor is connected to the second end of the secondary winding of the transformer and the second end of the fourth capacitor. The first end of the discharge topology is connected to the second end of the first resistor, and the second end of the discharge topology is connected to the second end of the second resistor.

6. The signal processing circuit according to claim 1, characterized in that, The signal processing circuit further includes a step-down circuit; the step-down circuit is connected between the first filter circuit and the transformer, and is configured to step down the signal processed by the first filter circuit before outputting it.

7. The signal processing circuit according to claim 6, characterized in that, The step-down circuit includes at least one resistor voltage divider topology, which limits and divides the current of the signal processed by the first filter circuit before outputting it.

8. The signal processing circuit according to claim 1, characterized in that, The signal processing circuit further includes a signal sampling circuit; the signal sampling circuit is connected to the secondary winding of the transformer and is configured to perform current limiting processing on the differential signal before outputting it.

9. The signal processing circuit according to claim 8, characterized in that, The signal sampling circuit includes at least one resistor current limiting topology, through which the differential signal is current limited and then output as a combined signal.

10. A signal detection system, characterized in that, include: The signal processing circuit according to any one of claims 1 to 9; The processor, connected to the second filter circuit, is configured to detect the signal processed by the second filter circuit.

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