LED chip and light emitting device

Abstract

This invention provides an LED chip and a light-emitting device. The LED chip can effectively prevent moisture intrusion and protect the LED electrodes by a passivation layer disposed on the surface of the epitaxial stack away from the substrate and extending to the sidewall of the electrode.

Description

Technical Field

[0001] This utility model relates to the field of LED technology, and in particular to an LED chip and a light-emitting device. Background Technology

[0002] LEDs (light-emitting diodes) are widely used in lighting fixtures worldwide. They have advantages such as small size, high brightness, low power consumption, low heat generation, long lifespan, and environmental friendliness. They also come in a wide variety of colors and are very popular with consumers.

[0003] Among them, LED reliability is one of the important indicators for evaluating LED quality that is of great concern. In order to improve the reliability of LEDs in terms of bonding ability and moisture intrusion, SiO2 is usually deposited on the surface of chip electrodes by PECVD during the chip manufacturing process, thereby achieving the purpose of protecting the chip electrodes.

[0004] However, traditional single protective film chips have poor reliability because: 1) Since SiO2 is a covalent compound and has a different crystal structure from metals, the chemical bonding between the two is weak, resulting in poor adsorption; 2) SiO2 is an acidic oxide, which will undergo chemical reactions in an alkaline environment, leading to electrode exposure; 3) SiO2 deposited by PECVD has poor density and is susceptible to moisture intrusion; 4) Due to the limitations of the PECVD process, the passivation layer prepared by this method cannot achieve full coverage of steps in the production of LED chips with high aspect ratios. Utility Model Content

[0005] Based on this, the purpose of this utility model is to provide an LED chip and a light-emitting device, which aims to protect the LED electrodes by using a composite dielectric protective film structure, thereby avoiding the problem of LED chip failure caused by the exposure of electrodes due to the single structure of traditional protective films.

[0006] The first aspect of this application provides an LED chip, the LED chip comprising: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode is disposed on the side surface of the epitaxial stack opposite to the substrate; A passivation layer is disposed on the surface of the epitaxial stack opposite to the substrate and extends to the sidewall of the electrode.

[0007] Furthermore, the passivation layer includes a metal oxide passivation layer.

[0008] Furthermore, the passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer is a metal oxide passivation layer and the second passivation layer includes a non-metal oxide passivation layer.

[0009] Furthermore, the first passivation layer serves as the bottom contact layer of the passivation layer.

[0010] Furthermore, the first passivation layer serves as the top layer of the passivation layer.

[0011] Furthermore, the passivation layer also covers a portion of the electrode surface facing away from the substrate.

[0012] Furthermore, the first passivation layer and / or the second passivation layer cover the surface of the epitaxial stack facing away from the substrate.

[0013] Furthermore, it also includes an adhesive layer; The adhesion layer is disposed between the passivation layer and the electrode.

[0014] Furthermore, the electrode has a groove on the surface opposite to the substrate.

[0015] Furthermore, the first passivation layer is an Al2O3 layer.

[0016] Furthermore, the second passivation layer is a composite layer composed of one or more of the following: SiO2 layer and Si3N4 layer.

[0017] Furthermore, the adhesion layer is a Ti layer.

[0018] Furthermore, the electrode is an Au layer.

[0019] Furthermore, the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first type semiconductor layer, and the second electrode is electrically connected to the second type semiconductor layer.

[0020] Furthermore, the thickness of the first passivation layer is 50nm~200nm, including the endpoint values; the thickness of the second passivation layer is 50nm~500nm, including the endpoint values.

[0021] Furthermore, the thickness of the adhesion layer is 5 Å to 100 Å, including the endpoint values.

[0022] Furthermore, the LED chip can be a vertical structure, a horizontal structure, or a flip-chip structure.

[0023] A second aspect of this application provides a method for fabricating an LED chip, used to fabricate the LED chip described in the first aspect of this application, the method comprising: Provide a substrate; An epitaxial stack is formed on the substrate; An electrode is formed on the surface of the epitaxial stack facing away from the substrate; A passivation layer is fabricated on the surface of the epitaxial stack away from the substrate and extends to the sidewall of the electrode; the passivation layer includes a metal oxide passivation layer obtained by ALD deposition.

[0024] A third aspect of this application provides a light-emitting device, including the LED chip described in the first aspect of this application.

[0025] Furthermore, the light-emitting device includes at least a display device.

[0026] By means of the above technical solution, this application provides an LED chip and a light-emitting device. The LED chip can effectively prevent moisture intrusion and protect the LED electrodes by a passivation layer disposed on the surface of the epitaxial stack away from the substrate and extending to the sidewall of the electrode. Attached Figure Description

[0027] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0028] Figure 1 This is a schematic diagram of the structure of an LED chip provided in an embodiment of the present utility model; Figure 2 This is a schematic diagram of the structure of an LED chip provided for Comparative Example 1. Detailed Implementation

[0029] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0030] It should be noted that the directional terms appearing in this utility model are based on the relative positional relationships shown in the accompanying drawings and should not be taken as absolute limitations on this application.

[0031] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Specifically, the LED chip includes: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode is disposed on the side surface of the epitaxial stack opposite to the substrate; A passivation layer is disposed on the surface of the epitaxial stack opposite to the substrate and extends to the sidewall of the electrode; the passivation layer includes a metal oxide passivation layer obtained by ALD (Atomic Layer Deposition) deposition, wherein ALD deposition is a thin film deposition technology based on self-limiting chemical reaction, which achieves precise control of atomic-thickness thin films by pulsedly introducing gaseous precursors into the reaction chamber and chemically adsorbing them onto the substrate surface.

[0033] In some embodiments of this utility model, the passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer includes the metal oxide passivation layer obtained by ALD deposition, and the second passivation layer includes a non-metal oxide passivation layer.

[0034] In some embodiments of this utility model, the first passivation layer serves as the bottom contact layer of the passivation layer.

[0035] In some embodiments of this utility model, the first passivation layer serves as the top layer of the passivation layer.

[0036] In some embodiments of this utility model, the passivation layer also covers a portion of the electrode surface away from the substrate. Alternatively, it can be understood that the first passivation layer and / or the second passivation layer cover a portion of the electrode surface away from the substrate.

[0037] In some embodiments of this utility model, the first passivation layer and / or the second passivation layer cover the surface of the epitaxial stack away from the substrate.

[0038] In some embodiments of this utility model, an adhesive layer is also included; The adhesion layer is disposed between the passivation layer and the electrode.

[0039] In some embodiments of this utility model, the electrode has a groove on the surface opposite to the substrate.

[0040] In some embodiments of this utility model, the first passivation layer is an Al2O3 layer.

[0041] In some embodiments of this utility model, the second passivation layer is a composite layer composed of one or more of the SiO2 layer and the Si3N4 layer.

[0042] In some embodiments of this utility model, the adhesive layer is a Ti layer.

[0043] In some embodiments of this invention, the electrode is an Au layer.

[0044] In some embodiments of this utility model, the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first type semiconductor layer, and the second electrode is electrically connected to the second type semiconductor layer. It should be noted that the material of the epitaxial stack includes AlxInyGa. (1-x-y) N orAlxInyGa (1-x-y) P is a III-V group semiconductor material, where 0≤x, y≤1; x+y≤1. When the epitaxial stack material is AlInGaP series, it can emit red light with wavelengths between 610nm and 650nm or yellow light with wavelengths between 550nm and 570nm. When the epitaxial stack material is InGaN series, it can emit blue or deep blue light with wavelengths between 400nm and 490nm or green light with wavelengths between 490nm and 550nm. When the epitaxial stack material is AlGaN series, it can emit UV light with wavelengths between 400nm and 250nm.

[0045] In some embodiments of this utility model, the thickness of the first passivation layer is 50nm~200nm, including the endpoint values; the thickness of the second passivation layer is 50nm~500nm, including the endpoint values.

[0046] In some embodiments of this invention, the thickness of the adhesion layer is 5 Å to 100 Å, including the endpoint values.

[0047] In some embodiments of this utility model, the LED chip has a vertical structure, a horizontal structure, or a flip-chip structure. When the LED chip has a horizontal structure or a flip-chip structure, the substrate can be a substrate; when the LED chip has a vertical structure, the substrate can be a conductive substrate.

[0048] For a better understanding of this solution, please refer to [link / reference]. Figure 1 This is a schematic diagram of the structure of an LED chip provided in an embodiment of the present utility model. The LED chip includes a substrate 1. An epitaxial wafer is located on one side of the substrate 1. The epitaxial wafer includes an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 sequentially stacked on the substrate 1. In this embodiment of the invention, gallium nitride is used as an example of the material for the N-type semiconductor layer 2 and the P-type semiconductor layer 4, but it is not limited thereto. It can be understood that in this embodiment of the invention, the N-type semiconductor layer 2 is a first-type semiconductor layer, and the P-type semiconductor layer 4 is a second-type semiconductor layer. The epitaxial wafer has a first groove 11, which exposes a portion of the surface of the N-type semiconductor layer 2. It can be understood that etching is performed from the surface of the P-type semiconductor layer 4 toward the substrate until a portion of the surface of the N-type semiconductor layer 2 is exposed, thus forming the first groove 11. The N electrode 6, the adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 are sequentially stacked within the first groove 11. A current blocking layer 5, a P electrode 7, an adhesion layer 8, a first passivation layer 9, and a second passivation layer 10 are sequentially stacked on the P-type semiconductor layer 4. The N electrode 6 and the P electrode 7 are made of Au. It can be understood that after the conductive metal layer is processed, the N electrode 6 and the P electrode 7 are formed at corresponding positions on the N-type semiconductor layer 2 and the P-type semiconductor layer 4. That is, the N electrode 6 is the first electrode and the P electrode 7 is the second electrode. The P electrode 7 fills the through-hole 12 formed by the current blocking layer 5, and a second groove 13 with the same shape as the through-hole 12 is formed in the P electrode 7. It can be understood that after depositing a current blocking layer material on the P-type semiconductor layer 4, the current blocking layer material is etched to form a current blocking layer with through-hole 12. The sidewall of the through-hole 12 forms a certain angle with the surface of the P-type semiconductor layer 4. To a certain extent, the shape of the through-hole 12 can be understood as the sidewall of the through-hole 12 forming a certain angle with the surface of the P-type semiconductor layer 4, and the opening size of the through-hole 12 gradually decreases along the direction pointing to the substrate 1. Subsequently, on the current blocking layer 5 with via 12, a P electrode 7 and an adhesion layer 8 are deposited, and the designed circuit pattern is copied from the mask to the surface of the P electrode 7 to form a second groove 13 on the P electrode 7. The angle formed by the sidewall of the second groove 13 is consistent with the angle formed by the sidewall of the via 12 and the surface of the P-type semiconductor layer 4. In addition, the adhesion layer 8 is a certain distance from the opening of the second groove 13. It should be noted that the advantage of forming the second groove 13 is that it can effectively improve the wire bonding capability. Specifically, since the electrode is etched with the second groove 13, which can also be called a step, it can increase the contact area between the solder ball and the electrode and improve the push-pull force. Furthermore, the second groove 13 can effectively prevent the solder ball extrusion process from extending to the edge of the PAD, avoiding the abnormal electrode drop caused by the current blocking layer at the edge of the PAD breaking. Similarly, a third groove 15 is formed on the N electrode 6.

[0049] Specifically, the adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 are respectively arranged in a stepped manner on the surface of the N electrode 6 facing away from the N-type semiconductor layer and the surface of the P electrode 7 facing away from the P-type semiconductor layer, to form a V-shaped opening above the second groove 13, and the V-shaped opening exposes the second groove 13. The adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 respectively wrap the sidewalls of the corresponding P electrode 7 and the sidewalls of the N electrode 6 layer by layer.

[0050] It should be noted that, since the first passivation layer 9 is deposited using ALD technology, it has the advantage of being free of pinholes, effectively isolating moisture. Furthermore, by using Al2O3 as the first passivation layer 9, the chemical properties of Al2O3 can effectively compensate for the weakness of SiO2 being easily corroded by alkalis. In addition, Al2O3 is a high-k dielectric with a large band gap and high barrier, which can reduce tunneling current. Moreover, it has a low defect state density and fixed charge density, which can effectively suppress metal migration.

[0051] In this embodiment of the invention, the adhesion layer 8 is a Ti layer. It can be understood that a highly adhesive metal Ti is added on top of the Au coating on the chip electrode surface to improve the overall adhesion between the metal electrode and the passivation layer protective film. At the same time, by depositing an atomic-level passivation layer, namely the first passivation layer 9, in the sandwich between the PECVD passivation layer and the LED electrode, the passivation layer is a metal oxide passivation layer, which can have good metal bonding with the LED electrode and good covalent bonding with the non-metal oxide passivation layer deposited by PECVD, namely the second passivation layer 10, thereby improving the adhesion between the three film layers.

[0052] Finally, for flip chips with back-side light emission, the increased reflectivity of the metal electrodes helps to improve the chip's light utilization efficiency. Since the refractive index of the second passivation layer 10 is greater than that of the first passivation layer 9, the passivation layer forms an anti-reflection film structure, which can improve the overall light extraction efficiency of the chip to a certain extent.

[0053] In an optional embodiment of this utility model, the thickness of the adhesive layer 8 is 5 Å to 100 Å. For example, the thickness of the adhesive layer 8 is 5 Å, 10 Å, 20 Å, 30 Å, 40 Å, 50 Å, 60 Å, 70 Å, 80 Å, 90 Å or 100 Å, but is not limited thereto.

[0054] In an optional embodiment of this utility model, the thickness of the first passivation layer 9 is 50nm~200nm. For example, the thickness of the first passivation layer 9 is 50nm, 100nm, 150nm or 200nm, etc., but is not limited thereto.

[0055] In an optional embodiment of this utility model, the thickness of the second passivation layer 10 is 50nm~500nm. For example, the thickness of the second passivation layer 10 is 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, etc., but is not limited to this.

[0056] In summary, this utility model provides an LED chip and a light-emitting device. The LED chip can effectively prevent moisture intrusion and protect the LED electrodes by a passivation layer disposed on the surface of the epitaxial stack away from the substrate and extending to the sidewall of the electrode.

[0057] The present invention will be further described below with reference to specific embodiments: Example 1 The LED chip in this embodiment 1 includes: substrate; An epitaxial wafer located on one side of the substrate, the epitaxial wafer comprising an N-type semiconductor layer, an active layer and a P-type semiconductor layer sequentially stacked on the substrate, wherein the N-type semiconductor layer and the P-type semiconductor layer are both made of gallium nitride; The epitaxial wafer has a first groove that exposes a portion of the surface of the N-type semiconductor layer; An N electrode, an adhesion layer, a first passivation layer, and a second passivation layer are sequentially stacked within the first groove. The first passivation layer is an Al2O3 layer, and the second passivation layer is a composite layer composed of one or more of SiO2 and Si3N4 layers. The adhesion layer is a Ti layer, and the first passivation layer is deposited using ALD technology. A current blocking layer, a P electrode, an adhesion layer, a first passivation layer, and a second passivation layer are sequentially stacked on the P-type semiconductor layer, and the N electrode and the P electrode are made of Au. In this configuration, the P electrode fills the via formed by the current blocking layer, and a second groove with the same shape as the via is formed in the P electrode. The adhesion layer, the first passivation layer, and the second passivation layer are respectively arranged in a stepped manner on the surface of the N electrode facing away from the N-type semiconductor layer and the surface of the P electrode facing away from the P-type semiconductor layer, to form a V-shaped opening above the second groove, and the V-shaped opening exposes the second groove. The adhesion layer, the first passivation layer, and the second passivation layer respectively wrap the sidewalls of the corresponding P electrode and the sidewalls of the N electrode layer by layer.

[0058] In a specific embodiment, the thickness of the adhesion layer is 5 Å.

[0059] In a specific embodiment, the thickness of the first passivation layer is 50 nm.

[0060] In a specific embodiment, the thickness of the second passivation layer is 50 nm.

[0061] Example 2 This embodiment 2 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesive layer is 50 Å.

[0062] Example 3 This embodiment 3 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesive layer is 100 Å.

[0063] Example 4 This embodiment 4 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 100 nm.

[0064] Example 5 This embodiment 5 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 300 nm.

[0065] Example 6 This embodiment 6 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 500 nm.

[0066] Example 7 This embodiment 7 also provides an LED chip, the difference from embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the first passivation layer is 100 nm.

[0067] Example 8 This embodiment 8 also provides an LED chip, the difference from embodiment 7 is that the thickness of the second passivation layer is 100nm.

[0068] Example 9 This embodiment 9 also provides an LED chip, the difference from embodiment 7 is that the thickness of the second passivation layer is 300nm.

[0069] Example 10 This embodiment 10 also provides an LED chip, the difference from embodiment 7 is that the thickness of the second passivation layer is 500nm.

[0070] Example 11 This embodiment 11 also provides an LED chip, the difference from embodiment 10 is that the thickness of the first passivation layer is 200nm and the thickness of the second passivation layer is 50nm.

[0071] Example 12 This embodiment 12 also provides an LED chip, the difference from embodiment 11 is that the thickness of the second passivation layer is 100nm.

[0072] Example 13 This embodiment 13 also provides an LED chip, the difference from embodiment 11 is that the thickness of the second passivation layer is 300nm.

[0073] Example 14 This embodiment 14 also provides an LED chip, the difference from embodiment 11 is that the thickness of the second passivation layer is 500nm.

[0074] Example 15 This embodiment 15 also provides an LED chip, the difference from embodiment 14 is that the thickness of the adhesive layer is 100 Å.

[0075] Comparative Example 1 Comparative Example 1 provides an LED chip structure; please refer to [link / reference]. Figure 2 The difference from Embodiment 1 of this utility model is that after forming corresponding electrodes on the N-type semiconductor layer 2 and the P-type semiconductor layer 4, a SiO2 passivation layer 14 is deposited on the electrode surface. The SiO2 passivation layer 14 can be understood as the second passivation layer in this utility model embodiment, and the thickness of the SiO2 passivation layer 14 is 50nm.

[0076] Comparative Example 2 Comparative Example 2 provides an LED chip structure, which differs from Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 100 nm.

[0077] Comparative Example 3 Comparative Example 3 provides an LED chip structure that differs from Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 200 nm.

[0078] Comparative Example 4 Comparative Example 4 provides an LED chip structure, which differs from Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 300 nm.

[0079] The LED chips obtained in Examples 1 to 1 and the LED chip in Comparative Example 1 were subjected to reliability tests under the same conditions. The results are shown in the table below:

[0080] As can be seen from the table, the bonding push-pull force at the electrode of the LED chip in this embodiment is better than that of the LED chip in the comparative example. At the same time, the chip failure rate of the LED chip in this embodiment is lower than that of the LED chip in the comparative example.

[0081] Based on the above embodiments of the present invention, another embodiment of the present invention provides a light-emitting device, which includes the LED chip described in the above embodiments, and the light-emitting device includes at least a display device. The present invention provides a detailed description of an LED chip and a light-emitting device. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section. It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, The LED chip includes: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode is disposed on the side surface of the epitaxial stack opposite to the substrate, and the electrode includes an N electrode and a P electrode; A passivation layer is disposed on the surface of the epitaxial stack opposite to the substrate and extends to the sidewall of the electrode; The passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer includes a metal oxide passivation layer and the second passivation layer includes a non-metal oxide passivation layer, the first passivation layer serves as the bottom contact layer of the passivation layer, and the second passivation layer serves as the top layer of the passivation layer. The passivation layer also covers a portion of the electrode surface facing away from the substrate, and the first passivation layer and / or the second passivation layer cover the surface of the epitaxial stack facing away from the substrate; It also includes an adhesive layer; The adhesion layer is disposed between the passivation layer and the electrode; The electrode has a second groove on the surface opposite to the substrate; Specifically, the adhesion layer, the first passivation layer, and the second passivation layer are respectively arranged in a stepped manner on the surface of the N electrode away from the N-type semiconductor layer and on the surface of the P electrode away from the P-type semiconductor layer to form a V-shaped opening above the second groove, and the V-shaped opening exposes the second groove.

2. The LED chip according to claim 1, characterized in that, The passivation layer includes a metal oxide passivation layer obtained by ALD deposition.

3. The LED chip according to claim 1, characterized in that, The first passivation layer is an Al2O3 layer.

4. The LED chip according to claim 1, characterized in that, The second passivation layer is a composite layer composed of one or more of the following: SiO2 layer and Si3N4 layer.

5. The LED chip according to claim 1, characterized in that, The adhesion layer is a Ti layer.

6. The LED chip according to claim 1, characterized in that, The electrode is Au.

7. The LED chip according to claim 1, characterized in that, The epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first type semiconductor layer, and the second electrode is electrically connected to the second type semiconductor layer.

8. The LED chip according to claim 1, characterized in that, The thickness of the first passivation layer is 50nm~200nm, including the endpoint values; the thickness of the second passivation layer is 50nm~500nm, including the endpoint values.

9. The LED chip according to claim 1, characterized in that, The thickness of the adhesion layer is 5 Å to 100 Å, including the endpoint values.

10. The LED chip according to any one of claims 1-9, characterized in that, The LED chip can be a vertical structure, a horizontal structure, or a flip-chip structure.

11. A light-emitting device, characterized in that, Includes the LED chip as described in any one of claims 1-9.

12. A light-emitting device according to claim 11, characterized in that, The light-emitting device includes at least a display device.

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