Clock circuit and camera

Abstract

The application relates to a clock circuit and a camera. The clock circuit comprises a clock module and M filter modules; the first end of the clock module is connected with the first end of a control circuit and the first end of each filter module respectively, and the second end of the clock module is connected with the second end of the control circuit; the second end of the filter module is connected with the first end of a corresponding load circuit; the clock module is used for generating a first clock signal, inputting the first clock signal into the control circuit and each filter module respectively, and the first clock signal is used for controlling the control circuit to work in a preset time sequence; the filter module is used for filtering the first clock signal to obtain a second clock signal, sending the second clock signal to the corresponding load circuit, and the second clock signal is used for controlling the corresponding load circuit to work in a preset time sequence. The camera comprises the clock circuit.

Description

Technical Field

[0001] This application relates to the field of clock circuit technology, and in particular to a clock circuit and a camera. Background Technology

[0002] With the continuous development of electronic technology and the continuous improvement of people's living standards, the market demand for surveillance cameras is increasing. Currently, the functions of surveillance cameras on the market are becoming increasingly diverse. For example, in addition to basic video recording functions, they can also achieve wireless network connectivity. Therefore, the manufacturing cost of surveillance cameras inevitably increases. Utility Model Content

[0003] Therefore, it is necessary to provide a clock circuit and a camera that enable the control circuit and the M load circuits to operate at the same preset timing.

[0004] In a first aspect, embodiments of this application provide a clock circuit, the clock circuit comprising:

[0005] A clock module and M filter modules; M is an integer greater than or equal to 1;

[0006] The first terminal of the clock module is connected to the first terminal of the control circuit and the first terminal of each filter module, and the second terminal of the clock module is connected to the second terminal of the control circuit; the second terminal of the filter module is connected to the first terminal of the corresponding load circuit.

[0007] The clock module is used to generate a first clock signal, which is then input to the control circuit and each filtering module. The first clock signal is used to control the circuit to operate according to a preset timing sequence.

[0008] The filtering module is used to filter the first clock signal to obtain the second clock signal; the second clock signal is sent to the corresponding load circuit; the second clock signal is used by the corresponding load circuit to operate according to the preset timing sequence.

[0009] In one exemplary embodiment, the clock module includes a first resistor, a second resistor, a first capacitor, a second capacitor, and a crystal oscillator;

[0010] The first end of the first resistor is connected to the first end of the first capacitor, the first end of the crystal oscillator and the first end of the control circuit respectively, and the second end of the first resistor is connected to the first end of the second resistor and the second end of the control circuit respectively.

[0011] The second terminal of the crystal oscillator is connected to the first terminal of the second capacitor and the second terminal of the second resistor, respectively; the third and fourth terminals of the crystal oscillator are connected to the ground terminal, respectively.

[0012] The second terminal of the first capacitor is connected to ground.

[0013] The second terminal of the second capacitor is connected to ground.

[0014] In one exemplary embodiment, the clock module further includes a third resistor;

[0015] The first end of the third resistor is connected to the first end of the first resistor and the first end of the control circuit, and the second end of the third resistor is connected to the first end of each filter module.

[0016] In one exemplary embodiment, the filtering module includes a fourth resistor and a third capacitor;

[0017] The first end of the fourth resistor is connected to the first end of the clock module, and the second end of the fourth resistor is connected to the first end of the third capacitor and the load circuit, respectively.

[0018] The second terminal of the third capacitor is connected to ground.

[0019] In one exemplary embodiment, the filtering module further includes a fourth capacitor;

[0020] The two ends of the fourth capacitor are connected to the first end of the clock module and the first end of the fourth resistor, respectively.

[0021] In one exemplary embodiment, the capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.

[0022] In one exemplary embodiment, the capacitance values ​​of the first capacitor and the second capacitor are positively correlated with the capacitance value of the crystal oscillator.

[0023] Secondly, embodiments of this application provide a camera, which includes a clock circuit, a control circuit, and M load circuits as described in any of the first aspects of this application; the M load circuits include a first load circuit and M-1 second load circuits;

[0024] The first terminal of the clock circuit is connected to the first terminal of the control circuit, the second terminal of the clock circuit is connected to the second terminal of the control circuit, and the third terminal of the clock circuit is connected to the first terminal of each load circuit.

[0025] A control circuit is used to generate a control signal based on a first clock signal and to send the control signal to a first load circuit and each of the second load circuits.

[0026] The first load circuit is used to realize the imaging function based on the second clock signal and the control signal;

[0027] The second load circuit is used to implement the load function based on the second clock signal and the control signal; the load function plays a supporting role in the imaging function.

[0028] In one exemplary embodiment, the control circuit includes a first clock signal port, a second clock signal port, and a first power signal port;

[0029] The first clock signal port is connected to the first terminal of the clock module and the first terminal of each filter module; the second clock signal port is connected to the second terminal of the clock module; the first power signal port is connected to the first power supply.

[0030] The control circuit is specifically used to generate a control signal based on a first clock signal when the first power supply is received; and to send the control signal to the first load circuit and each of the second load circuits respectively.

[0031] In one exemplary embodiment, the load circuit includes a third clock signal port and a second power signal port;

[0032] The third clock signal port is connected to the second terminal of the corresponding filter module; the second power signal port is connected to the second power supply.

[0033] The third clock signal port is used to receive the second clock signal;

[0034] The load circuit is specifically used to realize imaging or load functions based on a second clock signal and control signal when receiving power from a second power source.

[0035] The aforementioned clock circuit, when dealing with M load circuits, does not require multiple clock modules. Instead, it only needs the cooperation of one clock module and M filter modules to provide a first clock signal to the control circuit and a second clock signal to each of the M load circuits. This achieves clock signal sharing between the control circuit and the M load circuits, enabling them to operate at the same preset timing. By ensuring the synchronization between the control circuit and the M load circuits, the stability and coordination between them can be guaranteed. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a clock circuit provided in an embodiment of this application;

[0038] Figure 2This is a schematic diagram of another clock circuit provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of another clock circuit provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of another clock circuit provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure of a camera provided in an embodiment of this application. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0045] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0046] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0048] like Figure 1 As shown, a clock circuit 10 in one embodiment includes:

[0049] Clock module 102 and M filter modules 104; M is an integer greater than or equal to 1.

[0050] The first terminal of the clock module 102 is connected to the first terminal of the control circuit and the first terminal of each filter module 104. The second terminal of the clock module 102 is connected to the second terminal of the control circuit. The second terminal of the filter module 104 is connected to the first terminal of the corresponding load circuit.

[0051] The clock module 102 is used to generate a first clock signal and input the first clock signal to the control circuit and each filter module 104 respectively; the first clock signal is used to control the circuit to work according to a preset timing sequence.

[0052] The filtering module 104 is used to filter the first clock signal to obtain the second clock signal; send the second clock signal to the corresponding load circuit; and use the second clock signal to make the corresponding load circuit work according to a preset timing sequence.

[0053] Since the second terminal of the filter module 104 is connected to the first terminal of the corresponding load circuit, each filter module 104 corresponds to one load circuit. That is, the number of filter modules 104 corresponds to the number of load circuits. Therefore, M is not only the number of filter modules 104, but also the number of load circuits electrically connected to the clock circuit 10.

[0054] Optionally, the M load circuits can each have a different function. For example, there can be a load circuit for implementing imaging, a load circuit for implementing wireless communication, and a load circuit for implementing wired communication.

[0055] Optionally, the control circuit may include a system-on-a-chip (SOC). Optionally, the SOC included in the control circuit may be a T23 chip.

[0056] It is easy to understand that since the second clock signal is obtained by filtering the first clock signal, the first clock signal and the second clock signal have the same waveform and frequency.

[0057] Optionally, the waveforms of the first clock signal and the second clock signal can be square wave signals, sine wave signals, or other waveform signals.

[0058] Optionally, the frequencies of the first clock signal and the second clock signal correspond to the same first preset frequency. The first preset frequency can be 18MHz-30MHz. For example, the frequencies of the first clock signal and the second clock signal can be 24MHz.

[0059] The first clock signal and the second clock signal provide a common time reference for the control circuit and the M load circuits, enabling the control circuit and the M load circuits to operate in the same preset timing sequence. The preset timing sequence is a series of time parameters defined based on this time reference (for example, the time parameters may be start time, end time, time interval, etc.), so that each operation performed by the control circuit and the M load circuits can occur at the correct time node, thereby ensuring the stability and coordination between the control circuit and the M load circuits.

[0060] The aforementioned clock circuit 10, when dealing with M load circuits, does not require multiple clock modules 102. Instead, it only needs the cooperation between one clock module 102 and M filter modules 104 to provide a first clock signal to the control circuit and a second clock signal to each of the M load circuits. This achieves the sharing of clock signals between the control circuit and the M load circuits, enabling the control circuit and the M load circuits to operate at the same preset timing. By ensuring the synchronization between the control circuit and the M load circuits, the stability and coordination between the control circuit and the M load circuits can be guaranteed.

[0061] In one exemplary embodiment, such as Figure 2 As shown, the clock module 102 includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a crystal oscillator Y.

[0062] The first end of the first resistor R1 is connected to the first end of the first capacitor C1, the first end of the crystal oscillator Y, and the first end of the control circuit, respectively. The second end of the first resistor R1 is connected to the first end of the second resistor R2 and the second end of the control circuit, respectively.

[0063] The second terminal of the crystal oscillator Y is connected to the first terminal of the second capacitor C2 and the second terminal of the second resistor R2, respectively. The third and fourth terminals of the crystal oscillator Y are connected to the ground terminal, respectively.

[0064] The second terminal of the first capacitor C1 is connected to ground.

[0065] The second terminal of the second capacitor C2 is connected to ground.

[0066] The first resistor, R1, is used to form negative feedback within the control circuit. Since its two ends are connected to the two ends of the control circuit, R1 acts as a feedback resistor for the control circuit. Forming negative feedback within the control circuit helps improve the stability of the control circuit's gain, thereby enhancing its performance.

[0067] The second resistor R2 is a protective resistor used to prevent excessive voltage or current, thereby protecting the safety of the electrical components in the clock module 102.

[0068] The first capacitor C1 and the second capacitor C2 are matching capacitors for the clock module 102. The first capacitor C1 and the second capacitor C2 are used to match the crystal oscillator Y so that the frequency deviation of the crystal oscillator Y is less than the preset frequency deviation and it is easier to start oscillating.

[0069] Optionally, the preset frequency offset can be 20 PPM (Parts Per Million).

[0070] In order for the first capacitor C1 and the second capacitor C2 to be matched with the crystal oscillator Y, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are determined based on the capacitance value of the crystal oscillator Y.

[0071] Optionally, the capacitance of the crystal oscillator Y can be 8pF.

[0072] In this embodiment, the clock module 102 includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a crystal oscillator Y. The first resistor R1 is a feedback resistor, the second resistor R2 is a protection resistor, and the first capacitor C1 and the second capacitor C2 are matching capacitors. Thus, the first resistor R1 can ensure that the control circuit has high operating performance, the second resistor R2 can protect the safety of the clock module 102, and the first capacitor C1 and the second capacitor C2 can make the crystal oscillator Y more likely to start oscillating, thereby ensuring the stability and accuracy of the first clock signal and the second clock signal.

[0073] Furthermore, the clock circuit 10 provided in this embodiment only needs a clock module 102 including a crystal oscillator Y to enable the control circuit and the M load circuits to operate in the same preset timing sequence. This avoids the undesirable situation that the number of crystal oscillators needs to be increased as the number of load circuits increases, and can improve the integration of the M load circuits connected to the clock circuit 10.

[0074] In one exemplary embodiment, such as Figure 2 As shown, the filter module 104 includes a fourth resistor R4 and a third capacitor C3.

[0075] The first end of the fourth resistor R4 is connected to the first end of the clock module 102, and the second end of the fourth resistor R4 is connected to the first end of the third capacitor C3 and the load circuit respectively.

[0076] The second terminal of the third capacitor C3 is connected to ground.

[0077] The fourth resistor R4 and the third capacitor C3 together form a low-pass filter.

[0078] The low-pass filter composed of the fourth resistor R4 and the third capacitor C3 is used to filter out high-frequency signals and frequency multipliers with frequencies greater than or equal to the second preset frequency, so as to prevent these high-frequency signals and frequency multipliers from interfering with the second clock signal of the first preset frequency transmitted to the load circuit.

[0079] The second preset frequency is greater than the first preset frequency.

[0080] Optionally, the second preset frequency can be 26MHz-34MHz. For example, the low-pass filter composed of the fourth resistor R4 and the third capacitor C3 is used to filter out high-frequency signals and harmonic signals with a frequency greater than or equal to 30MHz.

[0081] In this embodiment, the filtering module 104 includes a fourth resistor R4 and a third capacitor C3. Since the fourth resistor R4 and the third capacitor C3 can be combined into a low-pass filter, the filtering module 104 can avoid interference from high-frequency signals and frequency multiplication signals to the second clock signal, ensuring that the corresponding load circuit can operate at a preset timing based on a preset accurate frequency. In turn, it can ensure the stability and coordination between the control circuit and the M load circuits.

[0082] In one exemplary embodiment, such as Figure 3 As shown, the clock module 102 also includes a third resistor R3.

[0083] The first end of the third resistor R3 is connected to the first end of the first resistor R1 and the first end of the control circuit, and the second end of the third resistor R3 is connected to the first end of each filter module 104.

[0084] Among them, the third resistor R3 is the adjustment resistor, that is, the third resistor R3 can have an adjustable resistance value.

[0085] If the clock module 102 also includes a third resistor R3, the second end of the third resistor R3 is the third end of the clock module 102.

[0086] In this embodiment, the clock module 102 further includes a third resistor R3 as a debugging resistor. Thus, the third resistor R3 allows the clock circuit 10 to be adjusted or its performance optimized even after it has been assembled and put into use. For example, in some cases where the clock module 102 experiences excessive voltage amplitude, this problem can be resolved by adjusting the resistance value of the third resistor R3. It can be seen that the inclusion of the third resistor R3 improves the flexibility and reliability of the clock module 102.

[0087] In one exemplary embodiment, such as Figure 4 As shown, the filter module 104 also includes a fourth capacitor C4.

[0088] The two ends of the fourth capacitor C4 are connected to the first end of the clock module 102 and the first end of the fourth resistor R4, respectively.

[0089] The fourth capacitor C4 is a DC blocking capacitor, used to isolate the DC signal flowing from the clock module 102 to the load circuit and the DC signal flowing from the load circuit to the clock module 102, and to isolate the second clock signal with a frequency lower than the first preset frequency. Therefore, by including the fourth capacitor C4 in the filter module 104, the stability and signal integrity of the second clock signal transmitted from the clock module 102 to the load circuit can be ensured. Based on this, the fourth capacitor C4 can prevent signal interference between the clock module 102 and the corresponding load circuit.

[0090] When the clock module 102 includes a crystal oscillator Y, the fourth capacitor C4 is used to isolate the DC signal flowing from the crystal oscillator Y to the load circuit and the DC signal flowing from the load circuit to the crystal oscillator Y, and to isolate the second clock signal with a frequency lower than the first preset frequency.

[0091] In one exemplary embodiment, the capacitance value of the first capacitor C1 is the same as the capacitance value of the second capacitor C2.

[0092] In an exemplary embodiment, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are positively correlated with the capacitance value of the crystal oscillator Y.

[0093] In an exemplary embodiment, the capacitance value of the first capacitor C1 is the same as that of the second capacitor C2, which is the difference between the product of the capacitance value of the crystal oscillator Y and a preset coefficient and the parasitic capacitance.

[0094] The preset coefficient can be between 0.3 and 0.7. For example, the preset coefficient can be 0.5.

[0095] The size of the parasitic capacitance is determined by the printed circuit board that sets the clock circuit 10. For example, the parasitic capacitance is 0.3pF.

[0096] For example, when the preset coefficient is 0.5 and the parasitic capacitance is 0.3pF, the capacitance value of the first capacitor C1 or the capacitance value of the second capacitor C2 is equal to the capacitance value of the crystal oscillator Y × 0.5 - 0.3.

[0097] In this embodiment, when the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are the same, and are respectively the product of the capacitance value of the crystal oscillator Y and the preset coefficient and the difference between the parasitic capacitance, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are matched with the crystal oscillator Y. Thus, the frequency deviation of the crystal oscillator Y is less than the preset frequency deviation and it is easier to start oscillating, thereby ensuring the stability and accuracy of the first clock signal and the second clock signal.

[0098] It is understood that the clock circuit 10 described above can also take other forms, and is not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of enabling the control circuit and the M load circuits to work in the same preset timing sequence.

[0099] The circuit described above can be applied to electronic devices such as cameras, television receivers, or video game devices that require the control circuit and M load circuits to operate in the same preset timing sequence.

[0100] In one exemplary embodiment, this application also provides a camera, such as Figure 5 As shown, the camera 50 includes a clock circuit 10, a control circuit 12, and M load circuits 14 as described in any of the above embodiments of the clock circuit 10; the M load circuits 14 include a first load circuit 14-1 and M-1 second load circuits 14-2.

[0101] The first terminal of the clock circuit 10 is connected to the first terminal of the control circuit 12, the second terminal of the clock circuit 10 is connected to the second terminal of the control circuit 12, and the third terminal of the clock circuit 10 is connected to the first terminal of each load circuit 14.

[0102] The control circuit 12 is used to generate a control signal based on the first clock signal and send the control signal to the first load circuit 14-1 and each of the second load circuits 14-2.

[0103] The first load circuit 14-1 is used to realize the imaging function based on the second clock signal and the control signal.

[0104] The second load circuit 14-2 is used to implement the load function based on the second clock signal and the control signal; the load function plays a supporting role in the imaging function.

[0105] Among them, camera 50 can be a network camera (IP camera, IPC). IPC camera 50 refers to a camera that transmits images and videos over a network.

[0106] For example, assuming M=2, that is, the camera 50 includes M load circuits 14, then the third terminal of the clock circuit 10 is connected to the first terminal of the first load circuit 14, and the fourth terminal of the clock circuit 10 is connected to the first terminal of the second load circuit 14.

[0107] The control signal is used to cooperate with the second clock signal to enable the first load circuit 14-1 to perform the imaging function based on the correct preset timing, or to cooperate with the second clock signal to enable the second load circuit 14-2 to perform the corresponding load function based on the correct preset timing.

[0108] Optionally, in order to enable the first load circuit 14-1 to perform imaging function, the first load circuit 14-1 includes an image sensor. The image sensor is used to capture incident light and convert the incident light into an electrical signal that can be used to perform imaging function.

[0109] Optionally, the second load circuit 14-2 may include a load circuit 14 for implementing wireless communication functions, or it may include a load circuit 14 for implementing wired communication functions.

[0110] For example, when the second load circuit 14-2 includes a WIFI (Wireless Fidelity) chip for implementing wireless communication functions, the second load circuit 14-2 includes a network port PHY (Physical Layer Transceiver) chip when the second load circuit 14-2 includes a wired communication function.

[0111] The load function works in conjunction with the imaging function, meaning that the load function and the imaging function cooperate to jointly realize the function of the camera 50. For example, if the load function of a certain second load circuit 14-2 is a wireless communication function, the cooperation between the wireless communication function and the imaging function ensures that the image data obtained by the first load circuit 14-1 is transmitted from the camera 50 to the user equipment in a timely and accurate manner. Optionally, the user equipment can be an electronic device with a display interface, such as a personal computer, laptop computer, smartphone, or portable wearable device.

[0112] In an exemplary embodiment, the control circuit 12 includes a first clock signal port 12a, a second clock signal port 12b, and a first power signal port 12c.

[0113] The first clock signal port 12a is connected to the first terminal of the clock module 102 and the first terminal of each filter module 104 respectively; the second clock signal port 12b is connected to the second terminal of the clock module 102; and the first power signal port 12c is connected to the first power supply.

[0114] The control circuit 12 is specifically used to generate a control signal based on a first clock signal when the first power supply is received; and to send the control signal to the first load circuit 14-1 and each of the second load circuits 14-2 respectively.

[0115] Optionally, the first power supply can be a 3.3V power supply.

[0116] As is easily understood, the control circuit 12 receives the first clock signal from the clock circuit 10 through the first clock signal port 12a and the second clock signal port 12b.

[0117] For example, when the control circuit 12 includes the T23 chip, the first clock signal port 12a and the second clock signal port 12b can be the EXCLKI port and the EXCLKO port of the T23 chip.

[0118] In an exemplary embodiment, the load circuit 14 includes a third clock signal port 14a (14a-1 / 14a-2) and a second power signal port 14b (14b-1 / 14b-2).

[0119] The third clock signal port 14a is connected to the second terminal of the corresponding filter module 104; the second power signal port 14b is connected to the second power supply.

[0120] The third clock signal port 14a is used to receive the second clock signal.

[0121] The load circuit 14 is specifically used to realize imaging function or load function based on the second clock signal and control signal when receiving power from the second power supply.

[0122] Optionally, the second power supply can be a 3.3V power supply.

[0123] For example, if the load circuit 14 includes a WIFI chip, the third clock signal port 14a can be the XTAL_P port of the WIFI chip.

[0124] For the control circuit 12 and the M load circuits 14, the camera 50 only needs one clock circuit 10 to make the control circuit 12 and the M load circuits 14 work in the same preset timing sequence. Based on this, the disadvantage of traditional camera printed circuit boards needing to set multiple clock circuits 10 to correspond to the number of load circuits 14 can be overcome. Thus, by reducing the number of clock circuits 10, the manufacturing cost of the camera 50 can be reduced, and the area utilization rate of the printed circuit board of the camera 50 can be significantly improved, thereby increasing the integration of the camera 50.

[0125] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock circuit, characterized in that, The clock circuit includes: A clock module and M filter modules; M is an integer greater than or equal to 1; The first terminal of the clock module is connected to the first terminal of the control circuit and the first terminal of each of the filter modules, and the second terminal of the clock module is connected to the second terminal of the control circuit; the second terminal of the filter module is connected to the first terminal of the corresponding load circuit. The clock module is used to generate a first clock signal and input the first clock signal to the control circuit and each of the filtering modules respectively; the first clock signal is used by the control circuit to operate according to a preset timing sequence. The filtering module is used to filter the first clock signal to obtain a second clock signal; send the second clock signal to the corresponding load circuit; and the second clock signal is used by the corresponding load circuit to operate according to the preset timing sequence.

2. The clock circuit according to claim 1, characterized in that, The clock module includes a first resistor, a second resistor, a first capacitor, a second capacitor, and a crystal oscillator; The first end of the first resistor is connected to the first end of the first capacitor, the first end of the crystal oscillator, and the first end of the control circuit, respectively; the second end of the first resistor is connected to the first end of the second resistor and the second end of the control circuit, respectively. The second terminal of the crystal oscillator is connected to the first terminal of the second capacitor and the second terminal of the second resistor, respectively; the third and fourth terminals of the crystal oscillator are connected to the ground terminal, respectively. The second terminal of the first capacitor is connected to ground. The second terminal of the second capacitor is connected to ground.

3. The clock circuit according to claim 2, characterized in that, The clock module also includes a third resistor; The first end of the third resistor is connected to the first end of the first resistor and the first end of the control circuit, respectively, and the second end of the third resistor is connected to the first end of each of the filter modules.

4. The clock circuit according to claim 1, characterized in that, The filtering module includes a fourth resistor and a third capacitor; The first end of the fourth resistor is connected to the first end of the clock module, and the second end of the fourth resistor is connected to the first end of the third capacitor and the load circuit, respectively. The second terminal of the third capacitor is connected to ground.

5. The clock circuit according to claim 4, characterized in that, The filtering module also includes a fourth capacitor; The two ends of the fourth capacitor are respectively connected to the first end of the clock module and the first end of the fourth resistor.

6. The clock circuit according to claim 2, characterized in that, The capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.

7. The clock circuit according to claim 6, characterized in that, The capacitance values ​​of the first capacitor and the second capacitor are positively correlated with the capacitance value of the crystal oscillator.

8. A camera, characterized in that, The camera includes a clock circuit, a control circuit, and M load circuits as described in any one of claims 1-7; the M load circuits include a first load circuit and M-1 second load circuits. The first terminal of the clock circuit is connected to the first terminal of the control circuit, the second terminal of the clock circuit is connected to the second terminal of the control circuit, and the third terminal of the clock circuit is connected to the first terminal of each of the load circuits. The control circuit is used to generate a control signal based on the first clock signal; The control signal is sent to the first load circuit and each of the second load circuits; The first load circuit is used to realize the imaging function based on the second clock signal and the control signal; The second load circuit is used to implement the load function based on the second clock signal and the control signal; the load function has a cooperating effect on the imaging function.

9. The camera according to claim 8, characterized in that, The control circuit includes a first clock signal port, a second clock signal port, and a first power signal port; The first clock signal port is connected to the first terminal of the clock module and the first terminal of each of the filter modules; the second clock signal port is connected to the second terminal of the clock module; the first power signal port is connected to the first power supply. The control circuit is specifically configured to generate a control signal based on the first clock signal when receiving power from the first power source; and to send the control signal to the first load circuit and each of the second load circuits respectively.

10. The camera according to claim 8, characterized in that, The load circuit includes a third clock signal port and a second power signal port; The third clock signal port is connected to the second terminal of the corresponding filter module; the second power signal port is connected to the second power supply. The third clock signal port is used to receive the second clock signal; The load circuit is specifically used to implement imaging or load functions based on the second clock signal and the control signal when receiving power from the second power source.

Images