Pin short detection circuit

Abstract

A system includes input voltage terminals; a power converter integrated circuit package coupled without a fuse to the input voltage terminals and having first and second pins, the power converter integrated circuit package configured to detect a short circuit between the first and second pins; and a load circuit coupled to the power converter integrated circuit package.

Description

Background Technology

[0001] Various circuits, such as power converters, are housed within packages. The package includes the circuitry and protective materials, such as epoxy resin, to protect the circuitry from damage caused by external factors such as extreme temperatures, liquids, and blunt force. The package also includes multiple pins that facilitate electrical communication between the circuitry housed within the package and external electronic devices, such as devices mounted on a printed circuit board (PCB) together with the package. Package pin layouts vary, with some packages having finer pin spacing than others. Summary of the Invention

[0002] At least some aspects of this disclosure provide a system. In some examples, the system includes an input voltage terminal; a power converter integrated circuit (IC) package that is fuse-free coupled to the input voltage terminal and has first and second pins, the power converter IC package being configured to detect a short circuit between the first and second pins; and a load circuit coupled to the power converter IC package.

[0003] Other aspects of this disclosure provide a pin short-circuit detection circuit. In some examples, the pin short-circuit detection circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, the first gate terminal being coupled to an input voltage terminal, and the first source terminal being coupled to a first output node of the circuit via a plurality of bias transistors. The circuit includes a resistor coupled to the first gate terminal and the first source terminal; a second transistor having a second gate terminal coupled to the first drain terminal, a second source terminal coupled to a first node of the circuit, and a second drain terminal coupled to a second output node of the circuit. The circuit includes a first bias transistor coupled to the first node and the first drain terminal of the circuit; and a second bias transistor coupled to the first and second output nodes.

[0004] Other aspects of this disclosure provide a power converter integrated circuit (IC) package. In some examples, the power converter IC package includes a power transistor; and a pin short-circuit detection circuit coupled to the power transistor and including: a first transistor configured to compare first and second signals, the first signal being based on a signal received at a first pin of the package, and the second signal being based on a signal received at a second pin of the package; and a second transistor configured to provide an output signal having either a first state or a second state based on the comparison. The first state indicates a primary operating mode, and the second state indicates a pin short-circuit operating mode. The power transistor will operate using the output signal. Attached Figure Description

[0005] For detailed explanations of the various examples, please now refer to the accompanying drawings, in which:

[0006] Figure 1 Power converter integrated circuit (IC) packages included in electronic devices according to various examples are depicted.

[0007] Figure 2 Schematic diagrams of power converter IC packages including pin short-circuit detection circuits according to various examples are depicted.

[0008] Figure 3 Schematic diagrams of pin short-circuit detection circuits based on various examples are depicted.

[0009] Figure 4 Schematic diagrams of power converter IC packages including pin short-circuit detection circuits according to various examples are depicted.

[0010] Figure 5 Timing diagrams depicting the operation of pin short-circuit detection circuits according to various examples are provided.

[0011] Figure 6 Schematic diagrams of power converter IC packages including pin short-circuit detection circuits according to various examples are depicted.

[0012] Figure 7 Schematic diagrams of power converter IC packages including pin short-circuit detection circuits according to various examples are depicted.

[0013] Figure 8 Timing diagrams depicting the operation of pin short-circuit detection circuits according to various examples are provided.

[0014] Figure 9 A flowchart depicts the operation of a pin short-circuit detection circuit of a power converter IC package during the main operating mode, according to various examples.

[0015] Figure 10 A flowchart depicts the operation of a pin short-circuit detection circuit in a power converter IC package during pin short-circuit operation mode, according to various examples. Detailed Implementation

[0016] As mentioned above, package pin layouts vary. Some pin layouts are susceptible to electrical short circuits between pins. For example, some power converter integrated circuit (IC) packages include input voltage pins, input ground pins, and output voltage pins, and in some such packages, the output voltage pin may be prone to short-circuiting with the input voltage pins or input ground pins. Besides causing electrical damage to the package, such short circuits can also lead to smoke or fire, posing both a safety hazard and a threat to the electronic equipment containing the package. Current solutions for mitigating the harmful effects of pin short circuits on power converter IC packages include adding fuses to the system, such as adding fuses to the PCB on which the power converter IC package is mounted. When a short circuit occurs between package pins, the fuse trips, preventing smoke and fire and mitigating electrical damage. However, fuses occupy significant space on the PCB and result in undesirable high costs.

[0017] Therefore, this document describes various examples of power converter IC packages that include pin short-circuit detection circuitry to overcome the aforementioned challenges. Implementing the pin short-circuit detection circuitry described in this disclosure enables the power converter IC package to detect short circuits between its pins and, in response to the short-circuit detection, shut down the package (e.g., stop power supply). Because the power converter IC package described herein includes pin short-circuit detection circuitry capable of detecting short circuits between the package's pins, the aforementioned fuses can be omitted, resulting in significant savings in PCB space and cost. Furthermore, including the pin short-circuit detection circuitry within the power converter IC package does not require changing the form factor of the power converter IC package. Moreover, although the examples below are described in the context of power converter IC packages, the pin short-circuit detection circuitry is not limited to its application in power converter IC packages. Rather, the pin short-circuit detection circuitry can be implemented in any of a variety of packages susceptible to pin short circuits. An illustrative power converter IC package including an example pin short-circuit detection circuitry will now be described in detail with reference to the accompanying drawings.

[0018] Figure 1 A power converter integrated circuit (IC) package 206 is depicted included within an electronic device 100, which can be any type of electronic device (e.g., handheld communication device, medical device, consumer electronics, sensor, etc.). The following paragraphs describe examples of different circuits included in the electronic device 100, such as power converters. These circuits can be housed in packages comprising multiple pins to facilitate electrical communication between circuits housed within the package and circuits outside the package. An example illustrates a pin short-circuit detection circuit housed within the package for detecting short circuits between the package's pins. Specific technical advantages arising from these pin short-circuit detection circuits are also described, such as significant savings in PCB space, reduced smoke and fire hazards, and reduced electrical damage.

[0019] In some examples, electronic device 100 includes a PCB 102, which includes a Vs path 200 (also referred to as an input voltage terminal), a power converter IC package 206 coupled to the Vs path 200, and an additional circuit system 208 configured to receive power from the power converter IC package 206. The power converter IC package 206 includes any suitable type of power converter, such as a buck converter, boost converter, or buck-boost converter. The additional circuit system 208 includes any circuitry that can benefit from the output of the power converter. In some examples, the additional circuit system 208 is a load circuit. PCB 102 also includes a GND (ground) path 204. Although... Figure 1 The depicted power converter IC package 206 has six pins, but the scope of this disclosure is not limited to a six-pin package. Instead, the aforementioned pin short-circuit detection circuitry can be implemented in any of a variety of packages, such as eight-pin or ten-pin packages, without changing the package's form factor. For illustrative purposes, the following discussion will focus on a six-pin power converter package, and it should be understood that the principles described herein are extendable to virtually any type of package.

[0020] An example lacking a fuse between the power converter IC package 206 and the Vs path 200 is a fuse-free example, meaning that the power converter IC package 206 and the Vs path 200 are coupled to each other without a fuse. In some such fuse-free examples, the coupling between the power converter IC package 206 and the Vs path 200 is direct coupling, where there are no intervening electrical components (e.g., fuses, resistors, capacitors, inductors, transistors, etc.) that substantially alter or could substantially alter the functional relationship between the power converter IC package 206 and the Vs path 200.

[0021] The power converter IC package 206 has the following pins: a VIN pin 216 directly coupled to Vs path 200; a GND pin 212 coupled to ground path 204; an output SW pin 214 coupled to additional circuitry 208 and configured to provide output power to additional circuitry 208; and an input CB pin 210 coupled to SW pin 214 via capacitor 202. In some examples, capacitor 202 is placed on PCB 102. However, in other examples, capacitor 202 is located outside the electronics 100 and coupled to SW pin 214 and CB pin 210 via metal traces or paths on PCB 102. The remainder of this discussion assumes that capacitor 202 is coupled to the power converter IC package 206 on PCB 102 inside the electronics 100. The remaining two pins, PIN3 218 and PIN4 220, can be configured to provide additional inputs or outputs to the circuitry as needed.

[0022] In a further example, the power converter IC package 206 is configured to detect short circuits between the first and second pins of the power converter IC package 206. For example, due to design considerations such as the need to minimize electromagnetic interference, metallization resistance, and / or parasitic inductance, the VIN pin 216 and SW pin 214, or the SW pin 214 and GND pin 212, may be directly adjacent to each other, creating the possibility of a short circuit between the VIN pin 216 and SW pin 214, or between the SW pin 214 and GND pin 212. The pin short-circuit detection circuitry within the power converter IC package 206 is capable of detecting such short circuits to take remedial measures as described below, thereby eliminating any need for expensive, space-consuming fuses.

[0023] Figure 2 A schematic diagram depicts the contents of a power converter IC package 206 according to various examples. In some examples, the power converter IC package 206 includes a blanking circuit 332, a pin short-circuit detection circuit 330, a NOR gate 310, a D flip-flop 314, a buffer 316, a high-side field-effect transistor (FET) 320, and a low-side FET 322. The blanking circuit 332 can be any circuit designed to reduce noise in the received signal 334, such as a pulse width modulation (PWM) or time control (COT) signal. See below for reference. Figure 3 Illustrative details are provided regarding the pin short-circuit detection circuit 330. Furthermore, although the power converter IC package 206 depicts a NOR gate 310 and a D flip-flop 314, the power converter IC package 206 can utilize any electronic circuit that performs equivalent functions to the NOR gate 310 and the D flip-flop 314, as described below. Figure 4 The discussion.

[0024] In some examples, FETs 320 and 322 are metal-oxide-semiconductor field-effect transistors (MOSFETs). In one example, FETs 320 and 322 are n-channel MOSFETs (nMOSFETs or NMOS). In another example, FETs 320 and 322 are high-voltage FETs. The gate terminal 320G of the high-side FET 320 is coupled to the feedback path 319 of the output path 318 of the buffer 316 to the pin short-circuit detection circuit 330, which carries the signal hsfg. The drain terminal 320D of the high-side FET 320 is coupled to the VIN path 300, which in turn is coupled to the power converter IC package 206. Figure 1The drain terminal 320D receives the voltage signal VIN from Vs along the Vs path 200. The source terminal 320S of the high-side FET 320 is coupled to the SW path 326, which in turn is coupled to the SW pin 214 of the power converter IC package 206. In this way, the SW path 326 carries the signal SW. The drain terminal 322D of the low-side FET 322 is also coupled to the SW path 326. Since the operation of FETs 320 and 322 provides the signal SW at the output of the SW pin 214, each FET is referred to as a power transistor. The source terminal 322S of the low-side FET 322 is coupled to the GND path 324, which in turn is coupled to the GND pin 212 of the power converter IC package 206. Although Figure 2 The circuitry for driving the gate terminal 322G of the low-side FET 322 is not depicted, but Figure 6 An illustrative circuit for driving the gate terminal 322G is depicted.

[0025] The pin short-circuit detection circuit 330 includes multiple input paths, including VIN path 300 (carrying the voltage signal VIN), SW path 326 (carrying the signal SW), feedback path 319 (carrying the signal hsfg), and bootstrap capacitor path 328 (carrying the signal CB). The bootstrap capacitor or CB path 328 is coupled to the power converter IC package 206. Figure 1 The CB pin 210 of the circuit. The pin short-circuit detection circuit 330 has an output path 308 carrying the signal det_out.

[0026] In some examples, the output paths 308 and 306 of the blanking circuit 332 are coupled to the input of the NOR gate 310. The output path 312 of the NOR gate 310 is coupled to the reset input of the D flip-flop 314. The D flip-flop 314 also receives the clock signal Clk on the Clk path 304 and the voltage bias (VBIAS) on the VBIAS path 302, serving as the clock and set or D input, respectively. The output path 336 of the D flip-flop 314 is coupled to the input of the buffer 316. As previously described, the output path 318 of the buffer 316 is coupled to the gate terminal 320G of the high-side FET 320 and to the feedback path 319 of the pin short-circuit detection circuit 330. The operation of the power converter IC package 206 will now be described for the pin short-circuit operating mode and the main or normal operating mode.

[0027] In use Figure 2 In one example of the circuit, when SW pin 214 and GND pin 212 ( Figure 1When a pin short circuit occurs between the two pins, the pin short circuit detection circuit 330 asserts the signal det_out on the output path 308 as high. (As mentioned before, refer to the following...) Figure 3 The structure and function of the pin short-circuit detection circuit 330 are provided. Because the signal det_out is high, the signal on the output path 312 of the NOR gate 310 is low. When the reset input of the D flip-flop 314 receives a low signal, the signal on the output path 336 of the D flip-flop 314 is set low, regardless of the other inputs of the D flip-flop 314. (See below for details.) Figure 4 The structural and functional details of the operation of the D flip-flop 314 are provided. If the signal on output path 336 is low, the signal hsfg is also low after passing through buffer 316. The low signal at the gate terminal 320G of the high-side FET 320 turns off the high-side FET 320. As a result of the high-side FET 320 being off, no signal SW is transmitted along SW path 326 to the SW pin 214 of the power converter IC package 206. This is referred to as the pin-short operating mode.

[0028] In use Figure 2 In another example of the circuit, no pin short circuit occurs between SW pin 214 and GND pin 212. In this case, the signal det_out on output path 308 is not asserted as high. The signal on output path 312 of the NOR gate 310 is controlled by blanking circuit 332. More specifically, if blanking circuit 332 outputs a low signal, the signal on output path 312 is high, and therefore the high-side FET 320 is controlled according to the clock signal on Clk path 304. If blanking circuit 332 outputs a high signal, the signal on output path 312 is low, and therefore the high-side FET 320 is turned off. Specific timing and operational details of blanking circuit 332 can be implemented as needed to achieve specific performance or noise cancellation targets. When the operation of the power transistor is controlled by the clock signal on Clk path 304 or blanking circuit 332, this operation is referred to as the normal operating mode (and occasionally as the main operating mode herein).

[0029] In this discussion, although the signal det_out is asserted as high when the pin short-circuit detection circuit 330 detects a pin short-circuit event, the signal det_out can also be asserted as low when the pin short-circuit detection circuit 330 detects a pin short-circuit event, provided that the subsequent logic circuit system represented by the NOR gate 310 and the D flip-flop 314 is adjusted accordingly, as follows regarding... Figure 4As discussed above, when the pin short-circuit detection circuit 330 detects a pin short-circuit event, this state is referred to as the pin short-circuit operating mode, regardless of whether the signal det_out is asserted as high or low. In some examples, in response to the signal det_out indicating the pin short-circuit operating mode, the signal hsfg is driven low, which in turn turns off the high-side FET 320. The ability of the pin short-circuit detection circuit 330 to turn off the high-side FET 320 during a pin short-circuit event reduces the likelihood of smoke and fire and stops the propagation of the signal SW, advantageously helping to mitigate electrical damage to the circuit system without the need for fuses.

[0030] Figure 3 Schematic diagrams of pin short-circuit detection circuits 330 according to various examples are depicted. In some examples, the pin short-circuit detection circuit 330 includes transistors 404, 406, 408, 410, 426, 430, 432, and 434, and a resistor 422. In some examples, transistors 404, 406, 408, 410, 426, 430, 432, and 434 are FETs. In further examples, transistors 404, 410, 426, 430, 432, and 434 are nMOSFETs or NMOS, and transistors 406 and 408 are p-channel MOSFETs (pMOSFETs or PMOS). In further examples, transistors 404 and 426 are high-voltage FETs.

[0031] Pin short-circuit detection circuit 330 includes multiple input paths. VIN path 300 is coupled to power converter IC package 206. Figure 1 The VIN pin 216 of the power converter IC package 206 carries the voltage signal VIN. CB path 328 is coupled to the CB pin 210 of the power converter IC package 206 and carries the signal CB( Figure 1 Feedback path 319 is coupled to output path 318 of buffer 316 and high-side FET 320. Figure 2 The gate terminal 320G of the SW terminal carries the signal hsfg. SW path 326 is coupled to SW pin 214. Figure 1 The high-side FET 320 has a source terminal 320S and the low-side FET 322 has a drain terminal 322D, and it carries the signal SW. Figure 2 Path 414 carries the vbiasP voltage. Path 436 carries the vbiasN voltage. (As mentioned above...) Figure 2 The pin short-circuit detection circuit 330 includes an output path 308 carrying the signal det_out.

[0032] Transistor 404 includes a drain terminal 404D, a gate terminal 404G, and a source terminal 404S. The drain terminal 404D is coupled to VIN path 300. The gate terminal 404G is coupled to CB path 328. The source terminal 404S is coupled to vinsen path 420 carrying the signal vinsen.

[0033] Transistor 410 includes a drain terminal 410D, a gate terminal 410G, and a source terminal 41. Gate terminal 410G is coupled to vinsen path 420, source terminal 404S of transistor 404, and a first terminal of resistor 422. Drain terminal 410D (referred to herein as the non-control terminal) is coupled to det_in path 416 carrying the signal det_in. Source terminal 410S is coupled to swsen path 424 carrying the signal swsen, and is also coupled to a second terminal of resistor 422. Resistor 422 may be any resistance value sufficient to prevent transistor 410 from accidentally turning on, for example, due to noise or parasitic capacitance.

[0034] Transistor 426 has a drain terminal 426D, a gate terminal 426G, and a source terminal 426S. Feedback path 319 is coupled to the gate terminal 426G and the gate terminal 320G of the high-side FET 320. Drain terminal 426D is coupled to Swsen path 424, the source terminal 410 of transistor 410, and the second terminal of resistor 422. Source terminal 426S is coupled to the drain terminal 430D and the gate terminal 430G of transistor 430. (Drain terminal 430D and gate terminal 430G are also coupled to each other.) Source terminal 430S of transistor 430 is coupled to the drain terminal 432D and the gate terminal 432G of transistor 432. (The drain terminal 432D and the gate terminal 432G are also coupled to each other.) The source terminal 432S of transistor 432 is coupled to SW path 326 carrying signal SW, which is used as the basis for signal swsen when comparing signals vinsen and swsen, as described above and in detail below.

[0035] Transistor 406 includes a drain terminal 406D, a gate terminal 406G, and a source terminal 406S. CB path 328 is coupled to the source terminal 406S. Gate terminal 406G is coupled to path 414 carrying the vbiasP voltage. Drain terminal 406D is coupled to det_in path 416 carrying the det_in signal and the drain terminal 410D of transistor 410.

[0036] Transistor 408 includes a drain terminal 408D, a gate terminal 408G, and a source terminal 408S. The source terminal 408S is coupled to CB path 328. The gate terminal 408G is coupled to the det_in path 416 carrying the det_in signal, the drain terminal 410D of transistor 410, and the drain terminal 406D of transistor 406. The drain terminal 408D is coupled to the output path 308 carrying the det_out signal.

[0037] Transistor 434 includes a drain terminal 434D, a gate terminal 434G, and a source terminal 434S. The drain terminal 434D is coupled to the output path 308 carrying the signal det_out and the drain terminal 408D of transistor 408. The gate terminal 434G is coupled to the path 436 carrying the vbiasN voltage. The source terminal 434S is coupled to the SW path 326 and the source terminal 432S of transistor 432. (As described in the description...) Figure 2 Similarly, although Figure 3 The input circuitry for driving the gate terminal 322G of the low-side FET 322 is not depicted, but refer to the following... Figure 6 An illustrative circuit is provided for driving the gate terminal 322G.

[0038] In one example of the operation of the pin short-circuit detection circuit 330, there is no pin short circuit between SW pin 214 and GND pin 212, so the power converter IC package 206 operates in normal (or primary) operating mode. In this mode, the switching of the high-side FET 320 is driven by a clock signal on the Clk path 304. When the high-side FET 320 is turned on, the signal SW is pulled up to approximate the voltage signal VIN. With the gate terminal 432G coupled to the drain terminal 432D, the transistor 432 behaves as a diode-connected transistor, and the drain-source voltage (VDS) is equivalent to the voltage threshold (VT) of the transistor 432. Therefore, the signal SW is amplified or increases the VT of the transistor 432 at the drain terminal 432D. Similarly, since the gate terminal 430G and drain terminal 430D of transistor 430 are coupled, the voltage at drain terminal 430D increases the voltage at drain terminal 432D, which in turn increases the VT of transistor 430. This results in the amplified signal SW at drain terminal 430D being the original signal SW on SW path 326 plus the VT of transistor 432 plus the VT of transistor 430. In this way, transistors 430 and 432 can be considered as multiple bias transistors configured to amplify the signal SW. When the high-side FET 320 is operating normally, the signal hsfg coupled to the gate terminal 320G of the high-side FET 320 is high enough to turn on transistor 426. The amplified signal SW propagates through transistor 426, therefore the signal swsen at swsen path 424 is the amplified signal SW present at drain terminal 430D.

[0039] Furthermore, since the signal SW is pulled up to the voltage signal VIN when the high-side FET 320 is turned on, the voltage of the signal CB (signal SW plus the voltage coupled to the CB pin 210 and the SW pin 214) is also applied. Figure 1The voltage across the bootstrap capacitor 202 is pulled up to the voltage signal VIN. The gate terminal 404G, driven by the signal CB, turns on transistor 404, and the voltage signal VIN propagates through transistor 404, making the signal vinsen on the vinsen path 420 approximate the voltage signal VIN. For transistor 410 to turn on, the voltage at the gate terminal 410G should exceed the voltage at the source terminal 410S by an amount equal to the threshold voltage (VT) of transistor 410. Because the voltage at the gate terminal 410G is the voltage signal VIN, and the voltage of the signal swsen at the source terminal 410S is the amplified signal SW, and because the original signal SW on the SW path 326 approximates the voltage signal VIN, the amount by which the voltage at the gate terminal 410G exceeds the voltage at the source terminal 410S does not exceed VT, and transistor 410 is turned off. In this way, transistor 410 effectively acts as a comparator that compares signals vinsen and swsen and turns them on or off based on the comparison, thereby affecting the state of signal det_in (and ultimately affecting signal det_out), as described below.

[0040] When transistor 410 is off, the signal det_in is determined by transistor 406. Path 414 carries the voltage vbiasP to drive the gate terminal 406G of transistor 406. Since transistor 406 is a p-channel MOSFET in some examples, vbiasP should be at least VT lower than the signal CB of transistor 406 in order for bias current (lb) 412 to flow through transistor 406. Therefore, in some examples, vbiasP is fixed at a voltage low enough to keep transistor 406 on. When transistor 406 is on, the signal det_in on path 416 is approximately equal to a high level signal CB. Since transistor 408 is also a p-channel MOSFET in some examples, the voltage at gate terminal 408G should be at least VT lower than the voltage at source terminal 408S in order for transistor 408 to be on. Since the voltage at gate terminal 408G and the voltage at source terminal 408S are equal to the signal CB, transistor 408 is off.

[0041] When transistor 408 is off, the signal det_out on output path 308 is determined by transistor 434. Path 436 carries the vbiasN voltage to drive the gate terminal 434G of transistor 434. Since transistor 434 is an n-channel MOSFET in some examples, vbiasN should be at least higher than the signal SW by the VT of transistor 434 in order for bias current (lb) 412 to flow through transistor 434. Therefore, in some examples, vbiasN is fixed at a voltage high enough to keep transistor 434 on. When transistor 434 is on, the signal det_out on output path 308 is pulled low because transistor 408 is off. The low signal det_out indicates that there is no pin short between SW pin 214 and GND pin 212. When in main (or normal) operating mode, if the high-side FET 320 is based on the clock signal on Clk path 304 or blanking circuit 332 ( Figure 2 If the transistor is turned off during the operation of ), the transistor 410 remains off because the signal swsen is higher than the signal vinsen, so the signal det_out on the output path 308 remains low.

[0042] As described above, transistors 406 and 434 should remain on to allow the pin short-circuit detection circuit 330 to generate the signal det_out. Therefore, vbiasP should be calculated as being at least lower than the VT of transistor 406 than the signal CB, and vbiasN should be calculated as being at least higher than the VT of transistor 434 than the signal SW. Since transistors 406 and 434 are useful for the operation of the circuit and are driven by bias voltages to the gate terminals 406G and 434G respectively, each transistor will be referred to herein as a bias transistor. Bias transistor 406 provides a first bias current based on the signal det_in to control the operation of transistor 408. Bias transistor 434 provides a second bias current based on the signal det_in to drive the signal det_out.

[0043] In another example of the operation of the pin short-circuit detection circuit 330, a pin short circuit exists between SW pin 214 and GND pin 212 (pin short-circuit operation mode). When the high-side FET 320 is turned on by the clock signal on the Clk path 304, the signal SW is not pulled up to the voltage signal VIN due to the short circuit from SW pin 214 to GND pin 212. As explained in the previous example, transistors 430 and 432 operate as diode-connected transistors, and VDS is equal to the VT of transistors 430 and 432, respectively. Because the signal SW is pulled to GND, the voltage at the drain terminal 432D is approximately equal to the VT of transistor 432. The voltage at the drain terminal 430D is approximately equal to the VT of transistor 432 plus the VT of transistor 430. When the high-side FET 320 is turned on, the signal hsfg coupled to the gate terminal 320G of the high-side FET 320 is high enough to turn on transistor 426. The amplified signal SW propagates through transistor 426, so the signal swsen on the swsen path 424 is approximately the voltage at the drain terminal 430D.

[0044] The signal CB is equivalent to the voltage of the signal SW plus the voltage across the bootstrap capacitor 202 coupled between the CB pin 210 and the SW pin 214. Since the signal SW is pulled down to GND when the high-side FET 320 is on, the signal SW is zero volts, and therefore the signal CB is the voltage across the bootstrap capacitor 202 (…). Figure 1 The voltage across the gate terminal 404G is driven by signal CB, which operates transistor 404 in the saturation region, and the signal vinsen on vinsen path 420 is approximately equal to CB minus the VT of transistor 404. As discussed in the previous example, for transistor 410 to turn on, the voltage of signal vinsen should exceed the voltage of signal swsen by an amount equal to the VT of transistor 410. Since the voltage at gate terminal 410G is CB minus the VT of transistor 404, and the signal swsen at source terminal 410S is the sum of the VTs of transistors 430 and 432, the voltage at gate terminal 410G is greater than the voltage at source terminal 410S, and transistor 410 turns on.

[0045] With transistor 410 turned on, the signal det_in is determined by the drain voltage 410D of transistor 410, or by the signal vinsen minus the signal swsen minus the VT of transistor 410. Although the signal det_in is pulled high, this value is less than the signal CB (CB minus the sum of the VT of transistor 404 and the VT of transistors 430 and 432). As described in the previous example, since transistor 408 is a p-channel MOSFET, in order for transistor 408 to turn on, the voltage at the gate terminal 408G should be at least lower than the voltage at the source terminal 408S (i.e., the voltage of signal CB) than the VT of transistor 408. Since the voltage at the gate terminal 408G is less than the signal CB, transistor 408 is turned on. With transistor 408 turned on, the signal det_out on output path 308 is determined by the voltage at the drain terminal of transistor 408, therefore the signal det_out is pulled high to indicate that a pin short circuit has been detected.

[0046] As described above, transistor 410 generates a signal det_in by comparing signals vinsen and swsen. Based on the value of signal det_in, transistor 408 is turned on or off; therefore, the signal det_in at the non-control terminal 410D of transistor 410 is referred to as the reference signal. Furthermore, the value of the reference signal can be described as having a first state indicating the primary operating mode or a second state indicating a pin-short-circuit operating mode. Then, the signal det_out is determined by the reference signal, as it controls the operation of transistor 408. The value of the output signal det_out also has either a first state indicating the primary operating mode or a second state indicating a pin-short-circuit operating mode.

[0047] Figure 4 A schematic diagram of a power converter IC package 206 including a pin short-circuit detection circuit 330 is depicted according to various examples. In some examples, the power converter IC package 206 includes a blanking circuit 332, a NOR gate 310, a D flip-flop 314, a buffer 316, a pin short-circuit detection circuit 330, a high-side FET 320, and a low-side FET 322. Figure 2 In a further example, the D flip-flop 314 includes an inverter 524, an AND gate 500, an AND gate 502, a NOR gate 504, a NOR gate 506, and an AND gate 530. In some examples, the buffer 316 includes transistors 516, 518, 520, and 522. In a further example, transistors 518 and 522 are pMOSFETs or PMOS, and FETs 516 and 520 are nMOSFETs or NMOS. Although Figure 4 The circuitry for driving the low-side FET 322 is not depicted, but Figure 6An illustrative circuit for driving the low-side FET 322 is depicted.

[0048] The power converter IC package 206 includes multiple paths. Path 306 couples the output from the blanking circuit 332 to the NOR gate 310. Figure 2 The input of the NOR gate 310 is coupled to the input of the AND gate 530. Output path 308 carries the signal det_out from the pin short-circuit detection circuit 330 and is coupled to the input of the NOR gate 310. Output path 312 couples the output of the NOR gate 310 to the input of the AND gate 530. VBIAS path 302 carries the voltage bias VBIAS and is coupled to the input of the inverter 524 and the AND gate 500. Path 526 couples the output of the inverter 524 to the input of the AND gate 502. CLK path 304 carries the clock signal and is coupled to the input of the AND gate 500 and the AND gate 502. Path 508 couples the output of the AND gate 500 to the input of the NOR gate 504. Path 510 couples the output of the AND gate 502 to the input of the NOR gate 506. Path 514 couples the output of the NOR gate 504 to the input of the NOR gate 506. Path 528 couples the output of the NOR gate 506 to the input of the AND gate 530. Output path 336 couples the output from AND gate 530 to the input of NOR gate 504 and the shared input of transistors 516 and 518, which are configured as the first inverter of buffer 316. Path 532 couples the output of the first inverter of buffer 316 to the shared input of transistors 520 and 522, which are configured as the second inverter of buffer 316. Output path 318 carries the signal hsfg and couples the output of the second inverter of buffer 316 to feedback path 319 and high-side FET 320.

[0049] Now described as follows Figure 4 The operation of the power converter IC package 206 shown is illustrated. In use... Figure 4 In some examples of the circuit, VBIAS is high (and in some examples, remains high during both the primary operating mode and the pin-short operating mode), and the clock signal is high. Path 508 carries a high signal when both inputs to AND gate 500 are high. A high signal as an input to NOR gate 504 causes path 514 to carry a low signal. The signal on path 526 is low when a high VBIAS input is to inverter 524. The signal on path 510 is low when a high clock signal and a low signal on path 526 are inputs to AND gate 502. The signal on path 528 is high when the low signals carried on paths 510 and 514 are inputs to NOR gate 506.

[0050] Now assume that the pin short-circuit detection circuit 330 detects a short circuit from SW pin 214 to GND pin 212 and asserts the signal det_out high on output path 308. When the input signal of NOR gate 310 (e.g., the signal det_out) is high, the signal on output path 312 is low. When the input signal of AND gate 530 (e.g., the signal on output path 312) is low, the output signal on output path 336 is low. In this way, the output signal on output path 312 can be considered as a low-level reset driving D flip-flop 314. Buffer 316 receives the low signal on output path 336. Since transistors 518, 516 are configured to invert the low signal on output path 336, the signal on path 532 is high. Transistors 522, 520 are configured to invert the signal on path 532, so the signal hsfg on output path 318 is low. (See also: ...) Figure 2 As discussed, the low signal hsfg turns off the high-side FET 320 and stops the transmission of the signal SW along SW path 326 to the SW pin 214 of the power converter IC package 206. This is referred to as the pin-short-circuit operation mode. The ability of the pin-short-circuit detection circuit 330 to stop the transmission of the signal SW during the pin-short-circuit operation mode is technically advantageous because it reduces the safety hazards of smoke and fire and helps to mitigate electrical damage to the circuit system.

[0051] In use Figure 4 In another example of the circuit, no pin short occurs between SW pin 214 and GND pin 212. In this case, the signal det_out is not asserted as high. Therefore, the signal on output path 312 will be controlled by blanking circuit 332. More specifically, when blanking circuit 332 outputs a low signal, the signal on output path 312 is high, so the high-side FET 320 is controlled according to the clock input of D flip-flop 314. When blanking circuit 332 outputs a high signal, the signal on output path 312 is low, so AND gate 530 is driven low, which in turn turns off high-side FET 320. As mentioned above... Figure 2 The specific timing and operational details of the blanking circuit 332 discussed herein can be implemented as needed to achieve specific performance or noise reduction goals.

[0052] As discussed above Figure 2As described above, although in some examples the signal det_out is asserted as high when the pin short-circuit detection circuit 330 detects a pin short-circuit event, the signal det_out can also be asserted as low when the pin short-circuit detection circuit 330 detects a pin short-circuit event, provided that the subsequent logic circuitry represented by the NOR gate 310 and the D flip-flop 314 is adjusted accordingly. For example, if the signal det_out is asserted as low, then the signal det_out can be the input of an inverter whose output is the input of the NOR gate 310. This configuration should achieve the same effect as described above. Figure 4 The same output as described in the example.

[0053] Figure 5 Timing diagrams depicting the operation of the pin short-circuit detection circuit 330 according to various examples are provided. SW waveform 604 corresponds to SW path 326 ( Figure 2 The voltage signal SW on the high-side FET 320 is represented by the following waveforms: hsvgs-sw waveform 606 corresponds to the gate-to-source voltage (VGS) signal on the high-side FET 320; detout-sw waveform 608 corresponds to the voltage signal on the output path 308; swsen-sw waveform 610 corresponds to the voltage signal on the swsen path 424; and vinsen-sw waveform 612 corresponds to the voltage signal on the vinsen path 420. Since the signal det_out is determined by comparing the signals vinsen and swsen, these two waveforms are presented on the same axis, with swsen-sw waveform 610 represented by a solid line and vinsen-sw waveform 612 represented by a dashed line.

[0054] refer to Figure 5 waveform and Figure 3 and Figure 4Initially, the power converter IC package 206 is in the primary operating mode, as shown in figure 600, where there is no pin short between SW pin 214 and GND pin 212. In primary or normal operation 600, the clock signal on Clk path 304 drives the signal hsfg high, which turns on the high-side FET 320 for a fixed time interval, approximately 150 nanoseconds in this example. For the high signal hsfg to turn on the high-side FET 320, the VG of the high-side FET 320 (approximately 5.5V in this example) should exceed the high-side FET 320 by an amount of VT. With the high-side FET 320 on, the voltage signal SW corresponds to the voltage signal on VIN path 300, or approximately 20V in this example. As SW is pulled to VIN, the signal vinsen should be approximately equal to or lower than the signal swsen, causing the comparator transistor 410 to turn off. In this example, the swsen-sw waveform 610 and vinsen-sw waveform 612 indicate that the signals swsen and vinsen are nearly identical, or that vinsen is slightly lower than swsen, indicating that transistor 410 is turned off. As transistor 410 turns off, the signal det_out on the output path 308 of the pin-short-circuit detection circuit 330 is low, as shown in the detout-sw waveform 608. (Although there is a brief spike in the detout-sw waveform near the 300 nanosecond mark, the high-side FET 320 has already turned off, as shown in the hsvgs-sw waveform 606. The brief spike is caused by parasitic capacitance.)

[0055] Still referencing Figure 5 waveform and Figure 3 and Figure 4 When a short circuit occurs between SW pin 214 and GND pin 212, the signal SW on output path 326 is low, as indicated by the negligible voltage represented by number 602 in this example. Despite the short circuit, the high-side FET 320 will still attempt to turn on due to the initial clock signal driving the signal hsfg, as indicated by the spike in the hsvgs-sw waveform 606. However, when the signal SW is pulled to GND, the signal vinsen exceeds the signal swsen, as indicated at approximately 450 nanoseconds. This difference is large enough to turn on the comparator transistor 410. As transistor 410 turns on, the signal det_out goes high, as indicated by the time interval immediately following the 450 nanoseconds. The high signal det_out drives the signal hsfg low, which turns off the high-side FET 320 with a negligible delay. The shortest on-time of the high-side FET 320 during a pin short-circuit event reduces the safety hazards of smoke and fire and helps mitigate electrical damage to the circuit system.

[0056] Figure 6A schematic diagram depicts the contents of a power converter IC package 206 according to various examples. In some examples, the power converter IC package 206 includes a blanking circuit 732, a pin short-circuit detection circuit 730, a NOR gate 710, a D flip-flop 714, a buffer 716, a high-side FET 320, and a low-side FET 322. (As mentioned above...) Figure 2 The blanking circuit 732 can be any circuit designed to reduce noise in the received signal 734. See below. Figure 7 Illustrative details regarding the contents and function of the pin short-circuit detection circuit 730 are provided. Furthermore, although the power converter IC package 206 depicts a NOR gate 710 and a D flip-flop 714, the power converter IC package 206 can utilize any electronic circuit that performs equivalent functions to the NOR gate 710 and the D flip-flop 714, as described below. Figure 7 The discussion.

[0057] In some examples, the gate terminal 322G of the low-side FET 322 is coupled to the output path 718 of the buffer 716 carrying the signal Isfg and the feedback path 719 of the pin short-circuit detection circuit 730. The drain terminal 322D of the low-side FET 322 is coupled to the SW path 326, which in turn is coupled to the power converter IC package 206. Figure 1 The drain terminal 322D receives the voltage signal SW along the SW path 326. The source terminal 322S of the low-side FET 322 is coupled to the GND path 324, which in turn is coupled to the power converter IC package 206. Figure 1 The GND pin 212 of the high-side FET 320 is connected to the SW path 326. In this way, the GND path 324 carries the signal GND. The source terminal 320S of the high-side FET 320 is also coupled to the SW path 326. The drain terminal 320D of the high-side FET 320 is coupled to the VIN path 300, which in turn is coupled to the VIN pin 216 of the power converter IC package 206. Although... Figure 6 The circuitry for driving the gate terminal 320G of the high-side FET 320 is not depicted, but Figure 2 An illustrative circuit for driving the gate terminal 320G is depicted.

[0058] The pin short-circuit detection circuit 730 includes multiple input paths, including GND path 324 (carrying signal GND), SW path 326 (carrying signal SW), feedback path 719 (carrying signal Isfg), and CB path 328 (carrying signal CB). CB path 328 is coupled to the power converter IC package 206. Figure 1 The CB pin 210 of the circuit. The pin short-circuit detection circuit 730 has an output path 708 carrying the signal Isdet_out.

[0059] In some examples, output paths 708 and 706 of the blanking circuit 732 are coupled to the inputs of the NOR gate 710. Output path 712 of the NOR gate 710 is coupled to the reset input of the D flip-flop 714. The D flip-flop 714 also receives the clock signal Clk on the Clk path 704 and the voltage bias (VBIAS) on the VBIAS path 702, serving as the clock and set or D input, respectively. Output path 736 of the D flip-flop 714 is coupled to the input of the buffer 716. As previously described, output path 718 of the buffer 716 is coupled to the gate terminal 322G of the low-side FET 322 and the feedback path 719 of the pin short-circuit detection circuit 730.

[0060] In use Figure 6 In one example of the circuit, when a pin short circuit occurs between SW pin 214 and VIN pin 216, the pin short circuit detection circuit 730 asserts the signal Isdet_out as high. (As mentioned earlier, see below for reference.) Figure 7 The structure and function of the pin short-circuit detection circuit 730 are provided. Because the signal Isdet_out is high, the signal on the output path 712 of the NOR gate 710 is low. When the reset input of the D flip-flop 714 receives a low signal, the signal on the output path 736 of the D flip-flop 714 is set low, regardless of the other inputs of the D flip-flop 714. (See below for details.) Figure 7 The structural and functional details of the operation of the D flip-flop 714 are provided. If the signal on output path 736 is low, the signal Isfg is also low after passing through buffer 716. The low signal at gate terminal 322G turns off the low-side FET 322. As a result of the low-side FET 322 being off, the signal SW is not transmitted along SW path 326 to the SW pin 214 of the power converter IC package 206, thereby advantageously preventing smoke and fire and mitigating damage to the circuit system. This is the pin-short-circuit operation mode.

[0061] In use Figure 6In another example of the circuit, there is no pin short between SW pin 214 and VIN pin 216. In this case, the signal Isdet_out will not be asserted as high. The signal on the output path 712 of the NOR gate 710 will be controlled by the blanking circuit 732. More specifically, if the blanking circuit 732 outputs a low signal, the signal on the output path 712 is high, thus controlling the low-side FET 322 according to the clock signal on the Clk path 704. When the blanking circuit 732 outputs a high signal, the signal on the output path 712 is low, thus turning off the low-side FET 322. Specific timing and operational details of the blanking circuit 732 can be implemented as needed to achieve specific performance or noise cancellation targets. When the operation of the power transistor is controlled by the clock signal on the Clk path 704 or the blanking circuit 732, this operation is referred to as the normal operating mode (and occasionally as the main operating mode herein).

[0062] Although in this discussion, the signal Isdet_out is asserted as high when the pin short-circuit detection circuit 730 detects a pin short-circuit event, it can also be asserted as low when the pin short-circuit detection circuit 730 detects a short circuit, provided that the subsequent logic circuitry represented by the NOR gate 710 and the D flip-flop 714 is adjusted accordingly. (For example, see below regarding...) Figure 7 (The following is a discussion of the pin short-circuit detection circuit 730.) When the pin short-circuit detection circuit 730 detects a pin short-circuit event, the state is in pin short-circuit operation mode regardless of whether the signal Isdet_out is asserted as high or low. In some examples, in response to the signal Isdet_out indicating the pin short-circuit operation mode, the signal Isfg is driven low, which in turn turns off the low-side FET 322.

[0063] Figure 7A schematic diagram of a power converter IC package 206 including a pin short-circuit detection circuit 730 according to various examples is depicted. In some examples, the power converter IC package 206 includes a blanking circuit 732, a NOR gate 710, a D flip-flop 714, a buffer 716, a pin short-circuit detection circuit 730, a high-side FET 320, and a low-side FET 322. In some examples, the D flip-flop 714 includes an inverter 824, an AND gate 800, an AND gate 802, a NOR gate 804, a NOR gate 806, and an AND gate 830. In further examples, the buffer 716 includes transistors 816, 818, 820, 822, 838, 840, 842, and 844. In some examples, the pin short-circuit detection circuit 730 includes transistors 852, 854, 858, 862, 868, 870, 874, and 876. In a further example, transistors 816, 818, 820, 822, 838, 840, 842, 844, 852, 854, 858, 862, 868, 870, 874, and 876 are FETs. In one example, FETs 818, 822, 840, 844, 854, and 858 are pMOSFETs or PMOS, and FETs 816, 820, 838, 842, 852, 862, 868, 870, 874, and 876 are nMOSFETs or NMOS. In yet another further example, FETs 852 and 868 are high-voltage FETs. Although... Figure 7 The circuitry for driving the high-side FET 320 is not depicted, but it is discussed above. Figure 2 An illustrative circuit for driving the high-side FET 320 is depicted.

[0064] In some examples, the configuration of D flip-flop 714 is similar to that of D flip-flop 314, where paths 808, 810, 814, 826, and 828 are coupled to logic gates 500, 502, 504, 506, and 530, respectively, along with paths 508, 510, 514, 526, and 528. Figure 4 They are coupled to logic gates 800, 802, 804, 806, and 830 in the same manner. In a further example, pin short-circuit detection circuit 730 is configured similarly to pin short-circuit detection circuit 330 because transistors 852, 854, 858, 862, 868, 870, 874, and 876 are coupled to each other with transistors 404, 406, 408, 410, 426, 430, 432, and 434. Figure 3 They are coupled to each other in the same way. However, since the pin short-circuit detection circuit 730 is configured to drive the low-side FET 322, therefore Figure 7 The path of the D flip-flop 714 differs from the following aspects Figure 4 The path of D flip-flop 314. VBIAS path 702 replaces VBIAS path 302. The clock signal on Clk path 704 replaces the clock signal on Clk path 304. Coupled from the output of AND gate 830, the input of NOR gate 804 and configured as Figure 7 The output path 736 of the shared input of the first inverter transistors 816 and 818 in the buffer 716 is replaced. Figure 3 The output path is 336. Furthermore, Figure 7 The path of the pin short-circuit detection circuit 730 differs from that of the other circuits in the following ways. Figure 3 The path of the pin short-circuit detection circuit 330. Figure 7 Replace GND path 324 Figure 3 SW path 326. Figure 7 Replace SW path 326 Figure 3 VIN path 300. Figure 7 Replace gndsen path 866 Figure 3 The swsen path is 424. Figure 7 Replace swsen path 860 Figure 3 Vinsen path 420. Bearing Figure 7 The output path of the signal Isdet_out is replaced by the bearer 708. Figure 3 The output path of the det_out signal is 308. The path carrying the vbiasP voltage is 856 (replacement). Figure 3 Path 414, and path 872 carrying the vbiasN voltage is replaced. Figure 3 Path 436.

[0065] In a further example, buffer 716 includes four inverters. Path 832 couples the output of the first inverter of buffer 716 to the shared input of FETs 820 and 822, which are configured as the second inverter of buffer 716. Path 834 couples the output of the second inverter of buffer 716 to the shared input of FETs 838 and 840, which are configured as the third inverter of buffer 716. Path 836 couples the output of the third inverter of buffer 716 to the shared input of FETs 842 and 844, which are configured as the fourth inverter of buffer 716. Output path 718 carries the signal Isfg and couples the output of the fourth inverter of buffer 716, the feedback path 719 of the pin short-circuit detection circuit 730, and the low-side FET 322.

[0066] Now describing Figure 7 The operation of the power converter IC package 206 shown is illustrated. In use... Figure 7In some examples of the circuit, VBIAS is high (and in some examples, remains high during both the primary operating mode and the pin-short operating mode), and the clock signal is high. With both inputs to AND gate 800 high, path 808 carries a high signal. A high signal as an input to NOR gate 804 causes path 814 to carry a low signal. With a high VBIAS input to inverter 824, the signal on path 826 is low. With a high clock signal and a low signal on path 826 as inputs to AND gate 802, the signal on path 810 is low. With the low signals carried on paths 810 and 814 as inputs, signal 828 of NOR gate 806 is high.

[0067] Now assume there is no pin short between SW pin 214 and VIN pin 216. In this case, the low-side FET 322 is turned on by the clock signal on Clk path 704, and the signal SW is pulled low to GND (ground voltage). FETs 870 and 874, acting as multiple bias transistors, behave as diode-connected transistors, such that the voltage on gndsen path 866 is approximately the sum of VT of FETs 870 and 874. (See...) Figure 3 A complete description of the structure and function of the bias transistors (e.g., multiple bias transistors 430, 432). Furthermore, when the signal SW is pulled low to GND, the voltage on the swsen path 860 is approximately GND. Since the signal swsen is less than the signal gndsen, the comparator transistor 868 is turned off. (See also...) Figure 3 A complete description of the structure and function of the comparator transistor (e.g., comparator transistor 410). Since comparator transistor 868 is off, transistor 858 is also off, and the signal Isdet_out is asserted as high. (See also...) Figure 3 A complete description of the structure and function of driving transistor 408 and generating the signal det_out. Therefore, the signal on output path 712 will be controlled by blanking circuit 732. More specifically, when blanking circuit 732 outputs a low signal, the signal on output path 712 is high, so the low-side FET 322 is controlled according to the clock signal of D flip-flop 714. When blanking circuit 732 outputs a high signal, the signal on output path 712 is low, so AND gate 830 is driven low, which in turn turns off low-side FET 322. As mentioned above... Figure 6 The specific timing and operational details of the blanking circuit 732 discussed herein can be implemented as needed to achieve specific performance or noise cancellation targets. When the clock signal of the blanking circuit 732 or the D flip-flop 714 controls the operation of the low-side FET 322, it is referred to as the primary operating mode.

[0068] In another example, the pin short-circuit detection circuit 730 detects a short circuit between pin SW 214 and pin VIN 216. When the low-side FET 322 is turned on by the clock signal on the Clk path 704, the signal SW is not pulled low to GND because pin SW 214 is shorted to pin VIN 216. Multiple bias transistors 870 and 874, acting as diode-connected transistors, amplify the signal GND, making the voltage on the gndsen path 866 approximately equal to the VT of FETs 870 and 874. Furthermore, since the signal SW is pulled up to VIN, and the signal CB is the voltage across the bootstrap capacitor 202 plus the signal SW, transistor 852 turns on, and the voltage on the swsen path 860 approximately equals the signal VIN. Because the magnitude of the signal swsen exceeding gndsen is greater than the VT of transistor 868, comparator transistor 868 turns on. As a result of transistor 868 turning on, transistor 858 also turns on, and the signal Isdet_out is asserted high on output path 708. When the input signal of NOR gate 710 (such as the signal Isdet_out) is high, the signal on output path 712 is low. When the input signal of AND gate 830 (such as the signal on output path 712) is low, the output signal on output path 736 is low. In this way, the output signal on output path 712 can be considered as a low-level reset driving D flip-flop 714. Buffer 716 receives the low signal on output path 736. Since FETs 816 and 818 are configured to invert the signal on output path 736, the signal on path 832 is high. FETs 820 and 822 are configured to invert the signal on path 832, so the signal on path 834 is low. Since FETs 838 and 840 are configured to invert the signal on output path 834, the signal on path 836 is high. FETs 842 and 844 are configured to invert the signal on path 836, so the signal Isfg on output path 718 is low.

[0069] Such as about Figure 6 As discussed, the low signal Isfg turns off the low-side FET 322, and the stop signal SW propagates along SW path 326 to the SW pin 214 of the power converter IC package 206. This is referred to as the pin-short-circuit operation mode. The ability of the pin-short-circuit detection circuit 730 to turn off the low-side FET 322 during a pin-short-circuit event advantageously reduces the likelihood of smoke and fire, and the propagation of the stop signal SW helps mitigate electrical damage to the circuit system.

[0070] As discussed above Figure 6As described above, although in some examples the signal Isdet_out is asserted as high when the pin short-circuit detection circuit 730 detects a pin short-circuit event, the signal Isdet_out can also be asserted as low when the pin short-circuit detection circuit 850 detects a pin short-circuit event, provided that the subsequent logic circuitry represented by the NOR gate 710 and the D flip-flop 714 is adjusted accordingly. For example, if the signal Isdet_out is asserted as low, then the signal Isdet_out can be an input to an inverter, the output of which is an input to the NOR gate 710. This configuration should achieve the same effect as described above. Figure 6 The same output as described in the example.

[0071] Figure 8 Timing diagrams depicting the operation of the pin short-circuit detection circuit 730 according to various examples are provided. SW waveform 904 corresponds to SW path 326 ( Figure 6 The voltage signal SW on the low-side FET 322 is shown. Waveform 906 (Isfg) corresponds to the gate-source voltage (VGS) signal on the low-side FET 322. Waveform 908 (Isdet_out) corresponds to the voltage signal on output path 708. Waveform 910 (swsen) corresponds to the voltage signal on swsen path 860. Waveform 966 (gndsen) corresponds to the voltage signal on gndsen path 866. Since the signal Isdet_out is determined by comparing the signals swsen and gndsen, these two waveforms are presented on the same axis, with gndsen represented by a solid line and swsen by a dashed line.

[0072] refer to Figure 8 waveform and Figure 6 and Figure 7Initially, the power converter IC package 206 is in the primary operating mode, as shown in number 900, where there is no pin short between SW pin 214 and VIN pin 216. In primary or normal operation 900, the clock signal first turns on the high-side FET 320 for a fixed time interval, or approximately 150 nanoseconds in this example, before the low-side FET 322 turns on. When the high-side FET 320 turns on, the low-side FET 322 turns off, and the signal Isfg should be low, as shown during the initial 150 nanosecond period of primary operation 900. After the high-side FET 320 turns off, the clock signal drives the signal Isfg high, which turns on the low-side FET 322 for a fixed time interval, or approximately 150 nanoseconds in this example. For the high signal Isfg to turn on the low-side FET 322, VGS (approximately 5.5V in this example) should exceed the threshold voltage of the low-side FET 322. In the absence of a pin short circuit, the signal swsen should be approximately equal to or lower than the signal gndsen, causing comparator transistor 862 to turn off and the signal Isdet_out to be low. The voltage signal SW corresponds to the voltage signal on SW path 326, or approximately 20V in this example. As the signal SW is pulled to VIN, the signal vinsen should be approximately equal to or lower than the signal swsen, causing comparator transistor 862 to turn off. In this example, the swsen waveform 910 and the gndsen waveform 912 indicate that the signals swsen and gndsen are almost the same, or that the signal swsen is slightly lower than the signal gndsen, indicating that transistor 862 is off. With transistor 862 off, the signal Isdet_out on the output path 308 of the pin short circuit detection circuit 730 is low, as shown by the Isdet_out waveform 908. (Although there are two brief spikes on the Isdet_out waveform 908, one at approximately 150 nanoseconds and the other at approximately 450 nanoseconds, the low-side FET 322 is off during these periods, as shown in the Isfg waveform 906. The brief spikes are caused by parasitic capacitance.)

[0073] Still referencing Figure 8 waveform and Figure 6 and Figure 7When a short circuit occurs between pin SW 214 and pin VIN 216, the signal SW on path 326 goes high, as shown by 20V in this example, indicated by digit 902. Despite the short circuit, the low-side FET 322 will still attempt to turn on due to the initial clock signal driving the signal Isfg, as shown by the spike in the Isfg waveform 906. However, when the signal SW is pulled to VIN, the signal swsen exceeds the signal gndsen, as shown at approximately 625 nanoseconds. This difference is large enough to turn on the comparator transistor 862. When transistor 862 turns on, the signal Isdet_out goes high, as shown by the time interval after 625 nanoseconds. The high signal Isdet_out drives the signal Isfg low, which turns off the low-side FET 322 with a negligible delay. The shortest on-time of the low-side FET 322 during a pin short-circuit event reduces the safety hazards of smoke and fire and helps mitigate electrical damage to the circuit system.

[0074] Figure 9 A flowchart 1000 depicts the operation of the pin short-circuit detection circuit 330 of the power converter IC package 206 during the main operating mode, according to various examples. The high-side power transistor 320 is turned on (1002). The output voltage at pin 214 of SW is set to be equal to the input voltage VIN (1004). The reference voltage at pin 210 of CB is set to be equal to the output voltage at pin 214 of SW plus the voltage across the bootstrap capacitor 202 coupled between pin 210 of CB and pin 214 of SW (1006). Transistor 406 is turned on using the reference voltage at pin 210 of CB (1008). The signal det_in is pulled high by the current flowing through transistor 406 (1010). Transistor 434 is turned on using the output voltage at pin 214 of SW (1012). The output signal det_out is pulled low at the drain terminal 434D of transistor 434, thereby keeping the high-side power transistor 320 on (1014).

[0075] In various examples, transistors 406 and 434 are bias transistors configured to allow bias current to flow. In some examples, transistor 410 is turned off, and transistor 406 is configured to drive the gate terminal 408G of transistor 408. Transistor 408 remains off as the signal det_in is pulled high by the bias current flowing through it. Transistor 434 is configured to carry the output signal det_out. When transistor 408 is off, the bias current of transistor 434 is configured to carry the low output signal det_out.

[0076] Figure 10A flowchart 1100 depicts the operation of the pin short-circuit detection circuit 330 of the power converter IC package 206 during pin short-circuit operation mode according to various examples. Output pin SW 214 is shorted to GND pin 212 (1102). The output voltage at pin SW 214 is pulled to ground (1104). High-side power transistor 320 is turned on (1106). The signal swsen is generated as the output voltage at pin SW 214 plus the threshold voltage across transistors 430 and 432 (1108). The signal swsen is applied to the source terminal 410S of transistor 410 (1110). The reference voltage at pin CB 210 is set to equal the output voltage at pin SW 214 plus the voltage across bootstrap capacitor 202 coupled between pin CB 210 and pin SW 214 (1112). Transistor 406 is turned on using the reference voltage at pin CB 210 (1114). The signal vinsen is applied to the gate terminal 410G of transistor 410, thereby turning on transistor 410 (1116). The gate terminal 408G of transistor 408 is pulled low by transistor 410, thereby turning on transistor 408 (1118). The output signal det_out is pulled high at the drain terminal 408D of transistor 408, thereby turning off the high-side power transistor 320 (1120). In this way, the pin short-circuit detection circuit 330 reduces the safety hazards of smoke and fire and mitigates electrical damage.

[0077] In some examples, transistors 430 and 432 act as amplifiers for the signal swsen. Transistor 430 is configured to amplify the signal swsen with its threshold voltage to generate a first amplified signal. Transistor 432 is configured to amplify the first amplified signal with its threshold voltage to generate a second amplified signal, which is the signal swsen amplified with the threshold voltages of transistors 430 and 432. In a further example, transistor 410 is configured to act as a comparator that compares the signal vinsen and the amplified signal swsen. Based on the comparison result, transistor 410 turns on or off, thereby affecting the state of the signal det_in. Based on the value of the signal det_in, transistor 408 turns on or off, and therefore the signal det_in at the non-control terminal 410D of transistor 410 is referred to as the reference signal. The output signal det_out is then determined by the reference signal, as it controls the operation of transistor 408.

[0078] In the foregoing discussion, the terms "including" and "comprising" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". The term "coupled" is used throughout this specification and claims. This term may cover a connection, communication, or signal path that enables a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B. Similarly, if there is an intermediate component C (or multiple such intermediate components) between device A and device B, then device A and device B may be said to be coupled to each other.

[0079] A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform that function, and / or may be configured (or reconfigured) by the user after manufacturing to perform that function and / or other additional or alternative functions. This configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof. Furthermore, a circuit or device described as including certain components may alternatively be configured to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be configured, at manufacturing time or after manufacturing, for example by an end user and / or a third party, to be coupled to at least some passive elements and / or sources to form the described structure.

[0080] While certain components are described herein as being made of specific process technologies (e.g., FET, MOSFET, n-type, p-type, etc.), these components are interchangeable with components of other process technologies (e.g., replacing FETs and / or MOSFETs with bipolar junction transistors (BJTs), n-types with p-types, or vice versa, etc.), and circuitry including the replaced components can be reconfigured to provide a desired function that is at least partially similar to the function available before the component replacement. Unless otherwise stated, elements illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. Furthermore, the use of the phrase "ground voltage potential" in the foregoing discussion is intended to include chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable to or suitable for the teachings of this disclosure. Unless otherwise stated, "about," "approximately," or "substantially" preceding numerical values ​​means + / - 10% of the stated value.

[0081] The foregoing discussion is intended to illustrate the principles and various embodiments of this disclosure. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. A system for pin short-circuit detection, comprising: Input voltage terminals; The power converter integrated circuit package, or power converter IC package, is fuse-free coupled to the input voltage terminal and includes: A first package terminal and a second package terminal are configured to receive a first signal and a second signal, respectively. A transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to a first package terminal, the control terminal being coupled to a second package terminal, and the second current terminal being configured to provide a reference signal in response to a first signal and a second signal, the first signal being responsive to a signal received at the first package terminal, and the second signal being based on a signal received at the second package terminal, the reference signal having a first state or a second state, the first state indicating a primary operating mode, and the second state indicating a pin-short-circuit operating mode; and The load circuit is coupled to the power converter IC package.

2. The system of claim 1, wherein the power converter IC package is directly coupled to the input voltage terminal.

3. The system according to claim 1, wherein the power converter IC package comprises: A pin short-circuit detection circuit is configured to provide an output signal having a first state or a second state, the first state indicating a primary operating mode and the second state indicating a pin short-circuit operating mode; and A power transistor configured to be operated by the output signal.

4. The system of claim 3, wherein the power converter IC package is configured to turn off the power transistor in response to the output signal having the second state.

5. The system of claim 3, wherein the transistor is a first transistor and wherein the power converter IC package includes a second transistor to provide the output signal in response to the reference signal.

6. The system of claim 5, wherein the power converter IC package comprises: A first bias transistor is configured to provide a first bias current based on the reference signal to control the operation of the second transistor; as well as A second bias transistor is configured to provide a second bias current based on the reference signal to drive the output signal.

7. The system of claim 5, wherein the power converter IC package includes a plurality of bias transistors configured to amplify the second signal before the first transistor compares the first signal and the second signal.

8. A pin short-circuit detection circuit, comprising: A first transistor has a first gate terminal, a first source terminal and a first drain terminal, the first gate terminal being coupled to an input voltage terminal and the first source terminal being coupled to a first output terminal via a plurality of bias transistors; A resistor coupled between the first gate terminal and the first source terminal; The second transistor has a second gate terminal coupled to the first drain terminal, a second source terminal coupled to the first junction terminal, and a second drain terminal coupled to the second output terminal; A first bias transistor is coupled between the first junction terminal and the first drain terminal; as well as A second bias transistor is coupled between the first output terminal and the second output terminal.

9. The pin short-circuit detection circuit according to claim 8, wherein the plurality of bias transistors comprises: A third bias transistor has a third gate terminal, a third source terminal and a third drain terminal, the third gate terminal being coupled to the third drain terminal and the third source terminal being coupled to the first output terminal; as well as A fourth transistor has a fourth gate terminal, a fourth source terminal and a fourth drain terminal, the fourth gate terminal being coupled to the fourth drain terminal and the fourth source terminal being coupled to the third drain terminal.

10. The pin short-circuit detection circuit of claim 9, further comprising a fifth transistor having a fifth gate terminal, a fifth source terminal and a fifth drain terminal, wherein the fifth drain terminal is coupled to the input voltage terminal, the fifth gate terminal is coupled to the first junction terminal, and the fifth source terminal is coupled to the first gate terminal.

11. The pin short-circuit detection circuit of claim 10, further comprising a sixth transistor having a sixth gate terminal, a sixth source terminal and a sixth drain terminal, the sixth drain terminal being coupled to the first source terminal, the sixth source terminal being coupled to the fourth drain terminal, and the sixth gate terminal being coupled to a third junction terminal.

12. The pin short-circuit detection circuit of claim 11, wherein the sixth transistor is configured to be controlled by a signal at the second output terminal.

13. The pin short-circuit detection circuit of claim 8, wherein the gate terminal of the first bias transistor is coupled to a first bias voltage terminal, and the gate terminal of the second bias transistor is coupled to a second bias voltage terminal.

14. A power converter IC package comprising: Power transistors; as well as A pin short-circuit detection circuit, coupled to the power transistor, includes: A first transistor is configured to compare a first signal and a second signal, the first signal being responsive to a signal received at a first package terminal and the second signal being based on a signal received at a second package terminal. as well as A second transistor is configured to provide an output signal having a first state or a second state in response to the comparison, the first state indicating a primary operating mode and the second state indicating a pin-short-circuit operating mode. The power transistor is controlled by the output signal.

15. The power converter IC package of claim 14, further comprising a resistor coupled between the gate terminal and the source terminal of the first transistor.

16. The power converter IC package of claim 14, further comprising: A third transistor is configured to amplify the first signal to generate a first amplified signal; A fourth transistor is configured to amplify the first amplified signal to generate a second amplified signal.

17. The power converter IC package of claim 16, wherein the first transistor is configured to compare the second amplified signal with the second signal.

18. The power converter IC package of claim 17, further comprising a first bias transistor coupled to the first transistor, wherein the first bias transistor is configured to provide a first bias current to control the operation of the second transistor.

19. The power converter IC package of claim 18, further comprising a second bias transistor coupled to the second transistor, wherein the second bias transistor is configured to provide a second bias current to drive the output signal when the second transistor is turned off.

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