Semiconductor package structure and electronic device

Abstract

The present disclosure relates to a semiconductor packaging structure and an electronic device, the semiconductor packaging structure comprising a substrate, a chip, an upper cover, a first heat-conducting layer and a barrier wall structure, wherein the chip is arranged on the substrate; the upper cover is connected to the substrate to form a cavity accommodating the chip; the first heat-conducting layer is arranged on the chip; and the barrier wall structure is arranged in the cavity and connected to the substrate, and the barrier wall structure is arranged around the outer periphery of the chip and the first heat-conducting layer. Through the above technical solution, the semiconductor packaging structure provided by the present disclosure can avoid the problem that the heat-conducting material contacts and damages the electrical element, and is helpful to improve the packaging yield and reliability of the packaging structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and an electronic device. Background Technology

[0002] In related technologies, chips are placed on a substrate. In order to dissipate heat from the chip, the chip is brought into contact with the heat dissipation device through a thermally conductive material. However, since the thermally conductive material is prone to breakage, shedding, or sputtering and coming into contact with electronic components on the substrate, it can easily damage the electronic components. Therefore, how to avoid the thermally conductive material from coming into contact with electronic components has become a research goal for industry professionals. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor packaging structure and electronic device that can avoid the problem of thermally conductive materials coming into contact with and damaging electrical components, thereby helping to improve the packaging yield and reliability of the packaging structure.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a semiconductor packaging structure, comprising: a substrate on which a chip is disposed; a top cover connected to the substrate to form a cavity for accommodating the chip; a first thermally conductive layer disposed on the chip; and a barrier structure disposed within the cavity and connected to the substrate, the barrier structure being arranged around the outer periphery of the chip and the first thermally conductive layer.

[0005] Optionally, the barrier structure includes at least one first annular protrusion arranged around the outer periphery of the chip and the first thermally conductive layer.

[0006] Optionally, the first thermal conductive layer includes a liquid metal thermal conductive layer; and / or, the first surface of the chip facing the top cover is connected to the top cover through the first thermal conductive layer.

[0007] Optionally, the retaining wall structure is integrally formed with the upper cover; or, the retaining wall structure is connected to the upper cover.

[0008] Optionally, the top cover includes a cover plate and a second annular protrusion arranged around the outer periphery of the cover plate. The second annular protrusion is connected to the substrate and forms the cavity with the substrate. The baffle structure is located inside the second annular protrusion to divide the cavity into an inner space inside the baffle structure and an outer space outside the baffle structure. The inner space is used to accommodate the chip and the first heat-conducting layer, and the outer space is used to accommodate electronic components.

[0009] Optionally, the semiconductor package structure further includes a heat sink connected to the outer wall surface of the top cover opposite to the first thermally conductive layer.

[0010] Optionally, the radiator and the top cover are thermally connected via a second thermally conductive layer.

[0011] Optionally, the second thermally conductive layer and the first thermally conductive layer are made of different materials.

[0012] Optionally, the chip has a second surface disposed away from the top cover, the second surface being connected to the substrate via a ball grid array.

[0013] A second aspect of this disclosure provides an electronic device including the semiconductor package structure provided in the first aspect above.

[0014] The semiconductor packaging structure provided in this disclosure, through the above-described technical solution, forms a cavity for accommodating the chip by connecting the top cover to the substrate. This top cover provides protection for the chip, improving the reliability of the packaging structure. Furthermore, a baffle structure is provided within the cavity, connected to the substrate and arranged around the outer periphery of the chip and the first thermally conductive layer. This baffle structure prevents the thermally conductive material from contacting electronic components, for example, when it breaks off or sputters at the first thermally conductive layer. This protects the electronic components, reduces the possibility of electrical short circuits, and helps improve the packaging yield and reliability of the packaging structure.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the semiconductor packaging structure provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the semiconductor packaging structure provided in an exemplary embodiment of this disclosure after removing the heat sink, cover plate and first thermal conductive layer from another angle.

[0017] Explanation of reference numerals in the attached figures 1-Substrate; 2-Chip; 210-First surface; 220-Second surface; 3-Top cover; 310-Cover plate; 320-Second annular protrusion; 4-Cavity; 410-Inner space; 420-Outer space; 5-First thermally conductive layer; 6-Baffle structure; 610-First annular protrusion; 7-Electronic component; 8-Heat sink; 9-Second thermally conductive layer; 10-Bottom filler adhesive. Detailed Implementation

[0018] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0019] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to upper and lower within the space of the semiconductor package structure when it is in use. "Inner" and "outer" refer to inner and outer relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0020] The inventors discovered that in related technologies, when a chip is mounted on a substrate, it is placed in contact with a heat dissipation device via a thermally conductive material to achieve heat dissipation. However, when this material is fabricated as a thermal pad, installation errors during chip packaging can easily cause the thermally conductive material to break and detach, coming into contact with electronic components on the substrate and potentially damaging them. Furthermore, when the thermally conductive material includes liquid metal or thermal adhesive, its fluidity can cause splashing or overflow during chip packaging, leading to contact with electronic components on the substrate and further damaging them. Therefore, preventing thermally conductive materials from contacting electronic components during chip packaging has become a research goal for industry professionals.

[0021] Based on this, according to the first aspect of this disclosure, a semiconductor packaging structure is provided, with reference to... Figure 1 and Figure 2 As shown, the semiconductor packaging structure includes a substrate 1, a chip 2, a top cover 3, a first thermally conductive layer 5, and a barrier structure 6. The chip 2 is disposed on the substrate 1; the top cover 3 is connected to the substrate 1 to form a cavity 4 for accommodating the chip 2; the first thermally conductive layer 5 is disposed on the chip 2; the barrier structure 6 is disposed in the cavity 4 and connected to the substrate 1, and the barrier structure 6 is arranged around the outer periphery of the chip 2 and the first thermally conductive layer 5.

[0022] Through the above-described technical solution, namely the semiconductor packaging structure provided in this disclosure, the semiconductor packaging structure connects the top cover 3 to the substrate 1 to form a cavity 4 for accommodating the chip 2. This allows the top cover 3 to protect the chip 2, thus improving the reliability of the packaging structure. Furthermore, a baffle structure 6 is provided within the cavity 4, connected to the substrate 1 and arranged around the outer periphery of the chip 2 and the first thermally conductive layer 5. Thus, the baffle structure 6 prevents the thermally conductive material from contacting electronic components 7, for example, when the thermally conductive material at the first thermally conductive layer 5 breaks off or sputters. This protects the electronic components 7, reduces the possibility of electrical short circuits in the electronic components 7, and helps improve the packaging yield and reliability of the packaging structure.

[0023] In some implementations, reference Figure 1 As shown, the first surface 210 of the chip 2 facing the upper cover 3 can be connected to the upper cover 3 through the first thermal conductive layer 5. This arrangement allows the chip 2 and the upper cover 3 to be thermally connected through the first thermal conductive layer 5, which is beneficial for quickly conducting the heat generated by the chip 2 to the upper cover 3 through the first thermal conductive layer 5, reducing the possibility of local heat accumulation and hot spots on the chip 2, and ensuring that the packaging structure has a high heat dissipation effect.

[0024] The first thermally conductive layer 5 may include a liquid metal thermally conductive layer. Because the liquid metal thermally conductive layer has high thermal conductivity, it can effectively conduct the heat generated by the chip 2 to the top cover 3, reducing the possibility of localized heat accumulation and hot spots on the chip 2, and ensuring a high heat dissipation effect for the packaging structure. Furthermore, the liquid metal thermally conductive layer can also adapt well to chips 2 and top cover 3 of different shapes or sizes, ensuring good thermal contact and contributing to improved heat dissipation.

[0025] In addition, it is understandable that the first thermally conductive layer 5 formed by liquid metal is prone to risks such as overflow or splashing of liquid metal. Therefore, by setting the above-mentioned barrier structure 6, the possibility of overflow or splashing of liquid metal and contact with other electronic components 7 on the substrate 1, causing electrical short circuits, can be reduced or even avoided. This helps to improve the packaging yield of the packaging structure and ensure that the packaging structure has high structural reliability.

[0026] Of course, it should be noted that the specific embodiment in which the first thermally conductive layer 5 includes a liquid metal thermally conductive layer is exemplary. In other alternative embodiments, the first thermally conductive layer 5 may also include a single thermally conductive material such as a thermally conductive adhesive layer, or it may be a composite thermally conductive material, for example. This disclosure does not specifically limit this, and those skilled in the art can design it adaptively according to actual application needs.

[0027] Exemplarily, in some implementations, reference is made to Figure 1 and Figure 2 As shown, the upper cover 3 may include a cover plate 310 and a second annular protrusion 320 arranged around the outer periphery of the cover plate 310. The second annular protrusion 320 is connected to the substrate 1 and forms a cavity 4 with the substrate 1. This arrangement can achieve the function of protecting the chip 2 through the upper cover 3. In addition, by connecting the second annular protrusion 320 of the upper cover 3 to the substrate 1, the structural strength of the substrate 1 can also be enhanced, reducing the possibility of warping risk of the substrate 1 due to the difference in thermal expansion coefficient during, for example, the packaging process, which helps to improve the packaging yield.

[0028] Among them, such as Figure 1 and Figure 2 As shown, the baffle structure 6 can be located inside the second annular protrusion 320 to divide the cavity 4 into an inner space 410 located inside the baffle structure 6 and an outer space 420 located outside the baffle structure 6. The inner space 410 is used to accommodate the chip 2 and the first thermal conductive layer 5, and the outer space 420 is used to accommodate the electronic component 7. With this arrangement, the baffle structure 6 can separate the inner space 410 and the outer space 420. When the thermal conductive material at the first thermal conductive layer 5 breaks off or sputters, it can prevent the thermal conductive material from contacting the electronic component 7, thus protecting the electronic component 7 and reducing the possibility of electrical short circuits in the electronic component 7. This helps to improve the packaging yield and reliability of the packaging structure.

[0029] It should be noted that this disclosure does not specifically limit the connection and fixing method between the top cover 3 and the substrate 1. Those skilled in the art can adapt the design according to actual application needs, such as welding or bonding. This disclosure is not limited to this. In addition, the electronic component 7 mentioned above may include, but is not limited to, discrete components.

[0030] In some embodiments, the retaining wall structure 6 can be integrally formed with the upper cover 3. This arrangement facilitates on-site installation and preparation and has high reliability. Alternatively, in some alternative embodiments, the retaining wall structure 6 can also be connected to the upper cover 3, for example, by adhesive bonding or welding. This disclosure does not specifically limit such variations; the purpose is simply to achieve a stable connection of the retaining wall structure 6 to the upper cover 3.

[0031] It is understood that when the aforementioned retaining wall structure 6 and the upper cover 3 are integrally formed, the material of the retaining wall structure 6 can be the same as the material of the upper cover 3. However, when the retaining wall structure 6 is connected to the upper cover 3, the material of the retaining wall structure 6 can be the same as or different from the material of the upper cover 3. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs. For example, in some embodiments, both the retaining wall structure 6 and the upper cover 3 can be made of insulating and thermally conductive materials, achieving both electrical insulation and thermal conduction. This ensures high reliability of the encapsulation structure while also improving its heat dissipation effect. This disclosure does not specifically limit the specific material of the aforementioned insulating and thermally conductive material; those skilled in the art can choose any known single insulating and thermally conductive material or composite insulating and thermally conductive material to prepare the aforementioned retaining wall structure 6 and upper cover 3.

[0032] Furthermore, in some implementations, references Figure 2 As shown, the barrier structure 6 may include at least one first annular protrusion 610 arranged around the outer periphery of the chip 2 and the first thermal conductive layer 5. Thus, by providing the first annular protrusion 610, the possibility of debris or adhesive overflow caused by the breakage and fall off of the thermal conductive material at the first thermal conductive layer 5 coming into contact with other electronic components 7 on the substrate 1 and causing an electrical short circuit can be reduced. Furthermore, by connecting the barrier structure 6 to the substrate 1 and the top cover 3, for example, by bonding or welding the barrier structure 6 to the substrate 1, the structural strength of the substrate 1 can be enhanced, and the possibility of warping risk of the substrate 1 due to the difference in thermal expansion coefficients during, for example, the packaging process can be reduced, which helps to improve the packaging yield.

[0033] It should be noted that this disclosure does not specifically limit the specific outline of the first annular protrusion 610. For example, the first annular protrusion 610 can be arranged in a ring or a polygon (e.g., square). The purpose is to enable the baffle structure 6 to be arranged around the outer periphery of the chip 2 and the first heat-conducting layer 5, so as to separate the inner space 410 and the outer space 420 of the cavity 4.

[0034] Furthermore, this disclosure does not specifically limit the specific shape and dimensions of the substrate 1, the top cover 3, or the barrier structure 6. Those skilled in the art can adapt the design according to actual application requirements. For example, along the first direction (refer to...) Figure 1 (in the left and right direction of the middle picture), the thickness of the second annular protrusion 320 of the top cover 3 can be greater than the thickness of the first annular protrusion 610 of the barrier structure 6, which is beneficial to the overall lightweight design of the packaging structure. This disclosure is not limited thereto.

[0035] In some implementations, reference Figure 1 and Figure 2 As shown, the semiconductor package structure may further include a heat sink 8, which is connected to the outer wall surface of the top cover 3 away from the first thermally conductive layer 5, thereby helping to improve the heat dissipation effect of the package structure. This disclosure does not specifically limit the specific structure and dimensions of the heat sink 8; those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the rapid conduction of heat generated by, for example, the chip 2 to the surrounding environment, thereby reducing the operating temperature of the chip 2 and reducing the possibility of performance degradation or damage due to overheating.

[0036] Additionally, in some implementations, references Figure 1 As shown, the heat sink 8 and the top cover 3 can be thermally connected through the second thermal conductive layer 9, so that the heat from the chip 2, which is conducted to the top cover 3 through the first thermal conductive layer 5, can be quickly conducted to the heat sink 8, thereby quickly conducting the heat generated by the chip 2 to the surrounding environment and reducing the operating temperature of the chip 2.

[0037] The materials of the second thermal conductive layer 9 and the first thermal conductive layer 5 can be different. For example, in some embodiments, the first thermal conductive layer 5 may include a liquid metal thermal conductive layer, and the second thermal conductive layer 9 may include at least one of a thermal conductive pad or a thermal conductive adhesive. This disclosure is not limited to this. The purpose is to enable the heat generated by the chip 2 to be quickly conducted to the surrounding environment through the thermal conduction of the first thermal conductive layer 5, the top cover 3, the second thermal conductive layer 9 and the heat sink 8, thereby reducing the operating temperature of the chip 2.

[0038] Of course, it is understood that in other alternative embodiments, the materials of the second thermally conductive layer 9 and the first thermally conductive layer 5 may also be constructed to be the same. This disclosure does not specifically limit this, and those skilled in the art can design it adaptively according to actual application needs.

[0039] Additionally, in some implementations, references Figure 1 As shown, chip 2 may have a second surface 220 arranged away from the top cover 3. For example, the second surface 220 of chip 2 arranged away from the first surface 210 is connected to the substrate 1 through a ball grid array. This arrangement allows the active surface (second surface 220) of chip 2 to be flip-chip mounted on substrate 1, for example, through a ball grid array (BGA) package. This helps to shorten the signal transmission path between chip 2 and substrate 1, improve the operating speed and performance of the circuit, and also helps to conduct the heat generated by chip 2 to substrate 1 and dissipate it to the surrounding environment, thereby reducing the operating temperature of chip 2 and improving the heat dissipation effect.

[0040] In this process, the chip 2 is flip-chip mounted on substrate 1, for example, by means of ball grid array packaging. The packaging operation of the chip 2 can be performed with reference to the principle of existing ball grid array packaging, which will not be described in detail here.

[0041] Additionally, in some implementations, references Figure 1 As shown, an underfill 10 can be provided between the chip 2 and the substrate 1 to fill the gap between the chip 2 and the substrate 1. This arrangement can improve the connection reliability between the chip 2 and the substrate 1, and also isolate air, reducing the risk of oxidation on the surface of the chip 2 and helping to extend the service life of the chip 2. At the same time, since the underfill 10 usually has good thermal conductivity, it can also conduct the heat generated by the chip 2 to the substrate 1 and dissipate it to the surrounding environment, reducing the possibility of local heat accumulation and hot spots on the chip 2, and helping to improve the heat dissipation effect of the packaging structure.

[0042] Of course, it is understood that the connection method between chip 2 and substrate 1 is not limited to the ball grid array packaging method described above. For example, chip 2 and substrate 1 can also be packaged using, for example, hybrid bonding. Those skilled in the art can adapt the design according to actual application requirements, and this disclosure does not impose specific limitations in this regard.

[0043] According to a second aspect of this disclosure, an electronic device is provided, comprising the semiconductor packaging structure provided in the first aspect. Furthermore, the electronic device also possesses all the beneficial effects of the aforementioned semiconductor packaging structure, which will not be elaborated further herein.

[0044] In some implementations, the aforementioned electronic devices may include, but are not limited to, general-purpose computing devices or specialized computing devices, such as computers, mobile phones, tablets, workstations, smartwatches, AI servers, cloud computing servers, data center equipment, etc.

[0045] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0046] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0047] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: A substrate on which a chip is disposed; A top cover, which is connected to the substrate to form a cavity for accommodating the chip; A first thermally conductive layer is disposed on the chip; as well as A baffle structure is disposed within the cavity and connected to the substrate, the baffle structure being arranged around the outer periphery of the chip and the first thermal conductive layer.

2. The semiconductor packaging structure according to claim 1, characterized in that, The barrier structure includes at least one first annular protrusion arranged around the outer periphery of the chip and the first thermally conductive layer.

3. The semiconductor packaging structure according to claim 1, characterized in that, The first thermally conductive layer includes a liquid metal thermally conductive layer; and / or, The first surface of the chip facing the top cover is connected to the top cover through the first thermal conductive layer.

4. The semiconductor packaging structure according to claim 1, characterized in that, The retaining wall structure is integrally formed with the upper cover; or... The retaining wall structure is connected to the upper cover.

5. The semiconductor packaging structure according to any one of claims 1-4, characterized in that, The upper cover includes a cover plate and a second annular protrusion arranged around the outer periphery of the cover plate. The second annular protrusion is connected to the substrate and forms the cavity with the substrate. The baffle structure is located inside the second annular protrusion, so as to divide the cavity into an inner space inside the baffle structure and an outer space outside the baffle structure. The inner space is used to accommodate the chip and the first heat-conducting layer, and the outer space is used to accommodate electronic components.

6. The semiconductor packaging structure according to any one of claims 1-4, characterized in that, The semiconductor package structure also includes a heat sink, which is connected to the outer wall surface of the top cover away from the first thermally conductive layer.

7. The semiconductor packaging structure according to claim 6, characterized in that, The radiator and the top cover are thermally connected through a second thermally conductive layer.

8. The semiconductor packaging structure according to claim 7, characterized in that, The second thermal conductive layer is made of a different material than the first thermal conductive layer.

9. The semiconductor packaging structure according to any one of claims 1-4, characterized in that, The chip has a second surface disposed away from the top cover, and the second surface is connected to the substrate via a ball grid array.

10. An electronic device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-9.

Images