Test load board and test system for chip burn-in and test operating mode switching

CN224696024UActive Publication Date: 2026-08-28NANJING SILICONARRAY TECH CO LTD
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Patent Information

Application Number
CN202521785265.7
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-08-21
Publication Date
2026-08-28
Estimated Expiration
2035-08-21

AI Technical Summary

Benefits of technology

[0017]通过设置开关,可以在测试工况时将滤波电容旁路,不接入电路中以避免滤波电容影响第二引脚处的驱动能力,同时使得测试工况更加符合待测芯片的实际使用场景。此外,通过NMOS管或PMOS管来实现开关,由于NMOS管和PMOS管本身的尺寸较小,也不会导致滤波电容远离第一引脚,避免影响烧录工况时滤波电容的电压稳定效果,以提高烧录成功率和芯片良率。同时,通过MOS管实现的开关寿命较长、切换时间快、功耗极低,且可以与继电器复用控制。

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Abstract

This application discloses a test load board and test system for switching chip programming and testing modes. The chip under test includes an electronic fuse, a first pin connected to the electronic fuse, a linear regulator, and a second pin connected to the linear regulator. The test load board includes: a first external power supply terminal; a second external power supply terminal, which is powered on in a time-sharing manner with the first external power supply terminal; and an electromagnetic relay, including a normally open contact, a normally closed contact, a common terminal, and a relay power supply terminal. The relay power supply terminal is connected to the first external power supply terminal, the normally closed contact is connected to the second external power supply terminal, the normally open contact is connected to the second pin, and the common terminal is connected to the first pin. When the first external power supply terminal is not supplying power, the common terminal is connected to the normally closed contact; when the first external power supply terminal is supplying power, the common terminal is connected to the normally open contact.
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