Board, chassis, clock distribution circuit and system applied to quantum computing

Abstract

A board card, a case, a clock distribution circuit and system applied to quantum computing belong to the technical field of quantum computing; wherein the clock distribution adopts a homologous double-channel architecture: a high-precision clock source synchronously outputs a high-speed clock and a low-speed clock; the high-speed channel converts the high-speed clock electrical signal into a high-speed clock optical signal through microwave modulation of a light source, is amplified in optical power, is split by an optical splitter, is distributed to each case control board card through an optical fiber, is converted into a high-speed clock electrical signal by a PD detector, and is supplied to a DAC for use as a high-speed sampling clock; the low-speed channel accesses each case control board card through a radio frequency cable, is distributed after Buffer and PLL, is multiplied or divided, and is supplied to an FPGA and a DAC for use as a synchronous communication clock; the problem of multiple PLL clock asynchronization is solved, and the problems of phase drift, impedance mismatch, and temperature-sensitive jitter of existing radio frequency cable transmission are solved, and the phase stability of quantum bit control is significantly improved.

Description

Technical Field

[0001] This utility model belongs to the field of quantum computing technology, and relates to a board, chassis, clock distribution circuit and system for quantum computing. Background Technology

[0002] The synchronous clock distribution of chassis and boards is a key technology to ensure high-precision time synchronization among boards in a distributed system, especially crucial in fields such as quantum computing, quantum communication, lidar, and industrial automation. For example, in the field of quantum computing, when conducting large-scale qubit experiments, multiple control signals must be manipulated simultaneously, and any asynchrony in any control signal will affect the accuracy of the experiment.

[0003] like Figure 6 As shown, when multiple chassis are networked, the existing technology typically uses a high-precision clock source, which is cascaded from the top-level chassis (e.g., chassis 1) to the lower-level chassis (e.g., chassis 2 to chassis N) via RF cables, outputting the clock signal to the clock board input interface of the lower-level chassis. Specifically, Buffer 1 (Buffer means clock buffer) on the clock board of chassis 1 divides the clock signal into N paths. The first path of the clock signal is sent to Buffer 2 on the clock board of chassis 1 and then sent to each control board in chassis 1 through the backplane. The second to Nth paths of the clock signal are respectively sent to Buffer 2 on the clock boards of chassis 2 to chassis N as external reference clocks. In each control board of each chassis, the frequency is multiplied by a PLL phase-locked loop and then sampled by a frequency divider chip (such as FPGA, DAC, or other IC devices).

[0004] Existing solutions rely on cascaded RF cables for clock distribution between chassis boards, which has the following drawbacks: long-distance RF cables significantly exacerbate signal loss, latency, phase shift, and impedance mismatch; temperature changes and mechanical vibrations further degrade signal transmission quality, and existing phase-stable cables are only effective within a limited temperature range; multiple control boards use independent PLL (phase-locked loop) frequency multiplication clocks, and due to the closed-loop feedback mechanism of the PLL, if the error in the output oscillation frequency reaches a certain range, the PLL output frequency will be considered successfully locked. Therefore, the PLL output clock has inherent phase instability, and the phase synchronization of the clocks output between multiple PLLs is even worse. These drawbacks lead to the loss of synchronization of multiple control signals in large-scale quantum bit experiments, reducing the accuracy of the experiments. Utility Model Content

[0005] The technical solution of this utility model is used to solve the problem of how to improve the synchronization of control signals.

[0006] This utility model solves the above-mentioned technical problems through the following technical solution: This invention provides a control board for quantum computing, comprising a clock buffer, a phase-locked loop (PLL), a PD detector, an amplification and filtering module, a power divider, an FPGA, and multiple DACs. The output of the clock buffer is connected to the input of the PLL, and the output of the PLL is connected to the inputs of the FPGA and the multiple DACs. The output of the PD detector is connected to the input of the amplification and filtering module, the output of the amplification and filtering module is connected to the input of the power divider, and the output of the power divider is connected to the inputs of the multiple DACs. The input of the PD detector serves as the high-speed clock optical signal input interface of the control board, and the input of the clock buffer serves as the low-speed clock electrical signal input interface of the control board.

[0007] Furthermore, the output of the clock buffer is connected to the input of the phase-locked loop via PCB traces. The output of the phase-locked loop is connected to the inputs of the FPGA and multiple DACs via PCB traces. The output of the PD detector is connected to the input of the amplification and filtering module via PCB traces. The output of the amplification and filtering module is connected to the input of the power divider via PCB traces. The output of the power divider is connected to the inputs of multiple DACs via PCB traces.

[0008] This invention also provides a multi-channel clock distribution circuit for quantum computing, including a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple control boards. The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source. The output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces. The second output terminal of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces. The multiple high-speed clock optical signal output interfaces are connected one-to-one with the high-speed clock optical signal input interfaces of the multiple control boards, and the multiple low-speed clock electrical signal output interfaces are connected one-to-one with the low-speed clock electrical signal input interfaces of the multiple control boards.

[0009] Furthermore, the high-speed clock optical signal output interface is connected one-to-one with the high-speed clock optical signal input interfaces of multiple control boards using optical fibers.

[0010] Furthermore, the low-speed clock signal output interface is connected one-to-one with the low-speed clock signal input interfaces of multiple control boards using radio frequency cables.

[0011] Furthermore, the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable.

[0012] This utility model also provides a chassis for quantum computing, including multiple control boards as described above. The multiple control boards are arranged in parallel inside the chassis housing. The low-speed clock electrical signal input interface of the control board serves as the low-speed clock electrical signal input interface of the chassis, and the high-speed clock optical signal input interface of the control board serves as the high-speed clock optical signal input interface of the chassis.

[0013] This invention also provides a multi-channel clock distribution system for quantum computing, comprising a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple aforementioned chassis. The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source. The output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces. The second output terminal of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces. The multiple high-speed clock optical signal output interfaces are connected one-to-one with the high-speed clock optical signal input interfaces of the multiple chassis, and the multiple low-speed clock electrical signal output interfaces are connected one-to-one with the low-speed clock electrical signal input interfaces of the multiple chassis.

[0014] Furthermore, the high-speed clock optical signal input interface and the high-speed clock optical signal output interface of the chassis are connected by optical fiber.

[0015] Furthermore, the low-speed clock signal input interface and the low-speed clock signal output interface of the chassis are connected by an radio frequency cable. Attached Figure Description

[0016] Figure 1 This is a structural diagram of the control board for quantum computing according to Embodiment 1 of this utility model; Figure 2 This is a structural diagram of the chassis for quantum computing according to Embodiment 2 of this utility model; Figure 3 This is a structural diagram of the chassis networking system for quantum computing according to Embodiment 2 of this utility model; Figure 4 This is a structural diagram of the multi-channel clock distribution circuit applied to quantum computing according to Embodiment 3 of this utility model; Figure 5 This is a structural diagram of the multi-channel clock distribution system for quantum computing according to Embodiment 4 of this utility model; Figure 6 This is a structural diagram of a current multi-channel clock distribution system. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below in conjunction with the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0018] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 As shown, this embodiment provides a control board for quantum computing. The control board includes a clock buffer, a phase-locked loop (PLL), a PD detector, an amplification and filtering module, a power divider, an FPGA, and multiple DACs.

[0019] The output of the clock buffer is connected to the input of the phase-locked loop (PLL) via PCB traces. The output of the PLL is connected to the inputs of the FPGA and multiple DACs via PCB traces. The output of the PD detector is connected to the input of the amplification and filtering module via PCB traces. The output of the amplification and filtering module is connected to the input of the power divider via PCB traces. The output of the power divider is connected to the inputs of multiple DACs via PCB traces. The input of the PD detector serves as the high-speed clock optical signal input interface of the control board, and the input of the clock buffer serves as the low-speed clock electrical signal input interface of the control board.

[0020] The workflow of the control board in this embodiment is as follows: A high-speed clock optical signal is input through the high-speed clock optical signal input interface of the control board. It is converted into a high-speed clock electrical signal by the PD detector, and then amplified, filtered and divided by the amplification and filtering module and the power divider before being supplied to the DAC as a sampling clock. A low-speed clock electrical signal is input through the low-speed clock electrical signal input interface. It is distributed, multiplied or divided by the clock buffer and phase-locked loop before being supplied to the FPGA and DAC as a synchronous communication clock.

[0021] The control board in this embodiment can receive high-speed clock optical signals, which are converted into high-speed clock electrical signals by a PD detector, and can also receive low-speed clock electrical signals, enhancing the applicability and flexibility of the system. Amplification and filtering modules improve signal quality and reduce noise. A power divider distributes the high-speed clock electrical signal to multiple DACs, ensuring clock consistency across channels. A phase-locked loop (PLL) distributes, multiplies, or divides the low-speed clock electrical signal to meet the different clock requirements of the FPGA and DACs. The buffer, PLL, PD detector, amplification and filtering modules, power divider, FPGA, and DAC are integrated onto the same control board, with PCB traces connecting the modules to reduce signal delay and interference, and improve synchronization accuracy and system stability.

[0022] Example 2 like Figure 2 As shown, this embodiment provides a chassis for quantum computing. The chassis includes n control boards as described in Embodiment 1. The n control boards are arranged in parallel inside the chassis housing, where n is an integer greater than or equal to 2. The low-speed clock electrical signal input interface of the control board serves as the low-speed clock electrical signal input interface of the chassis, and the high-speed clock optical signal input interface of the control board serves as the high-speed clock optical signal input interface of the chassis.

[0023] like Figure 3 As shown, this embodiment also provides a chassis networking system for quantum computing, the chassis networking system including N chassis, the N chassis being arranged in parallel, where N is an integer greater than or equal to 2.

[0024] Example 3 like Figure 4 As shown, this embodiment provides a multi-channel clock distribution circuit for quantum computing. The clock distribution circuit includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple control boards as described in Embodiment 1. The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable. The output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces. These multiple high-speed clock optical signal output interfaces are connected one-to-one with the high-speed clock optical signal input interfaces of the multiple control boards in Embodiment 1 via optical fibers. The second output terminal of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces. These multiple low-speed clock electrical signal output interfaces are connected one-to-one with the low-speed clock electrical signal input interfaces of the multiple control boards in Embodiment 1 via RF cables.

[0025] The clock distribution circuit in this embodiment operates as follows: The high-precision clock source outputs both a high-speed clock electrical signal (1GHz~12GHz) and a low-speed clock electrical signal (10MHz~300MHz). The microwave modulation light source acts as a photoelectric conversion module, converting the high-speed clock electrical signal into a high-speed clock optical signal. The high-speed clock optical signal is amplified and distributed by an optical power amplifier and an optical beam splitter. The output of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces. The high-speed clock optical signal output interfaces use optical fibers to output high-speed clock optical signals and distribute them to multiple control boards. The second output of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces. The low-speed clock electrical signal output interfaces use radio frequency cables to output low-speed clock electrical signals and distribute them to multiple control boards.

[0026] The high precision of the high-precision clock source in this embodiment can be high synchronization precision (e.g., synchronization precision requirement: ≤20ns) or high frequency precision (usually reflected in phase noise, for example, low frequency phase noise requirement: 50MHz≤-160dBc / Hz@1kHz, 250MHz≤-143dBc / Hz@1kHz; high frequency phase noise requirement: 1GHz≤-140dBc / Hz@1kHz, 10GHz≤-122dBc / Hz@1kHz, 20GHz≤-116dBc / Hz@1kHz). Those skilled in the art can select the device according to actual needs.

[0027] In this embodiment, the clock distribution circuit outputs both a high-speed and a low-speed clock signal from a high-precision clock source, ensuring that the low-speed reference clock and high-speed sampling clock of multiple control boards share the same clock synchronization circuit. A microwave modulation light source is used to convert the high-speed clock signal output from the high-precision clock source into a high-speed clock optical signal for transmission and input to each control board. Fiber optic transmission solves the problems of loss, delay and phase shift, impedance mismatch, and noise interference caused by RF cable transmission. Furthermore, fiber optic transmission is less sensitive to temperature changes and mechanical vibrations, enabling precise clock synchronization among multiple control boards and ensuring high stability of the DAC output phase, meeting the requirements for quantum control output phase stability. The low-speed clock signal is used for synchronous communication between the FPGA and the DAC. All of the above achieves precise clock synchronization and high phase stability among multiple control boards.

[0028] Example 4 like Figure 5As shown, this embodiment provides a multi-channel clock distribution system for quantum computing. The clock distribution system includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and N (N is an integer greater than or equal to 2) parallel-arranged chassis, namely chassis 1, chassis 2... chassis N; each chassis includes n (n is an integer greater than or equal to 2) parallel-arranged control boards, namely control board 1, control board 2... control board n.

[0029] Each control board includes: a clock buffer, a phase-locked loop (PLL), a PD detector, an amplification and filtering module, a power divider, an FPGA, and multiple DACs. The output of the clock buffer is connected to the input of the PLL via PCB traces. The output of the PLL is connected to the input of the FPGA and multiple DACs via PCB traces. The output of the PD detector is connected to the input of the amplification and filtering module via PCB traces. The output of the amplification and filtering module is connected to the input of the power divider via PCB traces. The output of the power divider is connected to the input of the multiple DACs via PCB traces.

[0030] The high-precision clock source has a first output terminal that outputs a high-speed clock signal and a second output terminal that outputs a low-speed clock signal. The first output terminal of the high-precision clock source is connected to the input terminal of a microwave modulation light source via an RF cable. The output terminal of the microwave modulation light source is connected to the input terminal of an optical power amplifier via an optical fiber. The output terminal of the optical power amplifier is connected to the input terminal of an optical beam splitter via an optical fiber. The output terminal of the optical beam splitter is divided into N×n paths, each connected to the input terminal of one of the n PD detectors in each chassis via an optical fiber. The input terminals of the PD detectors serve as the high-speed clock signal input interface for the control board. The second output terminal of the high-precision clock source is also divided into N×n paths, each connected to the input terminal of one of the n clock buffers in each chassis via an RF cable. The input terminals of the clock buffers serve as the low-speed clock signal input interface for the control board.

[0031] The functions of each module in the clock distribution system of this embodiment are as follows: 1) The high-precision clock source outputs a high-speed clock signal (1GHz~12GHz) and a low-speed clock signal (10MHz~300MHz) from the same source. The high-speed clock signal is used for DAC sampling clock, meeting the performance requirements of low phase noise and low jitter, and ensuring the phase stability of the DAC output. The low-speed clock signal is used for digital signal communication data acquisition, which can achieve the performance requirements of lower phase noise and jitter, and ensure error-free transmission. The same source output can ensure the clock synchronization of the high-speed clock signal and the low-speed clock signal. 2) The microwave modulation light source, as a photoelectric conversion module, can convert the high-speed clock electrical signal generated by the high-precision clock source into a high-speed clock optical signal; 3) The optical power amplifier is used to amplify the converted high-speed clock optical signal. The amplified high-speed clock optical signal is then connected to the optical beam splitter. The amplification power is flexibly determined according to the number of chassis and control boards. 4) The optical beam splitter is used to distribute the high-speed clock optical signal into multiple paths and connect them to the PD detectors on each control board in each chassis. The number of beam splitters is flexibly determined according to the number of chassis and control boards. 5) The PD detector, as a photoelectric conversion module, converts high-speed clock optical signals into high-speed clock electrical signals; 6) The amplification and filtering module is used to amplify and filter the high-speed clock signal. The amplification factor is flexibly determined according to the number of DACs. 7) The power divider is used to distribute high-speed clock signals. The output signal is connected to the DAC, and the number of signals distributed is flexibly determined according to the number of DACs. 8) The clock buffer is used to distribute the low-speed clock signal generated by the high-precision clock source; 9) Phase-locked loops (PLLs) are used to distribute, multiply, or divide low-speed clock signals. Their number is determined by the number of low-speed clocks required by the integrated circuit devices (FPGA, DAC) on the control board. The output signals are connected to the FPGA and multiple DACs respectively for synchronous communication between the FPGA and DAC. 10) DAC is a digital-to-analog converter, used to convert digital signals into analog signals and output multiple analog signals. The control board in this embodiment is equipped with multiple DACs.

[0032] The workflow of the multi-channel clock distribution system in this embodiment is as follows: The high-precision clock source outputs both high-speed clock electrical signals (1GHz~12GHz) and low-speed clock electrical signals (10MHz~300MHz). The microwave modulation light source acts as a photoelectric conversion module, converting the high-speed clock electrical signals into high-speed clock optical signals. After being amplified by an optical power amplifier and an optical beam splitter, the high-speed clock optical signals are distributed into multiple paths and transmitted via optical fiber to each control board in each chassis. Each control board's PD detector converts the signals into high-speed clock electrical signals, which are then amplified, filtered, and divided by a power divider before being supplied to the DAC as a high-speed sampling clock. The low-speed clock electrical signals output from the high-precision clock source are connected to each control board in each chassis via RF cables. After passing through a clock buffer and a phase-locked loop, the signals are distributed, multiplied, or divided to the FPGA and DAC as a synchronous communication clock.

[0033] The clock distribution system in this embodiment outputs both high-speed and low-speed clock signals from a high-precision clock source, ensuring that low-speed reference clocks and high-speed sampling clocks from multiple chassis and boards share the same clock synchronization circuit. A microwave-modulated light source is used to convert the high-speed clock signal output from the high-precision clock source into a high-speed clock optical signal for transmission, which is then input to each control board in each chassis. Fiber optic transmission eliminates the losses, delays, phase shifts, impedance mismatches, and noise interference caused by RF cable transmission. Furthermore, fiber optic transmission is less sensitive to temperature changes and mechanical vibrations, ensuring precise clock synchronization between chassis and boards, guaranteeing high stability of the DAC output phase and meeting the requirements for quantum control output phase stability. The low-speed clock signal is used for synchronous communication between the FPGA and the DAC. All of these measures achieve precise clock synchronization and high phase stability between multiple chassis and boards.

[0034] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A control board for quantum computing, characterized in that, It includes a clock buffer, a phase-locked loop (PLL), a PD detector, an amplification and filtering module, a power divider, an FPGA, and multiple DACs. The output of the clock buffer is connected to the input of the PLL, and the output of the PLL is connected to the inputs of the FPGA and the multiple DACs. The output of the PD detector is connected to the input of the amplification and filtering module, the output of the amplification and filtering module is connected to the input of the power divider, and the output of the power divider is connected to the inputs of the multiple DACs. The input terminal of the PD detector serves as the high-speed clock optical signal input interface of the control board, and the input terminal of the clock buffer serves as the low-speed clock electrical signal input interface of the control board.

2. The control board according to claim 1, characterized in that, The output of the clock buffer is connected to the input of the phase-locked loop (PLL) via PCB traces. The output of the PLL is connected to the inputs of the FPGA and multiple DACs via PCB traces. The output of the PD detector is connected to the input of the amplification and filtering module via PCB traces. The output of the amplification and filtering module is connected to the input of the power divider via PCB traces. The output of the power divider is connected to the inputs of multiple DACs via PCB traces.

3. A multi-channel clock distribution circuit for quantum computing, characterized in that, It includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple control boards as described in claim 1 or 2; the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier through an optical fiber, and the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter through an optical fiber; the output terminal of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces; The second output terminal of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces; The multiple high-speed clock optical signal output interfaces are connected one-to-one with the high-speed clock optical signal input interfaces of multiple control boards, and the multiple low-speed clock electrical signal output interfaces are connected one-to-one with the low-speed clock electrical signal input interfaces of multiple control boards.

4. The clock distribution circuit according to claim 3, characterized in that, The high-speed clock optical signal output interface uses optical fiber to connect one-to-one with the high-speed clock optical signal input interfaces of multiple control boards.

5. The clock distribution circuit according to claim 3, characterized in that, The low-speed clock signal output interface is connected one-to-one with the low-speed clock signal input interfaces of multiple control boards using radio frequency cables.

6. The clock distribution circuit according to claim 3, characterized in that, The first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source via an RF cable.

7. A chassis for quantum computing, characterized in that, It includes multiple control boards as described in claim 1 or 2, which are arranged in parallel within the chassis housing. The low-speed clock electrical signal input interface of the control board serves as the low-speed clock electrical signal input interface of the chassis, and the high-speed clock optical signal input interface of the control board serves as the high-speed clock optical signal input interface of the chassis.

8. A multi-channel clock distribution system for quantum computing, characterized in that, It includes a high-precision clock source, a microwave modulation light source, an optical power amplifier, an optical beam splitter, and multiple chassis as described in claim 7; the first output terminal of the high-precision clock source is connected to the input terminal of the microwave modulation light source, the output terminal of the microwave modulation light source is connected to the input terminal of the optical power amplifier through an optical fiber, the output terminal of the optical power amplifier is connected to the input terminal of the optical beam splitter through an optical fiber; the output terminal of the optical beam splitter is divided into multiple high-speed clock optical signal output interfaces; The second output terminal of the high-precision clock source is divided into multiple low-speed clock electrical signal output interfaces; The multiple high-speed clock optical signal output interfaces are connected one-to-one with the high-speed clock optical signal input interfaces of multiple chassis, and the multiple low-speed clock electrical signal output interfaces are connected one-to-one with the low-speed clock electrical signal input interfaces of multiple chassis.

9. The clock distribution system according to claim 8, characterized in that, The high-speed clock optical signal input interface and the high-speed clock optical signal output interface of the chassis are connected by optical fiber.

10. The clock distribution system according to claim 8, characterized in that, The low-speed clock signal input interface and the low-speed clock signal output interface of the chassis are connected by an radio frequency cable.

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