Chip mount and laser annealing apparatus

Abstract

The utility model discloses a kind of chip carrier and laser annealing equipment, belong to chip preparation technical field.The chip carrier includes: substrate, with oppositely arranged upper surface and lower surface, the upper surface has the boss for placing the chip of laser annealing, the lower surface is equipped with recess;With the annular cavity wall of substrate connection, vertically set in the periphery of the substrate, form side structure;Cover plate, cover in the top of the cavity wall and with the substrate jointly constitute closed cavity;Refrigeration system, install in the recess bottom, for controlling the temperature of the recess bottom.In the above-mentioned chip carrier, the upper and lower surfaces of substrate have boss and recess respectively, the boss is used to place the chip for laser annealing, the refrigeration system for controlling the temperature of the recess bottom is installed in the recess, and then the refrigeration system can control the environmental temperature where the chip located in boss during laser annealing process, and the chip aging rate during laser annealing process can be reduced.

Description

Technical Field

[0001] This utility model belongs to the field of chip fabrication technology, specifically a chip stage and laser annealing equipment. Background Technology

[0002] Due to the limitations of the fabrication method of superconducting qubits, the frequency and room temperature resistance of the qubit structure cannot be directly and precisely controlled. Therefore, it is necessary to adjust the resistance of each qubit individually through laser annealing before packaging the quantum chip.

[0003] As the number of qubits on quantum chips increases dramatically, the number of qubits requiring laser annealing also increases, and the annealing time becomes longer. However, the increased total annealing time inevitably leads to the aging of qubits on the quantum chip.

[0004] Therefore, how to reduce the aging rate of qubits on quantum chips during laser annealing is an urgent problem to be solved. Utility Model Content

[0005] The purpose of this invention is to provide a chip stage and laser annealing equipment to overcome the shortcomings of the prior art. It can reduce the aging rate of qubits on quantum chips during the laser annealing process.

[0006] The solution presented in this application is implemented through the following steps.

[0007] In a first aspect, examples of this application provide a chip stage, the chip stage comprising:

[0008] The substrate has an upper surface and a lower surface disposed opposite to each other. The upper surface has a boss for placing a laser-annealed chip, and the lower surface has a groove.

[0009] An annular cavity wall connected to the substrate is vertically disposed around the substrate to form a side enclosure structure;

[0010] A cover plate, which covers the top of the cavity wall and together with the substrate, forms a closed cavity;

[0011] A refrigeration system is installed at the bottom of the groove to control the temperature at the bottom of the groove.

[0012] According to some examples of this application, the surface of the boss is coated with a heat dissipation medium to increase the heat dissipation of the chip.

[0013] According to some examples of this application, the cavity wall is connected to a vacuum valve for adjusting the vacuum level of the enclosed cavity.

[0014] According to some examples of this application, the cavity wall is integrally formed with the substrate.

[0015] According to some examples of this application, the cover plate is detachably connected to the cavity wall.

[0016] According to some examples of this application, the detachable method includes at least one of screw connection, snap-fit ​​connection or magnetic adsorption.

[0017] According to some examples of this application, the refrigeration system includes:

[0018] A semiconductor cooling chip is embedded in the bottom of the groove;

[0019] A liquid-cooled heat sink is attached to the side of the semiconductor cooling chip that is furthest from the chip.

[0020] A temperature controller, embedded in the inner wall of the groove, is used to detect the temperature of the chip and regulate the semiconductor cooling chip according to the temperature and a preset temperature.

[0021] According to some examples of this application, the cover plate is provided with a light-transmitting window for observation and laser beam incident.

[0022] According to some examples of this application, the chip stage further includes:

[0023] A water-collecting base is used to hold the substrate and to collect condensate.

[0024] Secondly, examples of this application provide a laser annealing apparatus having the chip stage described in the first aspect above.

[0025] In the chip stage of the example described above in this application, the upper and lower surfaces of the substrate have a boss and a groove, respectively. The boss is used to place the chip to be laser annealed, and the groove is equipped with a cooling system to control the temperature at the bottom of the groove. The cooling system can control the ambient temperature of the chip located on the boss during the laser annealing process, thereby reducing the chip aging rate during the laser annealing process. Attached Figure Description

[0026] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0027] Figure 1 This is a structural diagram of the substrate and annular cavity wall in one example of this application;

[0028] Figure 2 Here is a structural diagram of the cover plate in another example of this application;

[0029] Figure 3 This is a structural diagram of a water-receiving base in another example of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0031] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0033] In the fabrication of superconducting quantum chips, the frequency and room-temperature resistance of qubits cannot be directly and precisely controlled due to limitations in the manufacturing process. Laser annealing is required to fine-tune the resistance of each qubit before packaging. As the number of qubits increases (e.g., in chips with hundreds of qubits), the annealing time increases linearly, potentially taking tens of hours to anneal a single chip. This prolonged annealing process can accelerate the aging of the qubits on the chip.

[0034] Based on this, such as Figure 1 and Figure 2 As shown in the illustration, one embodiment of this utility model provides a chip carrier, which includes, for example, the following components:

[0035] The substrate has an upper surface and a lower surface that are disposed opposite to each other. The upper surface has a protrusion 110 for placing a laser-annealed chip, and the lower surface has a groove 120.

[0036] An annular cavity wall 130 connected to the substrate is vertically disposed around the substrate to form a side enclosure structure.

[0037] The cover plate 200 covers the top of the cavity wall 130 and together with the substrate forms a closed cavity;

[0038] A refrigeration system is installed at the bottom of the groove 120 to control the temperature at the bottom of the groove 120.

[0039] The protrusions 110 on the upper surface of the substrate are used to support the quantum chip and provide a temperature conduction interface. The cover plate 200, together with the substrate and the annular sidewall, forms a sealed cavity to isolate external contamination. The cover plate 200 can optionally integrate an optical window to observe the chip located inside the cavity. The cooling system located in the groove 120 is used to precisely control the substrate temperature and reduce the damage to the quantum bits caused by thermal effects during long-term laser annealing.

[0040] This application provides a chip stage, which is a packaged cavity structure for placing a quantum chip undergoing laser annealing. Its core function is to provide a controllable ambient temperature to achieve precise adjustment of the quantum bit resistance, while suppressing the aging rate of the chip during long-term laser annealing. In addition, the substrate has a central protrusion 110, which increases the conduction distance of the cooling system to other parts of the cavity, thus providing a certain degree of heat preservation.

[0041] In one embodiment of this application, the surface of the boss 110 is coated with a heat dissipation medium to increase the heat dissipation of the chip.

[0042] The substrate can be made of a high thermal conductivity material, such as oxygen-free copper or diamond-coated aluminum, to accelerate heat dissipation of the quantum chip and reduce the increase in chip temperature during long-term laser annealing. Furthermore, the protrusions 110 on the upper surface of the substrate are coated with a heat dissipation medium, such as vacuum grease or pump oil, to further enhance the chip's heat dissipation effect.

[0043] In one embodiment of this application, the cavity wall 130 is connected to a vacuum valve for adjusting the vacuum level of the sealed cavity.

[0044] Specifically, the vacuum valve is connected to the cavity wall 130 via a flange. By controlling the opening and closing of the valve, the vacuum level inside the cavity can be adjusted, allowing for more precise control of the annealing process and reducing interference from impurities and gas molecules, thereby improving the annealing effect. Furthermore, by introducing a specific gas atmosphere (such as an inert gas) with a certain pressure into the cavity of the chip stage through the vacuum valve, different environmental conditions can be provided for the laser annealing process. Using an inert gas or hydrogen as the annealing atmosphere can also prevent chip material oxidation or perform interface passivation.

[0045] In one embodiment of this application, the cavity wall 130 is integrally formed with the substrate.

[0046] The cavity wall 130 and the substrate can be integrally formed by metal die casting or integrally formed ceramic packaging, which eliminates the connection seam between the cavity wall 130 and the substrate, reduces the possibility of gas leakage at the seam, and maintains the stability of the vacuum level in the cavity.

[0047] In one embodiment of this application, the cover plate 200 and the cavity wall 130 are detachably connected.

[0048] The cover plate 200 and the cavity wall 130 are detachably connected, which maintains the integrity of the closed cavity of the chip stage while providing convenience for cavity maintenance and chip replacement.

[0049] In one embodiment of this application, the detachable method includes at least one of screw connection, snap-fit ​​connection or magnetic adsorption.

[0050] Specifically, the cover plate 200 and the cavity wall 130 may have corresponding threaded holes, and are fastened together by bolts and nuts that pass through the cover plate 200 and connect to the cavity wall 130; alternatively, one end of a stud can be fixed to the cavity wall 130, and the other end can be fastened to the cover plate 200 with a nut. The cover plate 200 and the cavity wall 130 may also be equipped with cantilever beam type latches, ring latches, and push-pull type latches to facilitate the disassembly of the cover plate 200 and the cavity wall 130. Strong magnets are placed at corresponding positions on the cover plate 200 and the cavity wall 130 to achieve a magnetic connection between them.

[0051] In one embodiment of this application, the refrigeration system includes:

[0052] A semiconductor cooling chip is embedded in the bottom of the groove 120;

[0053] Liquid cooling heat sink is attached to the side of the semiconductor cooling chip furthest from the chip;

[0054] A temperature controller, embedded in the inner wall of groove 120, is used to detect the temperature of the chip and regulate the semiconductor cooling chip according to the temperature and preset temperature.

[0055] The semiconductor cooling chip utilizes the Peltier effect when energized, with one side cooling (absorbing heat) and the other side heating (releasing heat) to actively cool the chip. Embedded at the bottom of the recess 120, it ensures close and flat contact between the cold side of the cooling chip and the chip base, maximizing heat conduction efficiency and reducing thermal resistance. The liquid cooling system adheres closely to the hot side of the semiconductor cooling chip, efficiently removing heat generated on that side. The temperature controller uses a temperature sensor (such as an NTC thermistor or PT100) embedded in the inner wall of the recess 120 to monitor the chip temperature in real time. It compares the detected temperature with a user-set preset temperature and, based on the comparison result (temperature difference), adjusts the magnitude or direction of the current output to the semiconductor cooling chip (e.g., using PWM pulse width modulation) to control its cooling power, ultimately stabilizing the chip temperature at the preset value.

[0056] like Figure 2As shown, in one embodiment of this application, the cover plate 200 is provided with a light-transmitting window 210 for observation and laser beam incident.

[0057] Specifically, the light transmission window 210 is formed on the cover plate 200, directly opposite the protrusion 110 below. The light transmission window 210 is usually made of optical glass, quartz, or optical crystal (such as ZnSe, CaF2, etc.), and the light transmission window 210 is usually coated with an anti-reflection coating (AR Coating) to reduce the loss of reflected light of specific wavelengths and improve the light transmission efficiency.

[0058] like Figure 3 As shown, in one embodiment of this application, the chip stage further includes:

[0059] Water collection base 300 is used to place the substrate for condensate collection.

[0060] Specifically, the water-receiving base 300 has a protrusion 310 for supporting the aforementioned enclosed cavity and refrigeration system, collecting condensate that may be generated during the operation of the refrigeration system, and guiding it to a safe collection area (e.g., through a drain pipe), thereby preventing water accumulation from affecting electrical insulation, causing short circuits, or corroding precision components. The protrusion 310 has a horizontal threaded hole, through which the aforementioned enclosed cavity and refrigeration system are laterally tightened and fixed by a set screw, which can prevent the cavity from slipping due to the pulling of various pipes and cables during movement, thus improving overall accuracy.

[0061] Based on the same inventive concept, this utility model embodiment also proposes a laser annealing device, which has the chip stage described in any of the above features, for performing laser annealing on a chip located on the chip stage.

[0062] In this specification, references to terms such as "some embodiments" or "examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0063] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.

Claims

1. A chip carrier, characterized in that, The chip platform includes: The substrate has an upper surface and a lower surface disposed opposite to each other. The upper surface has a boss for placing a laser-annealed chip, and the lower surface has a groove. An annular cavity wall connected to the substrate is vertically disposed around the substrate to form a side enclosure structure; A cover plate, which covers the top of the cavity wall and together with the substrate, forms a closed cavity; A refrigeration system is installed at the bottom of the groove to control the temperature at the bottom of the groove.

2. The chip carrier according to claim 1, characterized in that, The surface of the boss is coated with a heat dissipation medium to increase the heat dissipation of the chip.

3. The chip carrier according to claim 1, characterized in that, The cavity wall is connected to a vacuum valve for adjusting the vacuum level of the sealed cavity.

4. The chip carrier according to claim 1, characterized in that, The cavity wall is integrally formed with the substrate.

5. The chip carrier according to claim 1, characterized in that, The cover plate is detachably connected to the cavity wall.

6. The chip carrier according to claim 5, characterized in that, The detachable method includes at least one of screw connection, snap-fit ​​connection or magnetic adsorption.

7. The chip carrier according to claim 1, characterized in that, The refrigeration system includes: A semiconductor cooling chip is embedded in the bottom of the groove; A liquid-cooled heat sink is attached to the side of the semiconductor cooling chip that is furthest from the chip. A temperature controller, embedded in the inner wall of the groove, is used to detect the temperature of the chip and regulate the semiconductor cooling chip according to the temperature and a preset temperature.

8. The chip carrier according to claim 1, characterized in that, The cover plate is provided with a light-transmitting window for observation and laser beam incidence.

9. The chip carrier according to claim 1, characterized in that, The chip platform also includes: A water-collecting base is used to hold the substrate and to collect condensate.

10. A laser annealing apparatus, characterized in that, The laser annealing equipment has a chip stage as described in any one of claims 1-9.

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