Display circuit, display panel and display device

Abstract

The application discloses a display circuit, a display panel and a display device, and mainly relates to the technical field of display, and the display circuit at least comprises two groups of pixel array groups, each group of pixel array groups comprises a pixel unit, a first data line, a second data line, a first scanning line and a first group of selection active switches; the pixel units are arranged in a matrix mode; the first data line and the first scanning line are arranged in a vertical and horizontal interlaced mode; the first data line in different groups of pixel array groups is connected; the pixel unit comprises a pixel active switch and a pixel electrode; in each group of pixel array groups, the gate of the pixel active switch is connected with the first scanning line, the source of the pixel active switch is connected with the second data line, the drain of the pixel active switch is connected with the pixel electrode, the source of the first group of selection active switches is connected with the first data line, and the drain of the first group of selection active switches is connected with the second data line; and the first data line is used for receiving a data voltage. Through the above design, the power consumption of the display circuit is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display circuit, display panel, and display device. Background Technology

[0002] As an electronic product, power consumption is undoubtedly a crucial indicator of the quality of an LCD panel. The total power consumption of a display includes the power consumption of the backlight, the internal power consumption of each chip during operation, and the power consumption generated by the driving circuitry driving the pixels within the panel for charging and discharging.

[0003] However, some unnecessary power consumption occurs during the charging and discharging process of the pixel unit in the driving plane of the driving circuit. Therefore, how to reduce this power consumption has become an urgent technical problem to be solved. Utility Model Content

[0004] The purpose of this application is to provide a display circuit, display panel, and display device that reduce the power consumption of the display circuit.

[0005] This application discloses a display circuit, which includes at least two sets of pixel array groups. Each set of pixel array groups includes pixel units, a first data line, a second data line, a first scan line, and a first set of active selection switches. The pixel units are arranged in a matrix, and the first data line and the first scan line are arranged in a crisscross pattern. The first data lines in different sets of pixel array groups are connected. The pixel unit includes a pixel active switch and a pixel electrode. In each group of the pixel array, the gate of the pixel active switch is connected to the first scan line, the source of the pixel active switch is connected to the second data line, and the drain of the pixel active switch is connected to the pixel electrode. The source of the first group of active switches is connected to the first data line, and the drain of the first group of active switches is connected to the second data line. The first data line is used to receive data voltage.

[0006] Optionally, the scanning direction along the first scan line is defined as the first direction, and the gate of the first group of active selection switches is connected to the last first scan line in the pixel array group along the first direction.

[0007] Optionally, the pixel array group further includes a second scan line, which is connected to the gate of the first group of active selection switches.

[0008] Optionally, each group of the pixel arrays includes two rows of pixel units.

[0009] Optionally, each group of the pixel arrays includes four rows of the pixel units.

[0010] Optionally, each group of pixel arrays further includes a second group of active selection switches, wherein the source of the second group of active selection switches is connected to the first data line, and the drain of the second group of active selection switches is connected to the second data line. The gate of the second set of active selection switches is connected to the first scan line along the first direction in the pixel array group.

[0011] Optionally, the display circuit further includes a group connection active switch and a third scan line, wherein the source and drain of the group connection active switch are respectively connected to the second data line in the two groups of the pixel array, and the gate of the group connection active switch is connected to the third scan line.

[0012] Optionally, each group of the pixel array includes two rows of pixel units, defined as a first row of pixel units and a second row of pixel units, respectively; the second scan line is located between the first row of pixel units and the second row of pixel units.

[0013] This application also discloses a display panel, which includes a pixel substrate and a display circuit, wherein the display circuit is disposed on the pixel substrate.

[0014] This application also discloses a display device, which includes a display panel.

[0015] Compared to existing display circuit solutions, the display circuit of this application groups the pixel units into at least two pixel array groups. The second data line connected to the pixel active switch in each pixel array group is then connected to the first data line via a first set of active selection switches. The data line voltage can then sequentially enter the pixel active switch through the first data line, the first set of active selection switches, and the second data line. When refreshing the screen, the first set of active selection switches in one pixel array group is first turned on, while the first set of active selection switches in the other pixel array groups remains closed. Then, each row of pixel active switches in one pixel array group is turned on sequentially to charge the pixel electrodes. Because a first set of active selection switches is added to each pixel array group, the data voltage will not enter the second data line of the other pixel array groups, thus preventing the pixel active switches in the other pixel array groups from consuming voltage and reducing the power consumption of the display circuit. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of a display device according to an embodiment of this application; Figure 2 This is a schematic diagram of a display panel according to an embodiment of this application; Figure 3 This is a schematic diagram of a first display circuit according to the first embodiment of this application; Figure 4 This is a schematic diagram of a time-delay active switch according to the first embodiment of this application; Figure 5 This is a schematic diagram of a second display circuit according to the first embodiment of this application; Figure 6 This is a schematic diagram of the circuit timing corresponding to the second type of display circuit in the first embodiment of this application; Figure 7 This is a schematic diagram of the second set of active selection switches according to the first embodiment of this application; Figure 8 This is a schematic diagram of a first type of group-connected active switch according to the first embodiment of this application; Figure 9 This is a schematic diagram of a display circuit according to a second embodiment of this application.

[0017] Among them, 10 is a display device; 20 is a display panel; 30 is a pixel substrate; 40 is a first direction; 50 is a display circuit; 100 is a pixel array group; 110 is a pixel unit; 111 is a pixel active switch; 112 is a pixel electrode; 113 is a first row pixel unit; 114 is a second row pixel unit; 121 is a first data line; 122 is a second data line; 131 is a first scan line; 132 is a second scan line; 141 is a first group selection active switch; 142 is a second group selection active switch; 210 is a group connection active switch; 220 is a third scan line; 300 is a liquid crystal layer; 400 is a color filter substrate; 410 is a color filter substrate; 420 is a sub-color resist; 430 is a common electrode layer; and 600 is a delay active switch. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0020] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0023] Figure 1 This is a schematic diagram of a display device according to an embodiment of this application, as shown below. Figure 1 As shown, this application discloses a display device 10, which includes a display panel 20.

[0024] The display panel 20 includes, for example, a TN (Twisted Nematic) display panel 20, an IPS (In-Plane Switching) display panel 20, a VA (Vertical Alignment) display panel 20, and an MVA (Multi-Domain Vertical Alignment) display panel 20. Of course, it can also be other types of display panels 20, such as an OLED (Organic Light-Emitting Diode) display panel 20 and an electronic paper display panel 20, all of which are applicable to this application.

[0025] Figure 2 This is a schematic diagram of a display panel according to an embodiment of this application, as shown below. Figure 2 As shown, this application also discloses a display panel 20, which includes a pixel substrate 30 and a display circuit 50, wherein the display circuit 50 is disposed on the pixel substrate 30.

[0026] Taking the display panel 20 as an example of a TN display panel 20, the display panel 20 further includes a liquid crystal layer 300 and a color filter substrate 400. The color filter substrate 400 and the array substrate 20 are disposed in a cell, and the liquid crystal layer 300 is disposed between the array substrate 20 and the color filter substrate 400.

[0027] An electric field is formed between the common electrode layer 430 on the array substrate 20 and the color filter substrate 400, which drives the liquid crystal in the liquid crystal layer 300 to deflect, thereby displaying the image.

[0028] The color filter substrate 400 includes a color filter substrate 410 and a plurality of sub-color resists 420. The plurality of sub-color resists 420 are disposed on the color filter substrate 410. The common electrode layer 430 is also disposed on the color filter substrate 410, and the sub-color resists 420 correspond one-to-one with the pixel units 110 on the array substrate 20.

[0029] This application also discloses a display circuit 50, which can be used in the display panel 20 described above. Regarding the display circuit 50, this application provides the following design, which is specifically described through several embodiments: Example 1: Figure 3 This is a schematic diagram of a first display circuit according to the first embodiment of this application, as shown below. Figure 3As shown, this application also discloses a display circuit 50, which includes at least two sets of pixel array groups 100. Each set of pixel array groups 100 includes pixel units 110, a first data line 121, a second data line 122, a first scan line 131, and a first set of active selection switches 141. The pixel units 110 are arranged in a matrix, and the first data line 121 and the first scan line 131 are arranged in a crisscross pattern. The first data lines 121 in different sets of pixel array groups 100 are connected.

[0030] The pixel unit 110 includes a pixel active switch 111 and a pixel electrode 112. In each pixel array group 100, the gate of the pixel active switch 111 is connected to the first scan line 131, the source of the pixel active switch 111 is connected to the second data line 122, and the drain of the pixel active switch 111 is connected to the pixel electrode 112. The source of the first group of active selection switches 141 is connected to the first data line 121, and the drain of the first group of active selection switches 141 is connected to the second data line 122. The first data line 121 is used to receive data voltage.

[0031] The first data line 121 is used to receive data voltage, which is used to input to the pixel electrode 112, so that an electric field is formed between the pixel electrode 112 and the common electrode layer 430. It can be understood that the connection of the first data line 121 in different groups of pixel array groups 100 refers to the connection of one first data line 121 in one group of pixel array groups 100 to one first data line 121 in another group of pixel array groups 100, so that the pixel voltage from one source driver chip can be input to each group of pixel array groups 100.

[0032] Furthermore, the second data lines 122 in the pixel array groups 100 within different groups are not connected. This prevents the data voltage on the first data line 121 from entering the second data line 122 in the next pixel array group 100 through the second data line 122 when the first active selection switch 141 in the first pixel array group 100 is turned on.

[0033] Compared to existing display circuit solutions, the display circuit 50 of this application groups the pixel units 110 into at least two pixel array groups 100. Then, the second data line 122 connected to the pixel active switch 111 of each pixel array group 100 is connected to the first data line 121 through the first group selection active switch 141. The data line voltage can then enter the pixel active switch 111 in sequence through the first data line 121, the first group selection active switch 141, and the second data line 122.

[0034] When refreshing the screen, the first set of active selection switches 141 in one pixel array group 100 is turned on first, while the first set of active selection switches 141 in the other pixel array groups 100 remain closed. Then, the active pixel switches 111 in each row of one pixel array group 100 are turned on in sequence to charge the pixel electrodes 112. Since a first set of active selection switches 141 is added in each pixel array group 100, the data voltage will not enter the second data line 122 of the other pixel array groups 100, thereby avoiding the voltage consumption of the active pixel switches 111 in the other pixel array groups 100 and reducing the power consumption of the display circuit 50.

[0035] The voltage consumption of the pixel active switch 111 is mainly due to the parasitic capacitance generated between the source and drain of the pixel active switch 111 when the pixel active switch 111 is in the off state, as well as the parasitic capacitance generated between the gate and source of the pixel active switch 111.

[0036] In this embodiment, the first set of active selection switches 141 is connected to the first scan line 131 of the last row of pixel units 110 in a pixel array group 100. Specifically, the scanning direction along the first scan line 131 is defined as the first direction 40, and the gate of the first set of active selection switches 141 is connected to the last first scan line 131 in the pixel array group 100 along the first direction 40.

[0037] In this way, there is no need to add a scan line to control the first set of active selection switches 141. Moreover, when the first set of active selection switches 141 is turned on, the first set of active selection switches 141 and the pixel active switches 111 in the last row of pixel units 110 in a set of pixel array groups 100 will also be turned on, so that the pixel electrodes 112 in the last row of pixel units 110 in a set of pixel array groups 100 are pre-charged.

[0038] For example, each group of pixel arrays 100 in the first display circuit 50 may include two rows of pixel units 110.

[0039] Each pixel array group 100 includes two rows of pixel units 110. When charging the two rows of pixel units 110 in the first pixel array group 100, the fluctuation of data voltage will not affect the active pixel switches 111 of the two rows of pixel units 110 in other pixel array groups 100. This avoids the voltage consumption of the active pixel switches 111 of the two rows of pixel units 110 in other pixel array groups 100, thereby reducing the power consumption of the display circuit 50.

[0040] Figure 4This is a schematic diagram of a time-delay active switch according to the first embodiment of this application, as shown below. Figure 4 As shown, since the first set of active selection switches 141 and the last row of pixel units 110 are connected to the same first scan line 131, when the first set of active selection switches 141 is turned on, the pixel active switches 111 in the last row of pixel units 110 will also be turned on. Therefore, when the first row of pixel units 110 is charging, the data voltage will also be charged to the pixel electrodes 112 in the last row of pixel units 110. This results in a difference in charging efficiency between the pixel electrodes 112 in the first row of pixel units 110 and the pixel electrodes 112 in the last row of pixel units 110, leading to display abnormalities.

[0041] This application also adds a delayed active switch 600 to the front end of the pixel active switch 111 in the last row of pixel units 110. Thus, one pixel active switch 111 is provided in the first row of pixel units 110, and the delayed active switch 600 and the pixel active switch 111 are connected in series in the last row of pixel units 110. Specifically: Each pixel array group 100 includes two rows of pixel units 110, defined as a first row of pixel units 113 and a second row of pixel units 114, respectively. The second row of pixel units 114 is located on the first direction 40 of the first row of pixel units 113. The gate of the first group of active selection switches 141 is connected to the same first scan line 131 as the active pixel switch 111 in the second row of pixel units 114.

[0042] The pixel array group 100 further includes a delay active switch 600, the source of which is connected to the second data line 122, and the drain of which is connected to the source of the pixel active switch 111 in the second row pixel unit 114; and the gate of the delay active switch 600 and the gate of the pixel active switch 111 in the second row pixel unit 114 are connected to the same scan line.

[0043] This makes the charging efficiency of the pixel electrode 112 in the first row of pixel units 113 closer to that of the pixel electrode 112 in the second row of pixel units 114, thereby reducing or eliminating display abnormalities caused by the difference in charging efficiency between the pixel electrode 112 in the first row of pixel units 113 and the pixel electrode 112 in the second row of pixel units 114.

[0044] Figure 5 This is a schematic diagram of a second display circuit according to the first embodiment of this application. Figure 6 This is a schematic diagram of the circuit timing corresponding to the second type of display circuit in the first embodiment of this application, as shown below. Figures 5-6As shown, unlike the first type of display circuit 50, each group of pixel arrays 100 in the second type of display circuit 50 includes four rows of pixel units 110.

[0045] Each pixel array group 100 includes four rows of pixel units 110. When charging the four rows of pixel units 110 in the first pixel array group 100, fluctuations in data voltage will not affect the active pixel switches 111 of the four rows of pixel units 110 in other pixel array groups 100. This avoids the voltage consumption of the active pixel switches 111 of the four rows of pixel units 110 in other pixel array groups 100 and reduces the power consumption of the display circuit 50.

[0046] Compared to the first display circuit 50, this application sets each pixel array group 100 to include four rows of pixel units 110. By increasing the number of rows of pixel units 110 in each pixel array group 100, the total number of pixel array groups 100 can be reduced. Consequently, the number of first active selection switches 141 will also be reduced, thereby optimizing the control method. Moreover, the total energy consumption of the first active selection switches 141 in the display circuit 50 is also lower.

[0047] See Figure 6 G1 represents the opening time of the first scan line 131 of the pixel unit 110 in the first row of the pixel array group 100, G2 represents the opening time of the first scan line 131 of the pixel unit 110 in the second row of the pixel array group 100, G3 represents the opening time of the first scan line 131 of the pixel unit 110 in the third row of the pixel array group 100, G4 represents the opening time of the first scan line 131 of the pixel unit 110 in the fourth row of the pixel array group 100, and S represents the output of the data voltage. When G4 is open, the data voltage output is the data line voltage required by the pixel unit 110 in the first row. After G1 is closed, the data voltage output is the data line voltage required by the pixel unit 110 in the second row. After G2 is closed, the data voltage output is the data line voltage required by the pixel unit 110 in the third row. After G3 is closed, the data voltage output is the data line voltage required by the pixel unit 110 in the fourth row. This makes the charging process of the display circuit 50 of this application not significantly changed, the implementation cost is low, and it is easy to implement.

[0048] Figure 7 This is a schematic diagram of the second set of active selection switches according to the first embodiment of this application, as shown below. Figure 7As shown, each pixel array group 100 further includes a second set of active selection switches 142. The source of the second set of active selection switches 142 is connected to the first data line 121, and the drain of the second set of active selection switches 142 is connected to the second data line 122. The gate of the second set of active selection switches 142 is connected to the first scan line 131 along the first direction 40 in the pixel array group 100.

[0049] In this way, when a group of pixel arrays 100 is refreshed sequentially, the second active selection switch 142 will first turn on the first row of pixel units 110, so that the data voltage that enters in advance can precharge the first row of pixel units 110. While charging the first row of pixel units 110, it can also precharge one or more rows of pixel units 110 in the second, third and fourth rows. This will prevent the situation where the first row of pixel units 110 in each group of pixel arrays 100 cannot be precharged when precharging is required.

[0050] Figure 8 This is a schematic diagram of the first type of group connection active switch according to the first embodiment of this application, as shown below. Figure 8 As shown, this application also selectively connects the second data lines 122 of different pixel array groups 100 by setting the group connection active switch 210 and the third scan line 220. For ease of explanation, taking each pixel array group 100 as an example, which includes four rows of pixel units 110, specifically: The display circuit 50 further includes a group connection active switch 210 and a third scan line 220. The source and drain of the group connection active switch 210 are respectively connected to the second data line 122 in the two groups of pixel arrays 100, and the gate of the group connection active switch 210 is connected to the third scan line 220.

[0051] The source and drain of the group connection active switch 210 are respectively connected to the second data line 122 in the two groups of pixel array groups 100. For example, the source and drain of the group connection active switch 210 are respectively connected to the second data line 122 in the same column in the two groups of pixel array groups 100. In this way, when it is necessary to control the four rows of pixel units 110 in each group of pixel array groups 100, the third scan line 220 does not open the gate of the group connection active switch 210, so that the four rows of pixel units 110 can be controlled as a group of pixel array groups 100.

[0052] When it is necessary to control eight rows of pixel units 110 as a group of pixel arrays 100, first turn on the active group connection switch 210 between the first group of pixel arrays 100 and the second group of pixel arrays 100. Then, the four rows of pixel electrodes 112 in the first group of pixel arrays 100 and the four rows of pixel electrodes 112 in the second group of pixel arrays 100 can be charged sequentially. Then, turn on the active group connection switch 210 between the third group of pixel arrays 100 and the fourth group of pixel arrays 100. Then, the four rows of pixel electrodes 112 in the third group of pixel arrays 100 and the four rows of pixel electrodes 112 in the fourth group of pixel arrays 100 can be charged sequentially. This realizes the control of eight rows of pixel units 110 as a group of pixel arrays 100, reducing the control difficulty.

[0053] Furthermore, this allows for the implementation of four rows of pixel units 110 as a pixel array group 100, or eight rows of pixel units 110 as a pixel array group 100, or twelve rows of pixel units 110 as a pixel array group 100, or sixteen rows of pixel units 110 as a pixel array group 100, and so on, without further explanation.

[0054] Moreover, this allows the pixel array group 100 to be controlled by eight rows for a period of time, and then switched to a second pixel array group 100 consisting of four rows plus eight rows, thereby avoiding the problem of reduced lifespan caused by the continuous long-term operation of all the first group selection active switches 141.

[0055] Example 2: Figure 9 This is a schematic diagram of a display circuit according to a second embodiment of this application, as shown below. Figure 9 As shown, unlike the first embodiment, this embodiment provides a second scan line 132 to individually control the first group of active selection switches 141. Specifically, the pixel array group 100 further includes a second scan line 132, which is connected to the gate of the first group of active selection switches 141. For ease of explanation, this embodiment uses two rows of pixel units 110 in each pixel array group 100 as an example. Compared to the solution in the first embodiment, this embodiment adds a second scan line 132 to control the first group of active selection switches 141 separately. This prevents the data voltage from being pushed into the last row of pixel units 110 when charging the pixel units 110 in the previous row, thereby further reducing the power consumption of the display circuit 50.

[0056] Furthermore, after adding the second scan line 132, the second scan line 132 can be set between the two rows of pixel units 110. Specifically, each group of pixel arrays 100 includes two rows of pixel units 110, which are defined as the first row of pixel units 113 and the second row of pixel units 114, respectively; the second scan line 132 is located between the first row of pixel units 113 and the second row of pixel units 114.

[0057] For example, the first data line 121 and the second data line 122 that charge the pixel electrode 112 are located to the left of the pixel electrode 112. The first scan line 131 that turns on the pixel active switch 111 connected to the pixel electrode 112 is located above the pixel electrode 112. Then, the second scan line 132 is located between the first row of pixel units 113 and the second row of pixel units 114. That is, the second scan line 132 is located between the pixel electrodes 112 in the first row of pixel units 113 and the pixel electrodes 112 in the second row of pixel units 114. This makes the pixel electrodes 112 of the two rows of pixel units 110 in each pixel array group 100 respectively on both sides of the second scan line 132. Thus, the pixel electrodes 112 of the two rows of pixel units 110 in each pixel array group 100 are simultaneously affected by the second scan line 132, thereby making the electric field of the entire display circuit 50 more balanced.

[0058] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0059] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0060] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A display circuit, characterized in that, The display circuit includes at least two sets of pixel array groups. Each set of pixel array groups includes pixel units, a first data line, a second data line, a first scan line, and a first set of active selection switches. The pixel units are arranged in a matrix, and the first data lines and the first scan lines are arranged in a crisscross pattern. The first data lines in different sets of pixel array groups are connected. The pixel unit includes a pixel active switch and a pixel electrode. In each group of the pixel array, the gate of the pixel active switch is connected to the first scan line, the source of the pixel active switch is connected to the second data line, and the drain of the pixel active switch is connected to the pixel electrode. The source of the first group of active switches is connected to the first data line, and the drain of the first group of active switches is connected to the second data line. The first data line is used to receive data voltage.

2. The display circuit according to claim 1, characterized in that, The scanning direction along the first scan line is defined as the first direction, and the gate of the first set of active selection switches is connected to the last first scan line in the pixel array group along the first direction.

3. The display circuit according to claim 1, characterized in that, The pixel array group further includes a second scan line, which is connected to the gate of the first group of active selection switches.

4. The display circuit according to any one of claims 2 and 3, characterized in that, Each group of the pixel arrays comprises two rows of pixel units.

5. The display circuit according to any one of claims 2 and 3, characterized in that, Each group of the pixel arrays comprises four rows of pixel units.

6. The display circuit according to claim 2, characterized in that, Each pixel array group further includes a second set of active selection switches, the source of the second set of active selection switches being connected to the first data line, and the drain of the second set of active selection switches being connected to the second data line; The gate of the second set of active selection switches is connected to the first scan line along the first direction in the pixel array group.

7. The display circuit according to claim 5, characterized in that, The display circuit further includes a group connection active switch and a third scan line. The source and drain of the group connection active switch are respectively connected to the second data line in the two groups of the pixel array, and the gate of the group connection active switch is connected to the third scan line.

8. The display circuit according to claim 3, characterized in that, Each group of the pixel arrays includes two rows of pixel units, defined as a first row of pixel units and a second row of pixel units, respectively; the second scan line is located between the first row of pixel units and the second row of pixel units.

9. A display panel, characterized in that, The display panel includes a pixel substrate and a display circuit as described in any one of claims 1-8, wherein the display circuit is disposed on the pixel substrate.

10. A display device, characterized in that, The display device includes the display panel as described in claim 9.

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